Based on TLP and vf-TLP test results, ESDEMC will generate a device model if requested. Positive and negative IV characteristics will be matched with TLP results, and transient vf-TLP turn-on behavior will be modelled at various pulse levels. Board-level modelling may also be possible, but it should be discussed prior to testing.  Advanced Design System (ADS) and Spice are the standard simulation programs used to generate these models, and models can be made “classified” when intellectual property is a concern. This allows users to share their device models with others without revealing the internal model components.