PB2016.07 System-Level Modeling Methodology of ESD Cable Discharge to Ethernet Transceiver Through Magnetics

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Abstract—When a charged cable is plugged into an Ethernet connector, a cable discharge event (CDE) will occur. Ethernet transceiver pins are often affected by CDE as they are usually unshielded. The discharge current couples via the transformer and common mode chokes to the physical layer-integrated circuit and may damage it. This paper describes a methodology for CDE system-level modeling in SPICE taking the cable geometry into account via full-wave modeling and cross-sectional analysis. A charged cable model, a nonlinear magnetics model, an Ethernet transceiver pin model, and the traces in the system are combined to create a complete model. An Ethernet system suffering cable discharge was selected to illustrate the methodology. The simulation is compared to measurements.

Index Terms—Cable discharge event (CDE), electrostatic discharge, Ethernet transmission line pulse (TLP), system efficient ESD design (SEED).


Cable discharge event (CDE) robustness is a quality issue which network equipment designers should consider. Studies in [1]–[4] directly or indirectly determine the expected charge voltage, and studies in [5]–[7] give examples of possible discharge waveforms for a given voltage. Two CDE-producing situations can clearly be distinguished. The first is through triboelectric charging by pulling a cable over a surface. The authors of [2] reported voltages up to 1.7 kV in a setup that pulls cables from one spool to another while sliding the cable over insulating surfaces. In proprietary industry test standards, the use of 200 m LAN cable charged to 2 kV is suggested. The second scenario can be illustrated as follows. A person carries a laptop that is charged and inserts a LAN cable into the laptop. The voltage levels accumulated by a person can be derived from triboelectric charging by walking, sitting, and standing up from chairs or removing a garment [8]–[10] and can easily reach 10 kV or more.

When a charged cable is plugged into an Ethernet connector, the voltage and consequential current can damage the transformer, common mode chokes, and especially the Ethernet transceivers [1]. Because of the length of LAN cables, CDE discharges can be quite long and have the potential to stress the I/O more than those discharges described by the HBM or the IEC 61000-4-2 discharge model [4]. Most CDE will occur at voltages below 5 kV, leading to shorter rise rimes compared to the 0.85 ns of the IEC 61000-4-2 standard. These shorter rise times may require shorter turn on performance of the electrostatic discharge (ESD) protection circuit.

The electrostatic discharge association is now working on a CDE standard. However, no published CDE standard exits and complying with the system level IEC 61000-4-2 standard may not ensure sufficient robustness of a device or a system against CDE.

In order to characterize interface protection elements, the authors of many publications simulate or experimentally emulate cable discharge with long transmission lines [3]–[7]. The difficulty of creating a CDE standard test is complicated by the many parameters which influence the discharge, such as the charging and discharging mechanisms, pin mating sequence, cable geometry, height of the cable above ground, and the load conditions. In [4] and [11], CDE charging and discharging mechanisms were introduced. In [11], the effects of the pin mating sequence with respect to injecting a common and/or differential mode current were discussed. In [12], some effects of cable geometry were explained by a multibody capacitance model. Previous publications provide a basic understanding of the cable discharges, both from the theoretical and measurement’s point of view [11]– [13]. For system-level investigation, both a cable charging and discharging model need to be included. As many conductors are involved in LAN CDE, the model must be more complex than a single transmission line discharge scenario such as a transmission line pulse (TLP).

The Ethernet magnetic circuit is used to protect against noise, suppress common mode, and to provide galvanic isolation [14] and can come in several different configurations. The failure level of the PHY will depend on this magnetic module [15], which means that this magnetic circuit needs to be modeled correctly to understand its role in protecting the PHY. The performance of the magnetics depends not only on the winding inductances, but also on parasitic parameters such as leakage inductances and interwinding capacitances. In [16] and [17], the authors demonstrate examples linear magnetic modeling for such transformers. However, due to the large currents during an ESD event, nonlinear effects such as core saturation must be considered. Chiefly, the saturation of the magnetic cores can limit the amount of energy which is coupled into the transceiver circuit [18]. This requires a saturable B–H curve-based model [19], [20].

Finally, an Ethernet IC transceiver pin behavioral model is needed to predict its failure level during a discharge [21]. Such a model should be able to reproduce the VI curve behavior such that it can be used in simulation to model the pin [22]. A sudden strong change of the VI curve or an increase of the leakage current measured by a source measurement unit (SMU) is often regarded as an indication for the failure of the DUT [23]. The very fast transmission line pulse (VF-TLP) has been established as the best choice for the characterization of such VI curves and damage thresholds as it can also resolve the DUT behavior in the first nanoseconds of the stress stimulus.

This paper follows the concept of system efficient ESD design (SEED) [24] and uses a cable discharge system as an example to illustrate how to build the complete system-level model. Section II introduces the selected cable discharge system. Each part of the system modeling methods and results are shown in Section III. The models of each part were combined as a system circuit, and the comparison of simulation and measurement results is shown in Section IV. Section V discusses three situations which are not shown in the model. System level saturation situations, CDE versus ESD simulator discharging, and shielded cable influences are discussed in this section. Section VI presents the analysis of this modeling methodology.


As shown in Fig. 1, the selected cable discharge system includes: 1) charged Cat 5 cable; 2) magnetic group with Ethernet connector; 3) interconnection between magnetics and Ethernet PHY IC; and 4) PHY IC transceiver media-dependent interface (MDI) pins. The primary-side center tap of the magnetics is connected to a Bob Smith termination circuit [25] which consists of a 75 Ω resistor and a 1 nF high voltage capacitor. This termination circuit is sometimes implemented using different component values. For example, if power over Ethernet is provided, the capacitor value may be much larger. Furthermore, many center taps from different pairs or even cables may connect together and share the same termination circuit. In this case, the secondary-side center tap is connected to ground through a 1 nF capacitor.

As this paper does not attempt to examine the specific charging processes which can lead to CDE, we simply assume that the cable was charged in common mode based on [2]; i.e., all eight conductors had the same voltage with respect to a ground reference plane. The first pin that contacts initiates a current flow into the LAN connector. This is referred to as a common mode discharge, as the current magnitude depends on the common mode impedance of the cable to ground and the common mode termination impedance on the other end of the cable (open circuit, for an unconnected cable). Although already described in [11], it is important to be reminded of the effect of PIN sequencing during the discharge of an unshielded LAN cable. In CDE, at least two different modes can be initiated by the second pin that mates. The second pin can either be from the same twisted pair as the first pin that contacted, or from another twisted pair. If it is from the same pair, a differential mode current will be initiated and the first pin will be the main return path of a differential current on this pair. In this case, the common mode chokes cannot suppress this differential mode current. Most discharge current will transfer to the PHY IC pins through the magnetics. As the differential discharge case forms the worst case scenario, it was selected as the basis for modeling.


This cable discharge arrangement contains four parts; each part was simulated and tested separately, and then combined in the Allegro Design Entry CIS 16.6 SPICE solver.

A. Charged Cable Model

The charged cable model was built using CST Cable Studio’s hybrid method. The simulator analyzes the cable geometry by cross-sectional analysis and then places it into a 3-D solver to determine the effect of the surrounding on the cable currents. A geometric representation of the four twisted wire pairs (TWPs) of a Cat 5e cable 5 cm above the reference ground plane was first created and then the bundled to create the unshielded twisted pair geometry shown in Fig. 2. Placing a port on each side of all eight wires in the cable geometry results in a 16-port S-parameter matrix which represents the simulated cable. In practice, the wire pairs are twisted more closely together than in the simulated model but we are not aware of a method within CST to create such a closely bundled cable. Because the results shown in Sections III and IV indicate that the resulting error is acceptable, the super twisting of the cable bundle was not considered.

As the next step, the 16-port S-parameter file was converted to a circuit file using a commercial macro model generation tool [26]. This circuit file is suitable for the SPICE simulation as a 32 pin component.

Fig. 3 shows the cable charging and discharging circuit model. To experimentally verify the model, the ES631-LAN Ethernet CDE evaluation system provided by ESDEMC LLC was used. To reflect the inner structure of the CDE tester [27], two cables needed to be modeled. The 5.6 m long section is the external DUT and the 0.4 m long cable section is part of the CDE tester.

The cable charge voltage is set by the initial condition. The cable discharge sequence is determined by the voltage control switch S1 and the termination resistors on the right side in Fig. 3.

Although all wires are charged to the same voltage prior to the first contact, there will be a differential voltage after the first contact. This differential voltage will drive the possibly damaging differential current if the second pin that mates belongs to the same pair. The amount of the voltage depends on the ratio of the well-controlled wire-to-wire capacitance Cww of a pair and the capacitance of the second wire to ground Cwgnd . A simplified capacitive divider is shown in Fig. 4 to illustrate the charge redistribution after the first pin contacts. This is further analyzed in [28]. Measurements show that cables routed in a cable tray may have a capacitance ratio of Cww : Cwgnd up to 1:0.75. Thus, a common mode voltage caused by triboelectric charging of 2400 V will lead to a differential voltage of 1000 V after the first pin discharge.

To verify the cable model, simulated and measured results were compared for second pin discharge cases. The precharge differential voltage of the wire was set to 1 kV, and pin 1 and 2 (see Fig. 3) were shorted together to allow for differential current flow. The discharge current was measured using a CT2 current probe inside the CDE tester.

The results are shown in Fig. 5 together with currents simulated using a simple differential pair model having optimized per unit length parameters. This additional simulation has been performed as other publications have used a transmission line as approximation of the cable discharge pulse. The model consists of two differential lossy transmission lines connected in series. The long transmission line corresponds to the 5.6 m charge cable. Another short differential transmission line corresponds to the 0.4 m cable. The long transmission line was precharged to 1 kV. The switch is placed at the connection point of these transmission lines, similar to the cable model. The lossy transmission lines were defined by their per unit length parameters. In the model, L = 400 nH, C = 40 pF, R = {0.001 sqrt(2 s)}, G = 0 are used. R uses the Laplace variable “s” to model attenuation as a function of frequency. L and C have been derived from the propagation velocity and the characteristic impedance; the loss has been optimized for best match to the full cable model data. One can also use the method mentioned in [29] to create a twisted pair model.

As Fig. 5 shows, the differential currents which determine the discharge currents match well. The frequency of the current waveform oscillation is directly related to the cable propagation velocity and length. In this case, the 6 m total cable length corresponds to a pulse width of 60 ns. The measured data show more damping than the simulated data which is likely caused by additional losses in the CDE tester such as the discharge relays. From a damage point of view, the rise time, peak current, and duration of the first pulse measurement and simulation match.

However, when comparing the simulation using a differential transmission line to the multiwire model and additionally considering practical aspects in test implementation, one will realize that the differential transmission line is only a very good model for one specific case, and it loses generality if other pin sequences are analyzed.

For example, the first pin discharge current strongly depends on the height of the cable above ground; thus, it would require a TLP of adjustable characteristic impedance. A second case which is difficult to model by the differential transmission line is when the second pin to mate is part of a different twisted pair than the first. Experimentally, there is a fundamental difference between using a TLP to discharge to a pin and a differential transmission line discharge. The TLP is usually ground referenced; thus, it requires a high voltage pulse balun to attach the TLP such that a differential current is injected. Therefore, a full LAN CDE tester which has eight individual relays to model the pin mating sequences is preferable.

B. Magnetic Group Model

As shown in [15], the CDE performance depends on the type of Ethernet magnetics used in a product. A typical Ethernet magnetic circuit consists of a center tapped 1:1 isolation transformer and common mode chokes at the cable side and/or the physical (PHY) IC side. In the system investigated, the magnetic group contained three such magnetic components: a three-wire common mode choke at the PHY side, a balanced-to-balanced 1:1 transformer, and a two-wire common mode choke at the cable side (see Fig. 1). The magnetics are made from twisted wires, which form a twisted pair transmission line which is wrapped around a core (see Fig. 6). The 1:1 transformer was selected to illustrate this construction method. The Ethernet common mode chokes were created using the same method.

A linear 1:N transformer model usually contains parameters such as: primary and secondary winding inductance, primary and secondary winding capacitance, core loss resistance, leakage inductance, interwinding capacitance, primary and secondary loss resistance, among other characteristics.

Using a VNA and LCR meter, we obtained the linear parameters. Transformer linear parameter measurement theory and method are described in [30]. By measuring the transformer’s S-parameters, primary winding inductance L1 , primary winding capacitance C1 , core loss resistance RC , leakage inductance L5 , and interwinding capacitance C can be estimated by the equations in Table I. Primary and secondary loss resistance was obtained by measuring the resistance of the primary and secondary winding by LCR meter.

The B–H curve is needed to model the transformer’s nonlinear behavior. A measurement of the primary inductance L1 under different dc-bias currents is used to capture the change of the inductance as a function of dc current. To obtain the B–H curve, the initial permeability μi of the transformer toroidal core was determined from the initial inductance, the core size, and the number of turns (which is obtained from dissecting a transformer).

Allegro Design Entry CIS allows the user to define the magnetic core based on the Jiles–Atherton model [31] by directly importing the measured B–H curve data points to the model editor. Fig. 7 shows the B–H curve of the transformer core and the resultant nonlinear model.

The next step combines the two common mode choke models with the transformer model. The verification was performed in time domain using a TLP as the source (see Fig. 8). An oscilloscope was used to capture the output voltage at 50/100 Ω single/differential load and the input current is measured using a CT-2 probe. As the ac termination provides an additional current path in the real world, it was also added to the test circuit during the verification.

the verification. Fig. 9 compares simulation and measurement results for the input-side currents and the output-side voltages. At low-source voltage levels, the magnetic behavior is linear. The magnetics transfers the TLP pulse to the output side without distortion. However, as the injection source value increases, the nonlinearities begin to manifest. Saturation was first observed when the internal voltage source of the TLP is at approximately 600 V. At the onset of core saturation, the input current rapidly increases while the output voltage drops. Higher charge voltages lead to an earlier onset of saturation.

A comparison of the modeled and measured voltage and current waveforms shows very similar behaviors especially for the peak values and saturation onset time. Some differences are visible on the falling edges which could be explained by variation in material parameters from sample to sample, by the unmolded magnetic hysteresis, or similarly neglected frequency-dependent transformer parameters. Finally, it is known that even within one magnetic, the wire pairs have somewhat different behaviors, potentially due to subtle asymmetries in the geometry which can also contribute to differences between the real-world measurement and highly symmetric transformer equivalent circuit.

From the comparison of the simulation and measurements shown in Fig. 9, it can be seen that 100 ns 600 V excitation pulses inject 3 A into the primary side of the transformer and trigger saturation at 70% of the pulse width. Besides core material and size, the transformer saturation also depends on the secondary signals, but change to much lower impedances once the ESD protection circuits are triggered. Therefore, in order to simulate the system correctly, the transceiver pin impedances need to known side load. In the setup shown in Fig. 8, if the load was changed to 5 Ω saturation appears from 1400 V source voltage. In the application, the transformer is loaded by the Ethernet transceiver pins which provided a 50 Ω input impedance for in-band voltage.

C. Transceiver Pin Model

The PHY IC transceiver pin model consists of a linear and a nonlinear model. According to the VNA measurements, the parasitic parameters such as package inductance and input capacitance are rather small

The nonlinear transceiver pin model was obtained using the ES620 TLP VI-curve system from ESDEMC. Fig. 10 shows the test setup. To obtain the voltage and current waveforms during the first nanoseconds, the time-domain reflection (TDR) method was used [23]. In this method, the current is calculated from the forward and reflected waveforms. In order to distinguish the incident and reflected voltage waveforms, the TLP generator supply pulse width is limited by the length of the low loss coaxial cable which acts as a delay line. Using a 2 m long cable limited the TLP pulse width to less than 10 ns. The voltage at the pin side was measured by a 1 kΩ resistor. To gain direct access to the IC, the Ethernet connector and the magnetics were removed during the VI curve characterization. The PHY IC transceiver pin VI curve was measured in the unpowered state as it was known that this transceiver pin uses a dual diode protection circuit.

The leakage current was measured by the SMU B2961A after each pulse to identify if the I/O structure of the pin was damaged.

The VI curve was measured using an average window from 7 to 9 ns [23]. As the CDE pulse in the system level test is about 50 ns long, an additional VI curve measurement was performed using a TLP having 100 ns pulse length. Here, the average window was set to 70–90 ns. Both measurements yielded similar VI curves indicating that the VI curve of this dual diode-based protection structure is independent of the averaging window.

The VI curve was modeled by voltage-controlled switches, ideal diodes, and resistors where the resistors and switches were used to set the VI characteristics and the ideal diodes separate the positive and negative injection behaviors. Fig. 11 compares the IC transceiver pin modeling and measurement result. As expected in a dual diode protection, the turn-on voltage is about 0.7 V if not powered, and the curve is symmetric with respect to polarity. The diode’s dynamic resistance is about 0.4 Ω after turned on. Applying 1.6 V Vdd IC shifts the positive VI curve branch shift by 1.6 V.

Changes in leakage current are generally used as an indication of whether the IO pin has been damaged. During VF-TLP (10 ns pulse width), the leakage current was measured after each pulse by applying 1 V dc to the pin. The leakage current did not change. It remained at 300 μA for currents up to 40 A. Using a 100 ns wide pulse damage was observed at 23 A as indicated by an increase of the leakage current from 300 μA to 10 mA.

D. Traces and Other Influencing Factors

The traces between the Ethernet connector and PHY IC pins form a differential transmission line. Using a TDR, the trace length and impedance were determined. It is important not only to consider the inductance formed by the common mode choke, but to consider the fact that the common mode choke is made by winding a TWP around the core. Its electrical parameter also had been determined using a differential mode TDR. The effect of the pair is modeled as T1 and T2. Fig. 12 gives details of the traces and common mode choke transmission line modeling structure.


The model was completed by combining the cable model, the magnetic model, the interconnection, and the IC model. Fig. 13 compares the measured and simulated results for the second pin (pin 1) discharge case. A differential voltage of 1000 V was used and the current waveform was measured at the I_probe branch (see Fig. 3). The voltage waveform was measured at the MDI+ pin via a 1 k resistor, corresponding to the voltage at PHY-side node of inductor L3 (see Fig. 12).

Voltage overshoot and ringing is visible at the waveform shown in Fig. 13. For small signal levels, the PHY IC terminates the differential pair into 50 Ω to ground. However, if the signal levels are large enough to turn on the ESD protection of the PHY IC, the signal is reflected by the low dynamic resistance of the ESD protection (about 0.4 Ω). The ringing is caused by this reflection and the traces and inductances between the IC and the transformer.


A. Transformer Saturation

The first aspect to discuss is the effect of saturation of the transformer core and the common mode chokes. The chokes will not be saturated by differential signals, but long pulses or high current levels will saturate the transformer. This effectively reduces the IC current, protecting the IC. The transformer investigated began to saturate at 3 kV if a 5.6 m cable was used. Using a 25 m cable, saturation was observed above 1 kV (see Fig. 14). The saturation onset occurs at rather high currents which are caused by the low dynamic impedance of the ESD protection circuit (0.4 Ω). The large current in the secondary winding partially cancels the flux caused by the primary winding and in this way, preventing core saturation. As the saturation is reducing the current in the ESD protection, it is important to model saturation for predicting the CDE robustness of the system.

B. Comparing CDE to IEC 61000-4-2 Contact Mode Discharge

As CDE test equipment [32] is presently not widely available, it is common practice to test the robustness of equipment against CDE by using an IEC 61000-4-2 generator in contact mode. The IEC 61000-4-2 ESD generator is discharged to individual pins of the connector while the other pins are left unconnected. Simulations using the proposed model help to clarify the differences and similarities between a dedicated CDE tester and an ESD simulator.

As shown in Fig. 15, the ESD generator directly discharges to a LAN connector pin. The current flows via the common mode choke, and one half of the transformer to the 75 Ω – 1 nF termination circuit. This current, and the resulting voltages at the Ethernet PHY IC are compared to a discharge from a LAN cable in differential mode, i.e., to the case in which the second pin which contacts belongs to the same pair.

Here, an ESD generator charge voltage of 4 kV is assumed. For the discharge of the LAN cable, 1 kV differential voltage is used for the simulation. The ESD generator circuit model is taken from [22].

Comparing the CDE tester to the ESD generator shows clear differences between the measured current and voltage waveforms (see Fig. 16). The data indicate that a 1 kV CDE differential (second pin) discharge causes a peak current value of approximately 15 A, which is similar to the peak current caused by an ESD generator charged to 4 kV and discharged to the pin in contact mode.

The pulse lengths cannot be directly compared as the CDE pulse depends on the length of the LAN cable length. A 1:4 voltage ratio approximately matches the peak current which can be estimated by simply analyzing the impedance ratios. The CDE differential discharge has a source impedance of about 100 Ω (LAN cable); the approximate source impedance of an IEC 61000-4-2 generator can be estimated from the requirement of having 3.75 A/kV peak current which leads to about 266 Ω. Further, the 75 Ω of the ac termination must be included for the ESD generator discharge leading to an impedance ratio of 100:341. However, the fundamental difference in the return current path should not be overlooked. First, the second pin discharge of a LAN cable drives a differential current, which passes unaffected through the common mode chokes. In contrast, the ESD generator discharge current is not compensated within the common mode choke; thus, the choke will partially suppress the current up to the point of saturation.

An additional difference results from a large variation in circuit implementation of the ac termination circuit which carries the bulk of the return current when an ESD generator is used for testing. In this case, the circuit is implemented by a 1 nF capacitor and 75 Ω resistor connected in series from the transformer center tap to VSS. Because the connection method and component selection for this termination circuit varies strongly between products (e.g., multiple center taps may be connected to one termination, varying RC values, or a simply nonexistent termination), the ESD generator can see significantly different load impedances which are unrealistic during real CDEs. Therefore, it is recommended that IEC 61000-4-2 compliant generators not be used for evaluating the CDE robustness of the Ethernet front-ends.

C. Shielded LAN Cables

Cable discharge of a multiwire cable is a complex situation and the current depends on many parameters, such as the mating sequence, the distance of the cable to ground, the charge voltage and the response of the different linear and nonlinear components inside the product. If the cable is shielded, additional parameters need to be considered. If the cable is charged by applying a voltage to the shield and the shield contacts first, a discharge will occur between shield and the system ground. In this case, the discharge is not likely to cause damage, as the voltage between the shield and the wires would be very low. However, the quality of market sampled cables varies strongly. The best cables use both a foil and a braid and connect them well to the connector shield. However, some “shielded” cables have no shield at all, and some use only a rather resistive foil which does not make reliable contact with the connector. Thus, an analysis of “shielded cables” would have to include a discussion on the quality of the shield implementation-based cables sampled from the market.


This paper introduced a system-level modeling method for the electrostatic discharge of LAN cables. An Ethernet-connected system was chosen to illustrate the modeling method. Four main parts are included in the simulation model: charged cable, transformer and common mode choke arrangement, including saturation, traces in the system, and the nonlinear response of the Ethernet transceiver’s ESD protection circuit. The pins of the connector connect in a random sequence. A differential mode discharge will occur if the first and the second pin which contact are from the same twisted pair. This connection sequence may lead to the worst case discharge. This differential mode current can damage the physical layer-integrated circuit. It is further shown that the saturation of the transformer can help to protect the IC, and that testing for CDE robustness by using an IEC 61000-4-2 generator is not a good substitute for a CDE tester as the return current path for the IEC 61000-4-2 testing does not match the current path of the differential discharge. The methodology proposed in this paper provides a step toward a complete SEED simulation of LAN cable discharges.