Tag: ESD

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PB2016.02 ESD Failure Analysis of PV Module Diodes and TLP Test Methods

Download PDF – ESD Failure Analysis of PV Module Diodes and TLP Test Methods

Bypass diodes inserted across the strings of the solar panel arrays are essential to ensure the efficiency of the solar power system. However, those diodes are found to be susceptible to potential electrostatic discharge (ESD) events in the process of solar photovoltaic (PV) panel manufacture, transportation, and on-site installation. Please refer to [1], where an International PV Module Quality Assurance Forum has been set up to investigate PV module reliability, and Task Force 4 has been setting guidelines for testing the ESD robustness of diodes used to enhance PV panel performance.

This article explains the theory behind the ESD damage and the proper test and analysis methods for ESD failure of diodes. To demonstrate the proposed testing methodology that follows, we will be evaluating six different types of diode models as supplied by our customer, who manufactures solar panel arrays.

BACKGROUND

Bypass and Blocking Diodes in Solar Panel Arrays

To help maintain the efficiency and performance of solar panel arrays it is common for bypass diodes to be inserted across individual PV panels, and blocking diodes to be inserted in series with a string of panels that are used in a parallel array (see Figure 1). The bypass diodes provide a current path around a shaded or damaged panel. If these are not installed, the panel will act like a high impedance load when shaded. This effectively reduces the series string output as the current produced by the remaining series connected panels will be forced to go through the shaded panel, thereby reducing the voltage output of the string.

If the bypass diodes are installed, and one of them fails due to ESD, it typically fails to a short circuit. When this happens (see Figure 2), the shorted diode does not allow any power produced by its panel to enter the system, thereby lowering system efficiency. Blocking diodes keep current from the battery pack, or a parallel panel string from entering a damaged string. This is important at night when the panel array cannot provide any power, thus providing a path for the battery to discharge. When installed, the blocking diodes may have leakage current on the order of nano- or micro-amps. However, if they fail due to ESD, they typically fail to a short circuit providing another path for the battery to discharge. This discharge current can be milli-amps or amps. (See Figure 3 for an example of this failure scenario.)

Failure of even one of these diodes in the field is very expensive for companies to replace due to the need for a qualified service technician, as most installations will require code requirements to be met. Continued operation of the panel array with a damaged bypass or blocking diode will, at best, hamper the array’s efficiency and, at worst, cause permanent damage as it consumes power rather than produces power. It has been proposed that the damage to the diodes is caused by ESD stress.

What is ESD and how it damage the solar PV module diodes?

ESD is the sudden flow of electricity between two electrically charged objects caused by contact, an electrical short, or dielectric breakdown. Electrostatic discharge stress can occur in many forms and, depending on the characteristics of the stress, can damage different parts of solar PV module subjected to the stress. In particular, there are several ESD models with industrial standards that describe the pulse shape, source impedance, and determines levels at which the device should survive.

The commonly used ESD models (Table 1) are the Human-Metal Model (HMM) (IEC 61000- 4-2 for system level ESD testing or ANSI/ESD SP5.6-2009 for component level ESD testing), the Human-Body Model (HBM) for component level ESD testing (ANSI/ESDA/JEDEC JS-001-2014), and the Charged-Device Model (CDM) for device level ESD testing (ANSI/ESDA/JEDEC JS-002-2014). There is also the Machine Model (MM), but it has been discontinued due to poor repeatability. Further, a new ESD model that currently has no established industrial standard, but has a different damage effect is the Cable Discharge Event (CDE).

Human Metal Model (HMM)

The human-metal ESD can take place when a charged person holding a pointed metal object, like a screwdriver or a ballpoint pen, rapidly moves the hand against an electronic device. In regard to PV module bypass and blocking diodes, this type of ESD events would most likely occur during junction box assembly with metal tools like tweezers, pliers, or screw drivers, etc. Figure 4 demonstrates a HMM event between a screwdriver and a screw that is part of an electrical installation in the junction box.

Human-Body Model (HBM)

Human-body model simulates the transfer of charge from a human to a component, such as through a fingertip as a device is picked up. This model is one of the most commonly used ESD tests for component qualification. In regard to PV module bypass and blocking diodes, this type of ESD event would also most likely occur during junction box assembly, especially if the operator picks a diode and mounts it by hand into the junction box. Figure 5 demonstrates a personnel picking up a PV module diode with bare fingers.

Charged-Device Model (CDM)

Charged-device model simulates the transfer of charge from a device to ground. A device can collect charge by sliding across a surface and then discharged by contact to a metal surface or ground. In regard to PV module bypass and blocking diodes, this type of ESD event would most likely occur during junction box assembly.

Transmission Line Pulse (TLP)

The TLP technique is based on charging a transmission line to a pre-determined voltage, and discharging it into a device under test (DUT). The cable discharge emulates an ESD event that has better defined RF signal path, controllable rise-time, and pulse width. The test setup allows transient current and voltage waveform to be monitored. Therefore, the change of the DUT impedance can be monitored as a function of time in ps details. The DUT performance degrade or failure check can be automated with RF high voltage switch and help the system with faster ESD performance analysis. Regarding to the PV module diodes, this model is not a real-world event as the transmission line would not be well defined as the TLP model, but the type of waveform is relatively similar to cable discharge events (CDE) during the PV module on-site installation process.

Cable Discharge Event (CDE)

A cable discharge event is a frequent real-world electrostatic discharge event that occurs when a cable is connected onto a device and the cable has existing charge prior to making the connection. This can also happen by connecting a charged cable (open on one end) to a device. It occurs because there is a potential differential between the charge on the cable to be connected and the device. The resulting waveform is highly dependent on the real-world current return path and specifications of the cable.

However, these events usually have a fast rise time of less than 500ps, potential for high current that can reach over 100 Amperes, and a potential long pulse that can be several µs if the discharging cables are long. The fast rise time, high current, and long pulse duration can result in a permanent performance degrade or physical damage of device being subjected. Regarding to solar PV module, the cable connections between the panels can be very long, resulting the ESD current waveform could be very different from all previous cases. Because cable connection is an avoidable on-site installation process, cable discharge event should be treated as a special ESD case with special test setup for the PV module diodes quality assurance.

Although these ESD models describe how an ESD stress event may originate, the underlying physics of these models point to two basic damage causes. Damage may occur as the device cannot withstand the extremely fast voltage transient, or a device is not able to handle the current or the heating caused by the current. Here, the heating occurs within nanoseconds, such that there is no thermal exchange with the surrounding. Further, the current distribution within the conduction area of the device may not be homogeneous, such that local melting (“filament creation”) leads to damage at current levels that the device could handle, if the current would flow with equal current density in the device.

The CDM model is used to qualify a device for the first of these damage types in that a very fast rise time as 100 ps with a short duration pulse. This test can determine if the gate oxide layer of a component is susceptible to a CDM type of event. The HBM model is used to qualify a device for the latter of the damage types in which a long duration (100ns) pulse is applied. The HMM, CDE and TLP models could possibly contain both types of damage. However, the CDE or TLP type of model would result in the worst possible damage in all of the cases discussed above.

An example of damage to the semiconductor components is shown in Figure 7 which illustrates burn track damage on a PV bypass diode caused by ESD.

THE TRANSMISSION LINE PULSE TEST METHODOLOGY

Given the nature of how the bypass and blocking diodes could be exposed to and damaged by ESD events, the worst case that would be the cable discharge event, in which both fast rise-time and high energy pulses occur during the installation process. Therefore, based on the existing industrial ESD testing methods, we propose to use the transmission line pulse test method that does not necessarily replace the IEC 61000-4-2 standard, which may have been be used in the current qualification process. Instead, the TLP test method subject a diode (a low resistance DUT) to a faster rise-time and higher energy pulse up to 180A (pulse reflections being allowed to approach the real-world CDE case). This provides a fully-automated device ESD performance characterization system for transient IV signal and degrade/failure inspection before and after each pulse. Compared to the other types of ESD models, the advantages of using a TLP test are:

Well Defined Consistent Waveform Shape: Both circuit and waveform defined in ESD simulator standards are too flexible (no impedance control for test path, 30% tolerance at only certain time) This causes ESD simulators to provide very different ESD test results between different test sites. A TLP pulse is very clean and consistent.

Highly RepeaTable Test Setup: Fatigue from holding ESD simulator by hand can lead to inconsistent test setups. In TLP testing with jigs for mounting the DUT, a more controlled test is obtained.

Fast Automatic Measurement and Reporting: Typical TLP testing is done with full automatic control of oscilloscope scale adjustment, voltage pulsing, failure criteria checking, and IV curve update.

Important Device Behavior is recorded for ESD analysis and design: Many useful parameters can be extracted from TLP tests for device transient behavior analysis, modeling and system-efficient ESD design (SEED). Traditional ESD tests only generate pulse for pass/fail results.

Test Setup

The TLP test setup is shown in Figure 8. A transmission line pulse (TLP) generator provides a rectangular voltage pulse by charging a 50Ω transmission line to a test voltage, and discharging the pulse to the DUT by a special relay which can withstand the voltage, and can switch to an on “on” status without bouncing. The pulse then travels out of the TLP through a coaxial transmission line where it first reaches a high voltage relay (A621-HVLKR).

This relay is capable of withstanding up to 10kV, and is required for the high current TLP testing used with these high power diodes. The relay provides a means of transferring connection of the DUT between TLP measurement system and the failure detection system. In particular, during TLP pulsing, the relay connects the DUT to the TLP, the measurement probes, and the oscilloscope. After each TLP pulse test waveform has been captured, the system switches the DUT to the SMU to measure the diode reverse leakage current at maximum recurrent peak reverse voltage (VRRM). The A621-LTKSEM leakage test module also helps to facilitate these connection changes on the low voltage side of the measurement probes.

The DUT current is measured indirectly using a resistive tee to voltage measurement. The current is recovered by the overlapping reflection method. This method measures both the current through and the voltage across the DUT, but for lowresistance devices, such as a diode in the “on” state, this method is not well suited for measuring the device voltage. Instead, the DUT voltage is measured directly at the device, providing a highly accurate voltage probing measurement. The current measurement is performed by first measuring the pulse as it passes by the first pickoff resistor that goes to Ch1 of the oscilloscope. A short delay later (as determined by the length of coaxial cable between the pick off resistors), the pulse reflected from the DUT is measured at the same pick off resistor yielding an overlapped waveform. Using transmission line theory and a pre-measurement calibration pulse, the current into the DUT can be determined as:

Where V+, V- , and Zo are the incident pulse, reflected pulse, and characteristic impedance (50Ω) of the transmission line system, respectively.

Test Procedure

The test procedure is demonstrated in the flowchart shown in Figure 9. Upon entering the test loop, the system measures the leakage current of the DUT to obtain the initial degrade measurement. Next the TLP charge voltage is set. For the testing reported in this article, the charge voltage was set to sweep from 500V to 9600V, in 100V increments. For the first test point, the oscilloscope scale and trigger level are set based on the initial charge voltage and a 50Ω DUT. As testing progresses, the scale and trigger level are set based on if the waveforms clip, or is under scaled. If the waveforms do not clip or are not under scaled the settings are kept.

After setting the oscilloscope parameters, the DUT is pulsed and the captured data is compared to the oscilloscope display range for each captured channel to check for clipping and whether the scale is appropriate. If any of the waveforms are clipped, the scale is adjusted and the DUT is pulsed again. If the waveforms are ok, or under scaled, the data is accepted and processed. Any under scaled waveform corrections are made on the next pulse level. Processing is completed by scaling the data by the measurement attenuator and probe values.

Another DUT degrade/failure measurement (measure the PV diode leakage current under reverse working voltage) is made to determine if the DUT has failed or not. If failure occurs, the test is stopped. If. If not, the next pulse point is performed. This repeats until all pulse points are done, or failure occurs.

Dynamic IV Curve Measurement Principles

One of the goals of the measurement system described above is to obtain the dynamic IV curve of the DUT over the voltage range pulsed. Current and voltage waveforms resulting during pulse test are demonstrated in Figure 10. The dashed lines near the end of the pulses represent the start and stop points of the dynamic IV measurement window.

The measurement window is typically 70 to 90% range of the pulse but other ranges can be selected. Over this window, the average value of the time waveform is taken as the current and voltage, respectively. This value is then plotted for each voltage pulse applied.

Degrade/Failure Measurement (Leakage Current Measurement)

The leakage current was measured using the source meter unit (SMU) and, depending on the diode tested, the bias voltage was varied between two and three different voltages with the maximum bias voltage set to the maximum recurrent peak reverse voltage (VRRM) for each diode. The VRRM voltage is listed in each individual diodes datasheet.

Also, for the results reported below, for any diode that failed the leakage current upper limit was set to 2.5mA (a value that is very high and can be treated as failure criteria). This is the compliance limit of the SMU and is not an indicator of diode characteristic after failure, other than they appear to fail to a short.

SOLAR PV MODULE DIODES TESTS

Over the years, ESDEMC Technology has tested several diode models for solar PV module companies. The VRRM (from device datasheet) of the diodes are listed in Table 3. The VRRM values are important because they provide the maximum bias voltage applied to the diode for leakage current measurement. This value is supplied by the device manufacturer, and is typically found in their respective datasheets.

In the following sections, the test results will be presented in terms of the best performer to the worst performer in regard to diode failure during TLP testing.

Sample Set #5

Out of the 80 devices we tested in Sample Set #5, no failure occurred. The dynamic IV and leakage current curves for three samples are shown in Figure 12. The dynamic IV curve is read from the Y-axis to the bottom of the X-axis, and the leakage current from the Y-axis to the top of the X-axis. Note that the top of the X-axis is logarithmic due to the dramatic change in leakage current once a device fails to a short circuit.

Sample Set #3

The next best performers were the devices in Sample Set #3, which had only one diode fail out of one hundred units; failure occurring near the last few test pulse levels. The dynamic IV and leakage current curves are shown in Figure 14. Once the diode failed to a short, the resulting leakage current was at the compliance limit of the SMU, and is not an indicator of the diode condition.

Sample Set #6

Sample Set #6 had eleven failures out of eighty diodes tested. The minimum, maximum, and average pulse current for each of them are listed in Figure 25, and the dynamic IV and leakage current curves, for three of the failed diodes, are shown in Figure 16.

Sample Set #4

Sample Set #4 had 18 devices fail out of 100 tested. The dynamic IV and leakage current curves, for three of the failed diodes, are shown in Figure 18.

Sample Set #2

All of the diodes in Sample Set #2 failed. The minimum, maximum, and average pulse current for each of them are listed in Figure 25, and the dynamic IV and leakage current curves, for three of the failed diodes, are shown in Figure 20.

Sample Set #1

All of the diodes in Sample Set #1 failed. The minimum, maximum, and average pulse current for each of them are listed in Figure 25, and the dynamic IV and leakage current curves, for three of the failed diodes, are shown in Figure 22.

CONCLUSION

Of the diodes tested, only those in Sample Set #5 did not have failure up to 200 Amp or 10 kV of the eighty diodes tested. The next best performer was Sample Set #3, which only had only one failure, and that particular diode failed near the last few test pulses (100 diodes tested). Sample Set #6 had ten diodes fail out of eighty tested, and the Sample Set #4 had eighteen diodes fail out of one hundred tested. The worst performers were those in Sample Sets #1 and #2, where all diodes failed (all diodes tested failed for both models).

The chart shown in Figure 25 depicts the minimum, maximum, and average pulse current at failure for the diodes that failed.

It has been suggested that it is not necessarily the diode design type that determines if the diode is more or less susceptible to ESD stress, but instead a result of quality control of the manufacturing. For example, the process may be as follows: a diode as the 15SQ100 (tested data is now shown herein) is being checked in quality control after manufacturing. Its reverse breakdown voltage is checked. If it does not pass 100V, but passes 50V, it is re-labeled as a 15SQ050 model. This may not guarantee that the 15SQ50 model is a higher quality 050 design, and may instead be a poor quality 100 design relegated to the 050 model line. Here, the problem is that the diode may not hold 100V reverse voltage due to a local defect. The local defect will concentrate the current during ESD into a very small area and cause the diode locally to melt. Thus, the robustness of such a diode is much worse than a diode that passes the 100V reverse voltage, which may indicate that it does have few, and less severe local defects.

According to our customers (solar solution providers), our findings on the diode failure rate, through TLP test methodology, correlates to their field return failure rate. Therefore, we recommend that TLP testing be performed for all solar PV module diodes. In addition, it may be in the best interest of both solar PV module and diode manufacturers to investigate the quality control of the diodes selected, yielding a more reliable design for field use.

Read more: http://incompliancemag.com/article/esd-failure-analysis-of-pv-module-diodes-and-tlp-test-methods/#ixzz45fk4HnPT

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PB2012.09 An application of utilizing the system-efficient-ESD-design (SEED) concept to analyze an LED protection circuit of a cell phone

Download PDF – An application of utilizing the system-efficient-ESD-design (SEED) concept to analyze an LED protection circuit of a cell phone

An application of utilizing the system-efficient-ESD-design (SEED) concept to analyze an LED protection circuit of a cell phone
Tianqi Li #1, Junji Maeshima *2, Hideki Shumiya*3, David J. Pommerenke#4, Takashi Yamada*5, Kenji Araki*6

# EMC laboratory, Missouri University of Science and Technology, 4000 Enterprise Dr., Rolla, MO, 65401, USA, tlx6f; 4 davidjp@mst.edu
* Sony Corporation, Sony City, 1-7-1 Kounan Minato-ku, Tokyo, 108-0075, Japan
2 Junji.Maeshima; 3 Hideki.Shumiya; 5 TakashiB.Yamada; 6Kenji.Araki@jp.sony.com

 

Abstract—An LED circuit of a cell phone is analyzed using the System-Efficient-ESD-Design (SEED) methodology [1]. The method allows simulation of the ESD current path, and the interaction mechanisms between the clamp and the on-chip ESD protection circuit. The I-V curve and the non-linear behavior under high current pulses of every component including R, L, C, and ferrite beads are measured and modeled. By combining all of the component models, a complete circuit model is built for predicting the circuit behavior and damaging threshold at a given setting-voltage of a Transmission Line Pulser (TLP).

I. INTRODUCTION

To build lower cost systems with better ESDresistant design at the system level it is important to understand the ESD current path, and how an IC’s on-chip protection circuit interacts with outside clamp circuits [2]. For example, if the on-chip ESD circuit of an IO pin could provide enough protection, then any external protection components could be omitted to reduce cost. A more complex case would be if the on-chip ESD circuit could not meet the protection requirements and the off-chip protection circuit has a relatively large resistance, more ESD current would still flow through the IO pin’s internal ESD circuit and finally damage the IO circuit itself. In this case, the external protection circuit should be replaced with a different clamp with smaller resistance in order to protect the IO pin.

For this reason, the interaction between components, especially between different protection circuits inside a system needs to be thoroughly analyzed, to achieve a more efficient protection scheme at the system level [1]. This is the purpose of the SEED approach. Circuit modelling and simulation is a convenient approach for such SEED analysis. However, typical SPICE models of components cannot be used in these simulations because they usually only contain information for normal operating conditions, without responses to several kV pulses such as those seen in ESD strikes. In this project a TLP is used to measure transient IV characteristics of each component, and highvoltage-SPICE models are built based on the tested data [3].

In this paper, an LED circuit in a cell phone is chosen to demonstrate the SEED analysis approach. The schematic of the LED circuit is shown in Fig.1. Under typical working conditions the VCC pin outputs DC current that flows through the LED and is sunk by the IO pin. The driver IC controls LED turn-on and turn-off by changing the status of the output MOSFET. All other components such as capacitors and Zener diodes are used for ESD protection and other filtering purposes. A potential discharge point is at the LED, which is located near the cell phone’s keyboard.

A. Modeling the LED

The I-V curve of the LED has been measured using a TLP resulting in the SPICE model shown in Fig. 2. The model includes two parts: the normalcondition SPICE model which is provided by the device manufacturer, as well as switches for matching the transient I-V curve. The factory model is OK for emulating the device I-V curve in the positive voltage region, but does not conform to the I-V curve in the negative-voltage region. For this reason, two switches are used to correct the simulated I-V curve.

During the measurements, it was also found that the LED will be damaged if the current reaches +15A or -10A.

B. Modeling the Zener Diode

The Zener diode was modeled in a similar way. In the model which is shown in Fig. 4, diode 11 defines the I-V characteristics of the Zener under a negative pulse. Diode 10 and the switch determine the positive I-V characteristics. Diode 9 is used as a unidirectional switch.

A linear capacitance of 25 pF is also included. Its value is taken from the datasheet and verified through measurements.

The simulation results of this model (Fig. 5) show good agreement to measurements as well.

C. Modeling the IO Pin of the LED Driver IC

A reflection-based TLP system is used for insystem measurement of the transient I-V curve of the IO pin, which is modeled without knowledge of its internal circuit. Similarly, the model is a combination of linear and non-linear components. The non-linear behavior was measured by the reflection-based TLP system, and its linear part can be obtained by tuning the model parameters to conform to the measured S11. In this way, a complete model of the IO pin could be developed, as shown in the Fig. 6. R20 and C2 are these linear components which were obtained from the Sparameter measurement.

Similar to the Zener diode model, diode 7 defines the non-linear behavior of the device when a negative pulse is applied at the IO pin. Diodes 6 and 8 define the non-linear behavior when a positive pulse is applied to the IO pin.

A damage threshold of 22A was determined using a 13.5 ns pulse from the TLP to the IO pin. The transient I-V curve of the model is shown in Fig. 7.

D. Modeling the Ferrite Beads

Because ferrites are non-linear components, their equivalent inductances drop as through currents increasing, due to saturation effect. A non-linear model of the ferrite bead, as shown in Fig. 8, was obtained by defining its equivalent inductance as a function of current.

In this model, the linear parts include R1, C2 and R9, which are extracted from the impedance plot provided by the datasheet. The non-linear part of the ferrite model, the inductance as a function of current, was measured by a TLP, and modeled with following equation:

Where I stands for the current through the nonlinear inductor, L0 is the inductance value for I=0. Thus, for FB1 L0 equals to 60nH. Lsat stands for the saturated inductance which, for FB1, equals 20nH. The plot of the equation is shown in Fig. 9.

The model is validated by comparing simulation and measurement results, as shown in Fig. 10.

E. Modeling the Inductors

The inductors used in the circuit are assumed to be linear components, and the transient simulation result, as shown in Fig. 11, validates this assumption.

F. Modeling the Capacitors

The capacitors used in this circuit have anNP0 type dielectric, therefore it was expected that the capacitance would not change as a function of the voltage across the capacitor. Such expectation was validated by measuring capacitance variation with respect to voltage by using a TLP. These TLP measurements confirm that the NP0-dielectric capacitor can be modeled as a simple linear capacitor.

III. SYSTEM MODEL AND SEED ANALYSIS

A. The System Model

A system model was built by combining each of the experimentally obtained component models, as well as a TLP model as the source. The system model is validated through S-parameter measurements, as well as transient pulse measurements. The simulation result is compared to the measurement in Fig. 12. This comparison clearly shows that the injected 500 V TLP pulse is clamped to 9V by the protection circuit.

B. SEED Analysis

From Fig. 12, although it is known that the injected pulse is clamped to a low voltage, it is not known which one of the clamp circuit components is the primary clamping element. Additionally, it is not easy to predict what level of the injection pulse will damage the circuit, due to the fact that only a limited number of DUTs were available for real testing.

With the SEED method, the previous questions can easily be answered because it is possible to observe currents as they flow through various components in a simulation environment. In Fig. 13, it is clearly shown that more pulse current flows though the Zener diode during the first 10ns of an applied pulse before the protection diode inside the IO pin starts to conduct.

If the Zener diode is a more effective form of ESD protection we can ask if it is possible to remove FB1 before the IO pin to reduce cost. The simulation result in Fig. 14 shows that without the ferrite bead more current would flow through the IO pin, but not the Zener diode. Therefore, the ferrite bead has significant effect on the current that flows through the IO pin, and thus should not be removed.

SEED analysis may also tell us what the vulnerable parts in this circuit are, and how much margin left till the circuit would fail under a given injecting level, if the damage threshold of each component is known. For example, the simulation result in Fig. 15, shows that the current which flows though the LED is much larger than the current that flows through the IO pin. Therefore, for this circuit, the LED is more prone to damage than the driver IC, especially considering that LED device is usually placed at a location that has a greater chance to experience air discharge. It can be predicted that the LED will be damaged under 2000V TLP pulse because under this condition the LED’s through current reaches to 15A, which is its damaging threshold measured with 13.5ns TLP pulses.

IV.CONCLUSION

In this study, the SEED strategy is applied to analyze the ESD performance of a cell phone’s LED circuit. High current SPICE behavioral models of each component in the circuit were developed and validated against measurements. By combining these models with a TLP source model, major pulse-current paths, protection mechanisms, system transient response, and weak points of the protection circuit are revealed. These parameters can then easily be analyzed through simulation, instead of performing a large number of destructive measurements.

For next step, the TLP model can be replaced with an ESD gun SPICE model, so that we can predict the circuit’s response under real ESD gun contact discharge measurements. This may help circuit designers predict the ESD performance of a circuit before it is put in to production. This SEED strategy also facilities PCB level ESD protection design during initial product development, rather than traditional trial-and-error process.

ACKNOWLEDGMENT

This material is based upon work supported by the National Science Foundation under Grant No. 0855878, and supported by Sony Corporation of Japan.

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PB2009.08 A Measurement Technique for ESD Current Spreading on A PCB Using Near Field Scanning

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Abstract — Electrostatic discharge (ESD) can cause interference or damage in circuits in many ways e.g., by E- or Hfield coupling or via conduction paths. Although we can roughly estimate the voltage and current at the injection point during an ESD event, the real offending parameter is mostly the ESD current spreading throughout the system. Those currents can be simulated if great simplifications of the system are accepted.
However, even in moderately complex systems the ability to simulate is limited by lack of models and computational resources. Independent of the complexity, but obviously not free of its own limitations is a measurement technique that captures the current as a function of time and location through the system.
This article describes the proof on concept of ESD such a measurement technique that allows reconstructing the spreading current as a movie from magnetic field measurements. It details the technique, question of probe selection and how to process the data to present the current spread as a movie.

 I. INTRODUCTION

ESD can damage or disrupt a system. Understanding of system level ESD has been approached from different directions, such as ESD generator modelling [1], in circuit measurements [2], air discharge analysis [3], numerical simulation of currents and fields, protection circuit analysis, etc.

One of the effective methods for analysing ESD robustness is using a three dimensional scanning system to localize ESD sensitive areas or traces [4, 5, 6]. In conjunction with the circuit information the root cause of a system level problem often can be fully understood.

However, as in near field scanning, it is not obvious to connect local results (e.g., sensitive area, or strong fields in near field EMI scanning) to system level performance. For ESD one needs to understand which current densities, field strengths and derivatives are to be expected at one location if an ESD is injected into a test point.

The sensitive areas found by near field susceptibility scanning might not be those, which will receive a lot of current or field strength during an ESD. Thus, the current spreading during an ESD needs to be known to connect local sensitivity data with system level responses.

This article reports on our proof of concept for a current spreading measurement method. The main objective of the research is to develop a method to measure and reconstruct current spreading and field coupling in or close to circuits by scanning; to correlate system level ESD with scanning level ESD in time and spatial domain; and at the end to analyze and extract circuit and layout design strategies for ESD current protection.

This paper is mainly describing the methods of ESD current reconstruction on PCB. Research beyond this simple PCB will be continued in the future.

II. TEST STRUCTURE

For a proof of concept the structure of the device under test (DUT) and the experiments based on it have to be simple but meaningful. Fig. 1 shows the PCB structure we used:

It is a simple two layer PCB with 3 traces on the top layer and a solid ground plane on the bottom layer. Signal probing (for traces) is performed via SMA male to male connectors at the back side of the PCB. Their ground connects to a large ground plane. Injection is performed via a coax connection on the edge of ground layer. This allows easy numerical modelling. Fig. 2 is the setup picture:

For the test setup above, the injected current from the cable centre conductor will spread on the top PCB ground layer (both sides of the copper) and return via the 6 SMA connectors outer conductors to the large aluminium ground, then return to the injection cable through the injection structure. This current spreading and return is shown in fig.3 (top view) and fig.4 (side view).

III. MEASUREMENT METHOD

To capture the current, the magnetic field is measured by placing a probe close to the surface of the PCB. An ESD pulse is injected into the PCB and the magnetic field is captured. Due to the close proximity of the probe to the PCB one can approximately equate the magnetic field to the surface current density. Then the probe is moved to the next location and another pulse is injected. This is repeated until a sufficient number of locations have been measured. There are a couple of choices for setting up the measurements:

a) Probe Selection.

Before choosing current probes, we need to understand the E and H field coupling of the ESD scenario [7, 8, 9]. Fig. 5 shows the 3 field coupling paths we are concerned about:

We want to suppress the E-field. There are two relevant currents: The current density on the PCB and the currents on the traces. We are interested in both. The magnetic fields of the trace currents are often much weaker than the magnetic field of the surface current density.

Therefore it is difficult to measure trace currents by the same H-field probe that is used for the ground layer current. However, the field components are different. The trace current has an Hz field component. It is possible to separate the trace current by measuring the Hz component over the PCB. Probe selection requirements are:

1) The probe needs to suppress the E-Field, otherwise the E-field coupling will easily override the H-field coupling from the current.

2) The probe for measuring the ground layer current can be a shielded vertical loop probe measuring Hx or Hy. The trace current that is induced into the traces generates much weaker Hx Hy components, they are mostly overwhelmed by the Hx and Hy components from the ground layer current. In the test we used a 6 by 8 mm coaxial shielded vertical loop probe to capture Hx and Hy from the PCB ground layer current.

3) A good probe of measuring trace current in this scenario needs to well reject ground layer current coupling. For this application, a 3 by 3 mm patent pending trace current probe was designed to capture the trace current. It measures the trace currents Hz components since Hz is dominated by trace current locally and incorporate other features.

b) Time or Frequency Domain.

The first set of data presented here has been captured using a transmission line pulser (TLP) as source (about 300 ps rise time) and a real time oscilloscope to capture the signal. The use of a Network analyser (NWA) is also discussed further down this article.

A. TLP and Oscilloscope Scanning Method Setup

Fig.6 shows the test setup for current reconstruction scanning using a TLP and an oscilloscope.

The current is injected from the right middle edge (x =300mm, y = 150mm) of the PCB into the ground layer. From the injection point current spreads over the ground layer as fig. 3 showed before, and couples to the 3 traces. All traces are terminated by matched loads. A shielded vertical loop will measure the current spread on the surface of the PCB with 2 orthogonal directions (measuring Hx and then Hy components separately). In this way, two sets of data will be created for data processing.

The oscilloscope records data after receiving a trigger from the TLP. Providing the TLP repeats well all measurements are “synchronized” and show the current spread when plotted as a function of time. The probe couples to the time derivative of the current density via a probe factor. Thus multiplication by the factor (yet unknown, but a pure function of geometry) and integration would allow determining the current in absolute values.

B. Network Analyzer Scanning Method Setup

Our test setup is linear with respect to current. Thus, one is not forced to use a high voltage generator as injection. A network analyzer with time domain transformation can be used instead as setup in fig. 7 shows. The setup of the network analyzer is very similar to the TLP and oscilloscope method, the only difference is that the injection part is connected to network analyzer port 1; the probe is connected to the network analyzer port 2. S21 is measured and transformed to the time domain. To improve the signal to noise ratio, a 20 dB amplifier is added at the receiving port.

Its excitation equals the excitation of a step function (or the user could select an impulse transformation instead) [10]. For a linear system a network analyzer has many advantages over a direct time domain measurement:

It has better repeatability as it is frequency domain measurement, unlike TLP which uses a High Voltage relay to produce pulses.

Network analyzers have much better dynamic range than oscilloscopes

The time domain image of the signal injected by the Network analyzer is clean, e.g., there is no ringing, or overshoot. Fig. 8 shows the voltage waveform comparison.

IV. SCANNING RESULTS

A. Reconstructed Movie using the TLP and Oscilloscope Scanning Method on PCB Ground Layer

Fig. 9-12 show 4 fames of the reconstructed current spreading on the PCB surface when the shielded vertical loop probe is oriented at x-axis direction.

The first frame shows a very large current density at the injection moment. The current spreads in a circular fashion on both sides of the board as shown in frame 2 and 3. All frames here illustrate only the Hx component on the top side of the board. The board is connected to a large ground plane via SMA male to male connectors on PCB bottom side so most of the current will return through them. After the waveform reaches the left side of the board, reflections are visible in the last frame.

B. Reconstructed Movie for the Network Analyzer Scanning Method on PCB Ground Layer

Below are 2 current reconstruction frames obtained using the network analyzer scanning method:

The data shown in Fig.13 indicate that the wavefronts are better visible using the network analyser method. The large dynamic range of the NWA allows us to follow the current wave front over a larger distance.

However, it is necessary to use a network analyser that can cover the frequency range from 100 KHz – 3GHz; otherwise the missing frequency component will distort the time domain signal, especially the tails.

C. Data Process in MATLAB

The total field is reconstructed using MATLAB from two orthogonal scans (Hx and Hy). The scanning resolution was set to 1 by 1 cm. This leads to 30 by 30 scanning points for each scan. Fig. 14 shows 3 plots resulting from the recovering process.

The first plot is using the raw data taken from the Hy scanning. When the vertical loop probe is oriented such that the loop is normal to Y-axis, it measures the Hy component which is mainly generated by the current flowing in the direction of the X-axis.

The second plot shows the result of the Hx scanning. When the vertical loop probe is oriented such that the loop is normal to the X-axis, it measures the Hx component which is mainly generated by current flowing in Y direction. The first and second frames are snapshots at the same moment for better understanding and comparison.

The third plot in fig. 15 plots the root square sum of the raw data from the two orthogonal scanning results:

 This is the magnitude of the total horizontal H-field strength close to the plane which equals the current density on the PCB ground layer.

D. Trace Current Reconstruction

If the vertical loop is used, we can hardly see the H-field of the trace current (the trace current caused by the current injected into the PCB). It is overwhelmed by the magnetic field of the ground plane current.

Different probes have been designed a special probe just for the trace current. These probes detect the magnetic field from the trace while suppressing other field components. Fig.15 shows the comparison of the probe response when moving it across a trace during ground layer injection:

The vertical loop can hardly detect the trace current (blue trace). The horizontal loop detects the Hz component; it can detect the magnetic field of the trace current (green trace). The response of the trace current probe (red) detects only the trace current as one peak, which is located above the center of the trace.

Fig. 16 shows one frame of the current reconstruction using the trace current probe and a frame from the CST simulation movie. In both the trace current is visible.

One final remark on the trace current probe: It recovers the trace current well, but it is only sensitive to the Ix or Iy current, thus two scans need to be conducted for full reconstruction.

V. CONCLUSION

The paper presents a prove of concept for a measurement method that reconstructs currents spread as a function of time for ESD or other pulses injected into a system. A special probe is able to suppress the ground plane current to extract trace currents; its principle function has been shown.

The next steps are a comparison to simulated data and a comparison of local current density and field strength, as seen during a system level ESD tests compared to local current density and field strength as they are caused by local injection during ESD scanning. This will further help to connect local to system level results.

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PB2003.11 Problems with the electrostatic discharge (ESD) immunity test in electromagnetic compatibility (EMC)

Download PDF – Problems with the electrostatic discharge (ESD) immunity test in electromagnetic compatibility (EMC)

Asia-Pacific Conference on Environmental Electromagnetics, CEEM’ 2003 Nov. 47,2003 Hanzhou .China

Jiusheng Huang*, David Pommerenke**, Wei Huang**
*)Beijing Institute of Electromechanical Technology, Beijing, China, jshuang@ESD-China.Com
* *) Electromagnetic Compatibility Laboratory, University of Missouri-Rolla, USA
***) Beijing University of Post and Telecommunication, Beijing, China

Abstract- Electrostatic discharge (ESD) immunity test is one of the important electromagnetic compatibility (EMC) tests. The IEC standard IECdlOOO-4-2 is the widely used standard to test the ESD immunity for electronic equipment. Many amendments such as amendment 1 (1998), amendment 2 (2000) have been published since 1995, but there is still problems with the ESD immunity test even with the 200x version. More than six ESD generators of different bands are tested for different equipment. The results show that the failure voltages of different ESD generators are vary much from different bands for the same test equipment. This may lead to the results incomparable when test the ESD immunity test in the EMC. Further studies show that there is a good correlation between the failure voltage and the induced voltage.

1. Introduction The electrostatic discharge (ESD) current waveform of the IEC61000-4-2 s&ndard[ 11 is shown in figure 1. It says the rise time of the first peak is 0.7-1 ns and the current is in the range of 3.375-4.125 A/kv. The current at 30 ns is in the range of 1.4-2.6 A/kv and the current at 60 ns is in the range of 0.7-1.3~kv. Many works were made on the research of the ESD current, electromagnetic and magnetic field radiated from the ESD[2-51. Any ESD generator is standard if its ESD current is per IEC61000-4-2 standard. The failure ESD voltage for the same equipment should be the same in certain tolerances. But the failure voltages for the same equipment are very large for more than six bands of ESD generators. This paper is to investigate the main reasons and the factors which influence the compatibility of the results.

2. Test 2.1 Test setups More than six bands of ESD simulators from different factors were used as the test equipment of the experiment. A high speed oscilloscope (TekTonix TDS7404 Phosphor oscilloscope 4GHz, 20GS/s) and ESD current targets and field sensors were used as the main equipment in our experiment.

2.2. Test Results

All the ESD generators are calibrated as the IEC6 1000-4-2 standard requirements. They have the same ESD current as the standard. The ESD failure voltages of the same electronic equipment for different bands of ESD generators were tested. The failure voltage may be very much from 1kV to even 6kV for the same equipment even if all the ESD current are accordant with the same standard. This may lead to the results incomparable when test the ESD immunity test in the EMC.

2.2.1 The influence of the ground strip to the ESD current waveform Many factors such as the parasitic capacitors and inductors will influence the waveform of the ESD current and the failure voltage in our experiments. The rise time, the first peak of the ESD current and the shape of waveforms of the ESD current are easily influenced by those factors. But those parasitic capacitors and inductors are constant in a given ESD generator when it is made in the factor. Other factors such as the length and shape of the ground strip are vary in the practice experiment. The waveform of the second segment is influenced by the RC network and the shape and position of the ground strip. Several tests are made to demonstrate the effects. A ESD generator is used to test the waveform. The results are shown in figure 3 and figure 4. Figure 4 has some offset in order to observe easily (Total Y offset 70%, Total X offset 20%)

It can be seen from figure 3 and figure 4 that when the ground strip is in winding, that is the inductance is very large, the waveform (Black) vibrating during the decay period. When the ground strip is in straight line, the waveform (Blue) is very similar to the waveform proposed by IEC standard. When tlhe ground strip is in other shape and position, the waveform is also influenced by the inductance.

2.2.2 ESD induced voltage Voltage induced by both the electric field and magnetic field radiated from ESD at a given distance can be easily measured than that of the electric field and magnetic field. It is mainly the induced voltage which makes the electronic equipment failure. So, more attention will be paid to the induced voltage. There &e two typical induced voltages which represent the real effects of ESD. One is the monopole induced voltage. It is mainly induced by electric field. Another is the loop induced voltage which may be induced by both magnetic field and electric field if the sensor is not electric shielded. In order to test the ESD current, monopole induced voltage and loop induced voltage. Three channels of the digital oscilloscope is connected to ESD current target, monopole with 10″ length and the half circular loop with diameter of 13 mm respectively. It will be unstable due to the lower sampling rate when three or more channels are used simultaneously. But the concurrent phenomena can be easily observed.

2.3 ESD current and ESD induced voltage In order to test the ESD current and ESD induced voltage in the sensor. Two channels of the oscilloscope are connected the ESD current target and the loop sensor. The ESD current is much varies with the ESD induced voltage in shape and duration. The induced voltage is very short in duration than that of the ESD current shown in Fig.6. The induced voltage may be small just like noise after several ns even if the ESD current is increase.

Figure 6 shows that the ESD current will increase after 10 nanoseconds due to the discharge of the capacitor in the ESD. But the induced voltage doesn’t increase any more. This further demonstrates that the induced voltage doesn’t correlate with the ESD current.

For the same equipment the failure level of discharge may be from 1kV to 6kV. But there is good correlation between the ESD susceptibility and induced voltage from different simulators. The correlation coefficient R= -0.88567, standard deviation SD= 0.86476[2].

3. Conclusions and Future Works ESD current for different ESD simulators are tested. The ESD susceptibility of computer with different CPU and auto switch are experimentally investigaied. ESD induced voltage are tested for different ESD simulators. Some conclusions are summarized [ 51. 1. The parasitic inductor and capacitor of the ESD simulator are critical factors which will influenced the both the waveform of the ESD current and the ESD model of discharge, Different ESD simulators have different parasitic parameters that lead to the different ESD susceptibility. 2. The shape and position of the ground strip of the ESD simulator will influence the inductor of the LCR and lead to the generation of different waveform of the ESD current. These two factors are mainly source lead to the variation of the ESD susceptibility of the electronic equipment. 3. ESD induced voltage doesn’t correlate with the ESD current but it is correlated with the induced voltage. It is generated by the process of contact of the relay in the ESD. The duration of the ESD voltage is about 5 nanoseconds and the typical duration of ESD current is more than 100 nanoseconds. The ESD susceptibility is very complicated. It may be influenced by both the ESD current and Electromagnetic, and magnetic field radiated from the ESD. If the ESD current and the induced voltage can be defined more exactly, the ESD susceptibility test results may be more repeatable.

Acknowledgements

Thanks go out to Dr. Thomas Van Doren of EMC laboratory, University of Missouri-Rolla for his warmly supports to the ESD work, Kai Wang and all students in UMR for their supports and helps during my stay in UMR from 2002-2003.