Transmission Line Pulse testing, or TLP testing, is a method for semiconductor characterization of Electrostatic Discharge (ESD) protection structures. In the Transmission Line Pulse test, high current pulses are applied to the pin under test (PUT) at successively higher levels through a coaxial cable of specified length. The applied pulses are of a current amplitude and duration representative of the Human Body Model (HBM) event (or a Charged Device Model – CDM – event in the case of Very Fast TLP, or VF-TLP). The incident and reflected pulses are evaluated, and a voltage-current (V-I) curve is developed that describes the response of an ESD protection structure to the applied TLP stresses. The Transmission Line Pulse test is unique because the current pulses can be on the order of Amps, and the TLP test results can show the turn-on, snap-back, and hold characteristics of the ESD protection structure.
Transmission Line Pulse testing is useful in two very important ways. First of all, TLP may be used to characterize Input/Output (I/O) pad cells on test chips for new process technologies and Intellectual Property (IP). TLP is very useful in developing simulation parameters, and for making qualitative comparisons of the relative merit of different ESD protection schemes for innovative pad cell designs. Secondly, TLP may be used as an electrical failure analysis tool, often in combination with conventional, standards-based component ESD testing.
TLP testing is done according to the ESDA TLP test method, ESDA SP5.5-2014. TLP is quoted on a case by case basis, based on the scope of the work requested; estimated engineering time to perform the test, and customer requested reporting.
Applicable TLP Specs
