Transmission Line Pulse testing, or TLP testing, is a method for semiconductor characterization of Electrostatic Discharge (ESD) protection structures. In the Transmission Line Pulse test, high current pulses are applied to the device under test (DUT) at successively higher levels through a coaxial cable of specified length. The applied pulses are of a current amplitude and duration representative of the Human Body Model (HBM) event (or a Charged Device Model – CDM – event in the case of Very Fast TLP, or VF-TLP). The incident and reflected pulses are evaluated, and a voltage-current (V-I) curve is developed that describes the response of an ESD protection structure to the applied TLP stresses. The Transmission Line Pulse current pulses can be on the order of amps, and the TLP test results can show the turn-on, snap-back, and hold characteristics of the ESD protection structure.
Transmission Line Pulse testing is useful in two very important ways. First, TLP may be used to characterize Input/Output (I/O) pad cells on test chips for new process technologies and Intellectual Property (IP). TLP results are very useful in developing simulation parameters, and for making qualitative comparisons of the relative merit of different ESD protection schemes for innovative pad cell designs. Secondly, TLP may be used as an electrical failure analysis tool, often in combination with conventional, standards-based component ESD testing.
TLP test services are quoted on a case-by-case basis, based on the scope of the work requested; estimated engineering time to perform the test and customer requested reporting. Please kindly fill out below service requirement form with your test configurations for the quote purpose.
Related Standards: ANSI/ESD STM5.5.1-2016, IEC 62615:2010
Test Capability (customized setup available upon request):
TLP and VF-TLP testing can provide a comprehensive ESD characterization for devices. TLP (pulse width of 100ns, typically) is often used to generate an IV curve which can be analyzed to understand many of a device’s ESD protection characteristics such as dynamic resistance, trigger voltage, hold voltage, and current, and second breakdown (Vt2/It2). A VF-TLP test is often used to understand the transient response of a DUT. Initial voltage peak and turn-on time can be measured and may play a large role in choosing the best protection device for a design. When analyzing this data, it is important to understand the device under protection and the system operating conditions.
In design applications where signal integrity is important, low-loss devices at the frequencies of interest should be selected. ESDEMC’s S21 measurements will provide the customer with insertion loss data up to 18GHz. Temperature and DC bias control are available upon request.
Capacitance is a component parameter that can be crucial for circuit design, whether it is in a low frequency or high-frequency application. Protection devices and capacitors have an expected and desired capacitance that may be important for signal integrity or general circuit operation. Based on the frequency, temperature, and DC bias applied to the DUT, the capacitance may be much different than expected. ESDEMC’s VNA capacitance measurements allow for capacitance measurements to be taken at a specific DC bias level and temperature. The capacitance can be measured using VNA S- parameters swept up to 18GHz.
Capacitance is a component parameter that can be crucial for circuit design, whether it is in a low frequency or high-frequency application. Protection devices and capacitors have an expected and desired capacitance that may be important for signal integrity or general circuit operation. Based on the frequency, temperature, and DC bias applied to the DUT, the capacitance may be much different than expected. ESDEMC’s LCR capacitance measurements allow for capacitance measurements to be taken at a specific DC bias level and temperature. The capacitance can be measured at frequencies lower than the VNA measurement method can achieve. The typical measurement frequencies are taken at 1 MHz – 10 MHz.
High frequency protection devices often generate harmful and unwanted harmonic frequencies. The power of these undesirable harmonics may play an important factor in selecting the proper device for a design. ESDEMC’s harmonics generation measurement provides harmonic power data that will aid in making these design decisions. Base frequencies of 900MHz, 2.4GHz, and 5GHz can be injected into the DUT at power levels ranging from -30dBm to +30dBm. Resulting second and third harmonic power levels will be measured. Custom frequency and power ranges may be measured upon request.
IEC ESD Simulator testing is a qualification requirement for designs, mostly system level. The system-level tests are well-outlined in the IEC standard and are often simply pass/fail. Device level tests are performed in the industry as well, but these tests are also often simply pass/fail. ESDEMC’s ESD Simulator Clamping measurements provide more than just pass/fail data for device-level ESD Simulator tests. Transient voltage for each applied ESD pulse is measured and provided for a better understanding of the DUT’s ESD clamping response. Standard ESD Simulator pulse levels are +/-8kV, but other levels can be applied upon request.
Based on TLP and vf-TLP test results, ESDEMC will generate a device model if requested. Positive and negative IV characteristics will be matched with TLP results, and transient vf-TLP turn-on behavior will be modelled at various pulse levels. Board-level modelling may also be possible, but it should be discussed prior to testing. Advanced Design System (ADS) and Spice are the standard simulation programs used to generate these models, and models can be made “classified” when intellectual property is a concern. This allows users to share their device models with others without revealing the internal model components.
While TLP provides clean rectangular pulses up to 100’s of nanoseconds (and pulses with sag up to a couple microseconds), some test applications require much longer pulse duration. For these applications, ESDEMC provides long pulse EOS testing. The EOS is a solid-state pulser that can output clean rectangular pulses from 200ns to 1ms at very fine steps. By default, this is a 50-ohm pulser like the TLP, but different output impedances can be configured if requested. This may be useful in higher-current pulsing. The 50-ohm EOS can output pulses up to 1kV. These tests are often useful for generating SOA curves, Wunsch-Bell curves, or just analyzing transient behavior across a longer timescale.
Many protection devices require a surge rating for qualification. ESDEMC provides its low voltage surge testing service to aid in understanding component surge performance. ESDEMC’s surge test systems will inject a surge pulse into the device, capture the transient voltage and current, test for failure, and move onto the next pulse level. Not only does automation of surge testing set ESDEMC apart from other surge testers, but ESDEMC’s testers output linear in-spec waveforms from 500mA up to >250A. The standard available waveforms are the 8/20us and 10/1000us surges.
Cable discharge events occur when a cable, such as ethernet, HDMI, or USB, is plugged into a system whose potential differs enough to cause an electrostatic discharge. These discharges can be detrimental to the board or system. Factors such as cable charge level, cable length, and pin contact sequence can affect the severity of the discharge. ESDEMC provides a means of discharging different cable types of specific length and voltage into your board or system. Pin contact sequence can be controlled, and the electrical state of each pin can be set prior to discharge. The discharge current waveforms can be saved and captured for up to 8 pins, and failure analysis can be performed by request.