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PB2022.02 Improved Design of Flange Mount Coaxial Connector with Low Passive Intermodulation Distortion

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Abstract—Imperfect electrical connections cause multiple problems in radio frequency (RF) measurements, passive intermodulation (PIM) being the most common one. This paper proposes a new design approach to reduce the PIM distortion caused by the imperfect electrical connection in flange mount coaxial connectors. The proposed approach employs a flexible ring embedded in the outer conductor of the flange mount coaxial connector to improve the reliability of the metal electrical connection. A simulation model is further developed to analyze the effects of the embedded ring on the signal transmission performance. The effectiveness of the proposed approach is verified by experiments, demonstrating that the improved design can not only decrease the PIM level by up to 9 dB, but also show a good reliability and stability in the conditions requiring repeated connection and disconnection, and thus, this method has the potential for the application of all flange mount devices.

Index Terms—Passive intermodulation, flange mount coaxial connector, imperfect electrical connections, contact faults.

I. INTRODUCTION

Passive intermodulation (PIM) is the distortion generated by weak nonlinear characteristics in passive devices such as connectors, multiplexers, etc. [1]-[3]. When two fundamental frequencies (f1, f2) are considered, the possible frequency components of PIM distortion can be described as fN(PIM) =mf1+nf2, where m and n are the coefficients of the fundamental frequencies, N is the order of PIM products, which can be calculated by N=|m|+|n|. The third-order PIM frequencies (2f1-f2, 2f2-f1) are very close to the fundamental frequencies, and thus are difficult to be eliminated by filters [4], [5]. Therefore, reducing PIM distortion in microwave circuits and RF measurement systems is challenging and relies on the design of low PIM devices.

Flange mount coaxial connectors, which have been used extensively to connect printed circuit board (PCB) or flange devices, are the main contributions to the PIM distortion [6], [7]. Three different kinds of sources, the nonlinear oxide (contaminant) films, the ferromagnetic material plating, and the imperfect electrical connections, are considered as the dominant reasons for PIM distortion in coaxial connectors [8]. Sources of both nonlinear oxide (contaminant) films and ferromagnetic material plating have been well concerned [9]- [11]. For example, in [9], the effects of coating materials and iron content in base brass on PIM performance have been investigated. In [10], the PIM distortion caused by aluminum plating-oxide films has been analyzed. In [11], the design guideline and plating standards have been proposed to minimize PIM generation in RF cables and connectors. However, to the best of authors’ knowledge, only a limited number of contributions have focused on the theoretical analysis for the source of imperfect metallic contact [12], [13], the manufacturing approaches for reducing the PIM distortion caused by imperfect electrical connections have not been sufficiently estimated. In practical situations, the manufacturing error, slight deformations of the contact surface, or tightened with insufficient torque, could potentially leads to an imperfect electrical connection in the flange mount surface when connected. Therefore, it is of great importance to design the high-reliability flange mount coaxial connector to reduce the PIM distortion and then improve the performance of the devised RF measurement system.

This paper proposes a modified design to improve the connection reliability and lower the PIM distortion generated by the imperfect electrical connection in N-type flange mount connectors, and this work is organized as follows. In Section II, the structures of the flange mount coaxial connectors are analyzed to investigate the physical mechanism and potential reasons for generating PIM distortion due to the imperfect electrical connection. In Section III, the improved design method is proposed, and the dimension and plating materials of the modified ring are further analyzed to minimize the PIM distortion in the flange mount coaxial connector by imperfect metallic contact. In Section IV, transmission characteristics, including the S21-parameter, the contact impedance, and the transmission loss for the improved design method are discussed to investigate the effect of structural changes on the quality of signal transmission. In Section V, experiments are conducted to validate the effectiveness of the proposed design method. Section VI draws a conclusion for this paper.

II. STRUCTURE ANALYSIS OF FLANGE MOUNT CONNECTORS

To aid visualization and completely understand the physical mechanisms of imperfect electrical connection in the flange mount devices, a photograph of a typical N-type flange mount coaxial connector is shown in Fig. 1. As can be observed in Fig. 1(a), the dimension of the flange mount surface is larger than that of the insulator. The flange mount surface is a square of a side-length 25.4 mm with an area of 645.2 mm2 , and the diameter of the insulator is 9.8 mm with an area of 75.4 mm2 . Accordingly, the area of the flange mount surface is approximately nine times larger than that of the insulator so that the imperfect metallic contact may occur in the flange mount surface with ease. This because the large flange mount surface could be slightly deformed as a result of manufacturing error, tightened with unequal torque on 4-mounting holes. Meanwhile, the outer conductor of the coaxial connector is the inner circle of the flange mount surface. The above two reasons lead to the imperfect metallic contact being easily occurred in the outer conductor of the N-type flange mount coaxial connector, and this phenomenon is further depicted in Fig. 1(b). On the left side of the flange mount surface, a small gap could exist between the flange mount surface and the corresponding connection female due to the deformation of the interconnected surfaces, resulting in the imperfect metallic contact of the N-type flange mount coaxial connector.

From the previous studies [6], [13], two critical factors are responsible for the PIM distortion generated by the imperfect metallic contact, i.e., the electro-thermal (ET) coupling and the variation of the nonlinear oxide (contaminant) films. For the ET PIM, the additional junction impedance emerges and increases with the imperfect metallic contact level, this causes significant self-heating of the connective junction in high-power microwave circuits. On the contrary, the material property, such as metal resistivity, is changed because of the self-heating. Therefore, the resistivity of the junction is nonlinear, and then the ET PIM is generated. For the oxide (contaminant) films PIM distortion, the self-heating accelerates the process of oxidation and increases the thickness of the nonlinear oxide films. Nevertheless, the additional junction impedance makes much more current through nonlinear oxide (contaminant) films, which further deteriorates the PIM level.

Specifically, as shown in Figs. 2(a) and 4(a), a method that designs a gasket on the outer conductor of the traditional flange mount surface has been proposed in industry to reduce the probability of the imperfect metallic contact. Generally, the width d and the height h of the gasket are designed ranges from 0.80 mm to 2.00 mm and 0.12 mm to 0.20 mm respectively.

Although the gasket method can enhance the connection reliability and reduce PIM distortion in the first few uses, the stability of repeated connections and disconnections in the course of service is unsatisfactory. This is due to the fact that, 1) the gasket is the main acceptor of the connection forces between the flange mount surface and the corresponding connection female. 2) the area of the flange mount surface is much larger than that of the gasket. These factors make it easy to have a plastic deformation in the corresponding part of the gasket under the conditions of over-standard tightening torque or requiring frequent connections and disconnections (the element after plastic deformation does not fully recover its original shape).

In summary, the gasket method can improve the connection reliability and diminish PIM level in the first few uses. However, when in the situations requiring frequent disconnection and reconnection, the gasket method may have more serious PIM distortion than the traditional N-type flange mount coaxial connector.

III. DESIGN FOR THE IMPROVED METHOD

In an effort to cure the deficiencies of the proposed gasket design method, in this section, we will provide a modified ring method that is composed of two parts, namely the stress ring and the conducting ring. As shown in Fig. 2(b), the stress ring has the same size as the gasket in Fig. 2(a), the conducting ring is embedded in the stress ring as the outer conductor for the flange mount coaxial connector to transmit the signal. Nevertheless, as illustrated in Figs. 3(a) and 4(c-e), the conducting ring is divided into many ring petals by slots so that there is a small gap between two neighboring ring petals. Therefore, when a connection force is applied in Figs. 3 (c), and 4(e), the ring petals are bent in response to the contact pressure, and then the stress ring will be the main acceptor for the contact pressure. In other words, the imperfect metallic contact and plastic deformation can be avoided in the signal transmission component because the parts for receiving the contact pressure and transmitting the signals are separated (the conducting ring is employed to transmit the signal and only occurs elastic deformation; the stress ring is used to receive the contact pressure and may generates plastic deformation). In addition, the parameters design on the dimension and plating for the modified ring method is discussed as follows.

A. Dimension Design for the Modified Ring

Similar to the gasket in Fig. 2(a), the stress ring is also the main acceptors for the connection forces, therefore, the stress ring and gasket have the same dimension and material, and both need to be heat-treated to improve the hardness. In practical situations, the hardness of them ranges from 28 HRC to 32 HRC, here, HRC represents Rockwell C scale hardness. As shown in Fig. 2(b), the height and width of the conducting ring are l and w, respectively, which refer to the skin depth and plastic deformation of the ring petals. The reasons are summarized as follows.

1). Almost all the conducting current is concentrated in the inner side of the conducting ring on account of the skin effect. Hence, for the integrity of the transmission signals, the width w must be larger than that of the skin depth. For example, as the frequency of the transmitted signal is 30 MHz, the skin depth of brass can be calculated as 24.3 μm (resistivity: ρ=6.98×10-8 Ω/m, relative permeability: μr=0.99994). Therefore, the minimum width w of the Conducting ring should be greater than 24.3 μm.

2). With the same connection force, increasing the height l or decreasing the width w can increase the electric contact reliability. However, as the electric contact level or the deformation of the conducting ring exceeds their limits, the plastic deformation will occur. Therefore, the dimensions of the conducting ring are necessitated to enable the N-type flange mount coaxial connector tightly connected and avoid plastic deformation. In other word, the stress ring should withstand the contact pressure absolutely before the conducting ring is deformed with plastic bending.

Taking the designing principles above into account and considering the tightening torque for all four mounting screws is 3.0 N·m, the width w and the height l of the conducting ring are designed ranges from 0.15 mm to 0.30 mm and 0.25 mm to 0.40 mm, respectively.

B. Plating Design for the Modified Ring

Electroplating can significantly increase the electrical conductivity, corrosion protection, and wear resistance of coaxial connectors. As aforementioned, the skin effect makes almost all transmitted currents concentrated on the surface of the conducting ring, and the stress ring is the main acceptors for the connection forces. Therefore, it is important to plate the conducting and stress rings to enhance the conductivity and wear resistance, respectively.

From the aspect of the practicality and economy, the plating thickness of the conducting and stress rings are designed both from 20 uin to 50 uin (uin: micro inch, 0.50 μm to 1.25 μm). However, the stress ring is plated with nickel to improve the performance of corrosion protection and wear resistance. Two metals, gold and tri-metal alloys (55% Copper, 30% Tin, 15% Zinc), are selected as the plating materials for the conducting ring. Specifically, the plating metal of tri-metal alloys is used in a common sensitivity environment of the PIM distortion. Hence, for the applications, where high PIM sensitivity and electrical conductivity are required, the noble metal (silver, gold, and others) is the optimal choice for plating the conducting ring.

IV. SIMULATIONS FOR THE MODIFIED RING

In this section, the transmission characteristics, including the S21-parameters, the contact impedance, and the transmission loss will be analyzed by simulations to investigate the modified ring structure impacts on the transmission performances for the flange mount coaxial connector. Figs. 3 & 4 show the structures of the simulation model. A voltage source is applied at the left terminal of the simulation model (Fig. 4(f)) to generate a Gaussian pulse excitation signal. At the other end of this model, a 50 Ω load is employed to match the characteristic impedance. Three different kinds of flange mount surfaces are considered, namely the traditional design method (Fig. 1(a)), the gasket design method (Fig. 4(b), and the modified ring design method (Fig. 4(c)). In addition, the side-length of flange mount surface is 25.4 mm, the diameters of the inner conductor and insulator are 3.0 mm and 9.8 mm respectively. The width d and the height h of both the gasket and the stress ring are 1.20 mm and 0.20 mm respectively. The width w and the height l of the Conducting ring are 0.15 mm and 0.30 mm.

In this paper, we will take the mobile communication system of GSM1900 as an example to analyze the PIM distortion in the N-type flange mount coaxial connector. The transmitter and receiver frequency bands for the GSM1900 range from 1930 MHz to 1990 MHz and 1850 MHz to 1910 MHz respectively. Two carriers, f1=1935 MHz and f2=1985 MHz, are selected as the excitation signal, and thus the third order PIM distortion product can be calculated as f3(PIM)=1885 MHz.

Figs. 5-6 show the simulated results of the S21-parameter, the transmission loss, and the contact impedance in the flange mount surface for the above three cases. it is important to notice that, the transmission characteristics of the modified ring method are not only in good agreement with that of the gasket method but also with that of traditional method. Not only that, we have further measured the S21 and S11 parameters for the three different types of flange mount connectors mentioned above, and the measurement results are shown in Fig. 7, which is confirm that all connectors used in measurements have the similar transmission and reflection characteristics.

Therefore, the results of both simulation (Figs. 5-6) and measurement (Fig. 7) indicate that the effect of the structural changes (traditional design → gasket design → modified ring) on the critical transmission characteristics can be ignored. In other word, it proves that the modified ring design method can enhance the connection reliability and stability, but does not degrade the performance of signal transmission.

V. VERIFICATION

For validations, the test setup is composed of a PIM tester, a device under test (DUT), and a terminal load (50 Ω). CCI PiMPro1921 is used as the PIM tester to generate excitation signals and display the reflective PIM values, and the output accuracy of the used PIM tester is 0.3 dB. The 50 Ω terminal load with the feature of low reflection PIM is employed to dissipate the transmitted power.

The DUT is essentially a micro-strip line and connects the PIM tester and the terminal load with two N-type flange mount coaxial connectors. As shown in Fig. 8, the connector on the right side of the micro-strip is a traditional N-type flange mount coaxial connector, however, the connector on the left side of the micro-strip is the employed test sample. Four types of samples, as detailed in Table I, are considered to evaluate the effects of the modified ring design on the PIM levels. It is important to notice that all test samples in measurements are brand new (so that, the effect of the oxide (contaminant) films on PIM distortion can be ignored), and the standard tightening torques for all four mounting screws are 3.0 N·m.

In experiments, the measurement conditions are set as shown in Table II, where, three connection cases of the standard, under-standard, and over-standard are considered in this work. The measurement on the third-order PIM results for the standard connection case is shown in Fig. 9. It is observed that, as the standard tightening torque is applied, the values of PIM distortion can be decreased up to 9 dB by designing the gasket or modified ring on the outer conductor of the traditional flange mount surface (comparing samples B, C with A), and the noble metal (gold) plating can further reduce the PIM distortion levels (modified ring D).

As shown in Table II, for the under-standard connection case, a slight imperfect contact is generated in the flange mount surface because the tightening torque applied to one mounting screw is insufficient (2.0 N·m). Fig. 10 shows the measured third-order PIM values for the under-standard connection. Comparing the measured results of the under-standard case with the standard cases, it is important to notice that the imperfect metal contact can deteriorate the PIM level (the PIM level of traditional A′ is higher than that in traditional A), but we can improve the connection reliability and diminish PIM level by adding a gasket or modified ring on the outer conductor of the traditional flange mount surface (the PIM distortions of samples B, B′, C, and C′ are almost on the same level).

For the over-standard connection case, the employed samples have been repeated connection and disconnection 20 times with the tightening torque 5 N·m, which means the plastic deformation has generated in the connection surface before the PIM test. Fig. 11 shows the third-order PIM results for over-standard connection case. It is observed that, the frequent connecting and disconnecting or over-standard tightening torque can significantly deteriorate the PIM level for the gasket method (Comparing the measured results of gasket B″ with gasket B). However, the PIM level of the modified ring method is almost the same as its original value (the PIM levels of modified rings C and C″are almost in the same range), this is due to the fact that the components for receiving the contact pressure and transmitting the signals are separated in the modified ring method, and thus the frequent disconnection and reconnection or over-standard tightening torque impacts only on the component of receiving the contact pressure, for the component to transmit the signals, the effect can be ignored.

Specifically, from Figs. 9-11, the differences between each two traces are larger than the measurement accuracy of the used PIM tester, and we can further find that the third-order intermodulation does not meet 3 dB/dB relationship with the input signal power, which can be explained by the fact that, a system is usually made up of linear and nonlinear components, the interaction between the linear and nonlinear elements of a system can dramatically transform the overall nonlinear behavior of the system from that of the nonlinear component in isolation [14], [15].

VI. CONCLUSION

In this paper, an improved design for minimizing the PIM distortion in the flange mount connectors has been proposed. Both the detailed design and verification have been provided. Specifically, to meet the requirement of repeated connections, this design has added two components for receiving the contact pressure and transmitting the signals respectively.

From the investigation in this paper, the proposed design method can not only significantly decrease the PIM distortion level caused by imperfect metallic contact, but also increase the reliability and stability for the flange mount coaxial connector in the conditions of over-standard tightening torque or requiring frequent disconnection and reconnection. Furthermore, this work has the potential to extend for all flange mount devices in engineering.

ACKNOWLEDGMENT

The authors would like to thank Dr. Yihong Qi, for his helps in technical supports and in the manufacturing the test samples.

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PB2022.01 Analysis of Passive Intermodulation Distortion Caused by Asymmetric Electrical Contact

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Abstract— This article investigates the passive intermodulation (PIM) distortion induced by the asymmetric electrical contact. Based on the analytical model, it is found that the increased current path is the cause of the additional impedance, resulting in PIM distortion. To validate our theoretical analysis, different levels of asymmetric electrical contact are studied via simulation and experiments. The demonstrations not only confirm the validity of our theoretical findings, but also substantiate the simulations. To the best of our knowledge, this work is the first to identify the asymmetric electrical contact as a PIM source and discuss its underlying physical mechanisms of causing electrothermal (ET) coupling PIM.

Index Terms— Asymmetric electrical contact, electrical contact failures, electro-thermal (ET) coupling, passive intermodulation (PIM)

I. INTRODUCTION

Passive intermodulation (PIM) distortion is a frequently encountered issue in microwave circuits and wireless systems. PIM phenomenon is caused by slight nonlinearities stemming from nonlinear material or nonlinear metallic contact. In the past decades, many physical mechanisms, namely electro-thermal (ET) coupling, ferromagnetic materials, tunneling effect, and field emission, are considered as PIM sources [1]–[4].

The ET coupling generally has not been considered as a dominant PIM mechanism in the traditional sparse frequency bands and low-power telecommunications [5]. However, with the further development of wireless technologies (e.g., high power, high frequency, and base station supporting 3G/4G/5G simultaneously), the ET PIM distortion, especially induced by electrical contact failures, needs to be addressed carefully.

In practical scenarios, the poorly soldered joints, oxidation, and corrosion of junctions in the courses of service, and minor deformations of the connection surfaces may lead to electrical contact failures in microwave circuits [6]. According to prior research [7], electrical contact failure increases the contact impedance of the connection surface. Typically, in high-power and high-frequency circuits, the increased contact impedance (additional impedance) will lead to significant self-heating. Furthermore, the material properties, such as metal resistivity, change as self-heating conditions vary. In other words, this bidirectional interaction between the electromagnetic domain (dissipated electrical power and the resultant self-heating) and the thermal domain (temperature rise and the consequent change in the metal resistivity), gives rise to temperature oscillations and resistivity variations. Therefore, the ET PIM distortion emerges due to the nonlinear contact impedance [8].

Specifically, electrical contact failures will increase the noncontact areas and lead to asymmetric electrical contact in the connected surface, that is, there are two important factors responsible for the ET PIM caused by electrical contact failures: one is the increased noncontact areas, while the other is an asymmetric electrical contact. In [9] and [10], PIM distortion induced by the additional impedance of the increased noncontact areas has been analyzed. In [11], the theories for ET PIM caused by the electrical contact failures have been studied, and a numerical expression was derived to calculate the PIM distortion related to the contact impedance. However, the impedance induced by the asymmetric electrical contact has been ignored, which renders the PIM distortion evaluated by the theoretical analysis insufficient.

In this article, we take a pair of faulty coaxial connectors as a case study to investigate the ET PIM distortion caused by the asymmetric electrical contact, and this work is organized as follows: Section II develops an analytical model of the asymmetric electrical contact, considering the case of coaxial connectors. In Section III, simulations are conducted to validate our theoretical analysis. In Section IV, experiments are conducted to check the goodness of the model and the consistency of the simulation results. Finally, Section V draws a conclusion of this article. In summary, the main contributions of this work are that it, for the first time, reveals the asymmetric electrical contact as a PIM source and discusses its underlying physical mechanisms, which will facilitate further improvements of the accuracy of PIM predictions and measurements related to the electrical contact failures.

II. ANALYSIS OF ASYMMETRIC ELECTRICAL CONTACT

A. Analytical Model for the Asymmetric Electrical Contact

To aid visualization and better understanding of the asymmetric electrical contact, a used coaxial connector sample is shown in Fig. 1, where the black solid/dashed lines enclose the actual contact areas of the female/male coaxial connectors. On the inner conductor of the coaxial connector, there are some small deformations. This makes the connected petals between the male and female coaxial connectors slightly unaligned, which increases the noncontact areas in the outer conductor and creates asymmetric electrical contacts in the inner conductor. In other words, the asymmetric electrical contact emerges and increases with the deformation levels of the connection surface.

As previously stated, the impedance is the dominant contributor to ET PIM, and a numerical relationship between the ET PIM and the impedance for lossy component has been developed by (33) in [8]. Therefore, the key to understanding ET PIM distortion caused by asymmetric electrical contact is to analyze the increased contact impedance, that is, when the associated physical mechanisms for the increased contact impedance are well understood, the ET PIM can be accurately calculated.

Fig. 2 shows the analytical model of this work, where two cases of symmetric and asymmetric electrical contact are considered to analyze the impedance characteristics in the connection surface. The total contact areas are the same in both cases, that is, A1 = A0 = B1 = B0 = C1 = C0, but one focuses on the symmetric contact (the left side of Fig. 2), while the other studies the asymmetric contact (the right side of Fig. 2). It is evident that the total lengths of the current paths in the asymmetric contact are longer than that in the symmetric contact. For example, the red solid line in the asymmetric noncontact area A1 is longer than that in the symmetric noncontact area A0.

From the classical electrical contact theory [6], the contact impedance increases with the length of the current path through the connection interface. Therefore, the asymmetric electrical contact creates more contact impedance than the symmetric electrical contact. Furthermore, the increased impedance is proportional to the level of asymmetry, which means the severer the asymmetry of the electrical contact is, the more additional impedance will be induced.

B. Simulations for the Asymmetric Electrical Contact

A simulation model of a typical 7/16 DIN coaxial connector, which is built in CST Microwave Studio, is employed to analyze the asymmetric electrical contact. As shown in Fig. 3, the length of the model is 20 mm. The inside diameter of the outer conductor and the outside diameter of the inner conductor are 16 and 7 mm, respectively. The thickness of the noncontact areas is 0.3 mm, and the asymmetric contact occurs at 10 mm from the right end. Materials for the contact and noncontact areas of the simulation model are white bronze (conductivity: 5.96 × 107 S/m) and air (εγ = 1.0059), respectively.

Four cases, namely the symmetric contact, small asymmetry, medium asymmetry, and severe asymmetry, are designed and implemented to investigate the increased contact impedance in different asymmetric contact conditions. Fig. 4 shows the simulation results for these four cases. Here, the variable


Z, which is the additional impedance, is the difference between a certain asymmetric electrical contact case (e.g., severe asymmetry) and the symmetric contact case when the peak impedance occurs. It is important to notice that, as there is a symmetric contact, the additional impedance


Z emerges and increases with the asymmetric contact level. Therefore, the simulation results correlate well with the analysis in the analytical model.

C. PIM Expression for the Asymmetric Electrical Contact

The ET theory has demonstrated that the ET PIM distortion originates from the nonlinearity of the impedance [8], Specifically, for the coaxial connector, the ET PIM can be written as

where k belongs to the natural numbers, Z is contact impedance of the connected interface, in(t) is the current through the connected interface, α is the temperature coefficient, and Tα is the ambient temperature. Rth.eq. is the equivalent thermal resistance, which is related to the thermal capacitance Cth, thermal resistance Rth, and carrier angular frequency ω, meeting the relationship as [12]

Typically, the third-order PIM frequencies are very close to the fundamental frequencies and thus are difficult to be eliminated by filters. Below, we will take the third-order PIM distortion as an example to understand the generation of ET PIM by the asymmetric electrical contact. Usually, the magnitude of the temperature coefficient α is in the order of 10−3, thus, the ET PIM distortion from the number of k ≥ 2 can be ignored, and then the third-order ET PIM distortion can be approximately expressed as

Furthermore, as the current signal in(t) is composed of two carriers, n 1, 2, with amplitudes In, frequencies fn, and angular phases ϕn, mathematically

where ωn = 2π fn , then the third-order ET PIM distortion generated by the asymmetric electrical contact can be further rewritten as

where Z0 is the contact impedance of the connected interface with the symmetric electrical contact and


Z is the additional impedance caused by the asymmetric electrical contact.

III. DEMONSTRATIONS

It has been analyzed and simulated in Section II that the asymmetric electrical contact induces an additional contact impedance, resulting in ET PIM distortion. In this section, experiments are conducted to verify the impacts of the asymmetric electrical contact on PIM distortion, and the measurements are made in the mobile communication system of GSM1900, that is, the transmitter/receiver frequency bands of the experiments range from 1930 to 1990 MHz and 1850 to 1910 MHz, respectively.

A 7/16 DIN coaxial connector is employed as the device under test (DUT), and different levels of asymmetric electrical contacts are achieved by embedding copper on the different locations of the inner or outer conductor surfaces. Since the height of the embedded copper is a bit higher than that of the outer/inner conductor surface, and therefore, when the male and female coaxial connectors form a connection, the contact areas are only consisted of the embedded coppers, which means the asymmetry can be controlled by changing the locations of the embedded coppers.

Furthermore, three cases of different symmetry have been designed in experiments, which are the symmetric contact [Fig. 5(a)], the medium asymmetric contact [Fig. 5(b)], and severe asymmetric contact [Fig. 5(c)]. They have the same contact area, but the symmetry is different, that is, the embedded coppers for the three cases are the same dimensions, but they are embedded in different locations (the total area of the embedded coppers is one-quarter of the apparent contact area of the 7/16 DIN coaxial connector).

As illustrated in Fig. 5, the reflected PIM testing technology is used for the principle of the PIM analyzer; in other words, the PIM tester first generates a dual-tone excitation signal ( f1 = 1935 MHz, f2 = 1985 MHz) to the DUT, and then the reflected third-order PIM values from the DUT are measured and displayed on the PIM tester.

Fig. 6 shows the measured and predicted results for the three asymmetric electrical contact cases in Fig. 5. Two conclusions can be drawn from Fig. 6: 1) the third-order PIM distortion is directly proportional to the level of asymmetric electrical contact (symmetric contact → medium asymmetric contact → severe asymmetric contact) and 2) the nonlinearity of the PIM distortion is also confirmed because there is not a fixed step between all the curves.

Meanwhile, it is important to notice that the predicted PIM value is lower than in measurement. This is due to the fact that, in practical scenarios, the connected surface may have other PIM source (e.g., electron tunneling effect), which has been ignored in the theoretical analysis. Furthermore, the PIM values of both measured and predicted are greater than that of the reference because when embedding the coppers, the real contact area of the connected surface is reduced. In summary, the experiments quantitatively and qualitatively demonstrate that the asymmetric electrical contact is a PIM source.

IV. CONCLUSION

Although it is well known that the electrical connection failures generate the ET PIM distortion, it is not very clear how it works for asymmetric connection scenarios. In this work, the underlying relationship between asymmetric electrical contact and ET PIM has been studied. It is revealed that the asymmetric electrical contact could increase the path length of the transmitted current through the connection interface, and the increased current path in turn leads to the emergence of additional impedance. Furthermore, the PIM distortion was generated in response to the ET coupling caused by the additional impedance. This conclusion will facilitate improved prediction and suppression of the ET PIM distortion from the asymmetric electrical contact and can also be extended to other types of connectors or soldered joints.

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PB2021.10 Study of CDM Relay Pogo-Contact First CDM and CC-TLP Pulses

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Abstract – The recently proposed RP-CCDM testing method is tested alongside the more established CDM and CC-TLP methods on two test ICs to assess the RP-CCDM’s efficacy as an alternate test method. High bandwidth analysis of field induced CDM spark events is presented to evaluate higher frequency components of the current.

I. Introduction

A CDM event occurs when the pin of a charged device approaches an external metal object such that the potential difference exceeds the breakdown voltage of the air gap between them. CDM is one of the most common ESD threats in modern manufacturing and usage environments. The current industry standard testing method is the Field Induced CDM (CDM) method governed by the ANSI/ESDA/JEDEC JS-002 standard [1]. Current CDM testers are plagued with repeatability issues due to the variable spark resistance of the air discharge making the practice difficult to standardize [1, 2]. Additionally, decreasing CDM testing voltages increase the pulse-to-pulse variability of the air discharge, causing concern over the ability to meaningfully classify devices at lower voltages [3]. This is becoming increasingly problematic as the necessity for classification at lower levels is becoming greater with advances in IC technology [2]. Several contact-first CDM methods where a CDM current is induced into the pin through a more controllable method, such as the CC-TLP, LICCDM, and RP-CCDM, have been introduced in an attempt to solve the issue of pulse variability [4, 5, 6].

This work presents a correlation study between the CDM, RP-CCDM and CC-TLP testers on two devices with well-known CDM failure levels and failure mechanisms. The devices are subjected to a series of RP-CCDM and CC-TLP tests with multiple risetimes. The study aims to evaluate the efficacy of the RP-CCDM method and gain insight into the correlation of RP-CCDM and CC-TLP to better understand their potential as replacements for CDM susceptibility testing.

II. CDM and CC-TLP Tester Configurations

A. RP-CCDM Tester

The RP-CCDM, or Relay Pogo-Contact First CDM, is a design of the CDM discharge head that allows the use of a repeatable relay discharge while largely preserving the design parameters of the JS-002 standard. Figure 1 shows a cross section of the RP-CCDM head.

As shown in Figure 1, the RP-CCDM uses the field charging method and a similar discharge path to the one specified in the JS-002 standard. To charge the device, the pogo pin of the RP-CCDM ground plane is lowered to contact the DUT pin, then the field plate is brought to the specified charge voltage. To discharge, the reed switch is closed and the current primarily flows up the pogo pin, through a high bandwidth 1 Ω resistor, and returns via the ground to field plate and DUT capacitances. A more detailed testing procedure for the RP-CCDM is presented in [6].

The RP-CCDM prototype head used for stressing devices in this study was found to adhere to the discharge waveform parameters specified in the JS-002 standard. The RP-CCDM prototype was also found to have a strong correlation in peak currents to the peak values measured with a CDM head across a range of coins with varying CDUT values.

B. ACRP-CCDM Test Setup

The RP-CCDM and CDM test are different in two key aspects that could be the source of correlation issues. First, the RP-CCDM spark takes place in a controlled environment free of air. This difference results in a much more reproducible spark environment that reduces the variability of the peak current when compared to air discharge CDM and enables testing below 100 V [6]. The altered spark environment may also influence the risetime and result in less damping of the system due to a smaller series spark resistance value. Second, the geometry of the RP-CCDM head is different from that of the CDM to accommodate the reed switch. Specifically, the pogo structure is no longer uniform in thickness and longer than in CDM, which will affect the inductance of the discharge path. To further investigate the role of these two variables the “Always Closed” RP-CCDM (ACRP-CCDM) test method was implemented. This test method uses the existing RP-CCDM test setup but alters the testing procedure to close the reed switch in the pogo pin prior to descent such that a CDM-like air spark is created. This method removes the reed switch spark variable and reveals differences between CDM and RP-CCDM based on the test head geometry alone.

To evaluate differences in the rising edge, or any other part of the current waveform, RP-CCDM, ACRP-CCDM, and CDM tests were performed using a 23 GHz bandwidth Tektronix MSO72304DX oscilloscope and a low loss measurement chain. The insertion loss of the measurement chain, shown in Figure 2, was less than 2 dB up to the 23 GHz measurement bandwidth of the oscilloscope. The same model of disk resistor was used for the construction of both heads with the resistive sheet facing away from the pogo-pin, this type of disk resistor has been characterized up to 26.5 GHz in [7]. The DC resistance value was used for current measurement scaling.

Figure 3 displays the five highest peak current pulses captured from a set of fifty discharges on a small JS-002 verification module at TC500. These pulses represent the lowest spark impedance discharges for each tester. The initial rising edge of the CDM and RP-CCDM pulses is observed to be similar, although the CDM rising edge reaches a higher peak in the first 50 ps and the RP-CCDM reaches a higher peak in the first 80 ps. The ACRPCCDM current measurement has a rising edge more similar to that of the CDM pulse, possibly indicating a relationship between the rising edge and the air spark event, whereas for the rest of the measurement duration the ACRP-CCDM pulse matches the curve of the RP-CCDM current indicating a relationship with the test head geometry. The risetime of the RP-CCDM does not exhibit any characteristics that indicate a faster risetime than its air spark counterparts. The RP-CCDM slew rate may be faster on average, however, due to degradation in the CDM slew rate during discharges with high series spark resistance. Figure 5 displays the frequency spectrum of each pulse shown in Figure 3.

In [7], it was observed that the high frequency content seen in the CDM and RP-CCDM spectrum is likely related to the pogo pin length and the disk resistor. As shown in Figure 5, the high frequency content observed in the RP-CCDM spectrum is quite similar to the content seen in the ACRP-CCDM spectrum, indicating that the RP-CCDM relay spark does not introduce any unwanted resonances. Whether the current measurements in Figure 3 and the structure resonances seen in Figure 5 are indicating the true current magnitude that is traveling though the IC pin during a CDM stress is not yet fully understood but is currently being investigated. The presence of the high frequency current components that occur in field induced CDM events could be an important factor in determining the efficacy of alternate test methods on sensitive ICs.

C. CC-TLP Test Setup

The CC-TLP method utilizes a VF-TLP pulse into to a single IC pin and a capacitively coupled return path to create a CDM equivalent stress [4]. CC-TLP is a contact-mode tester and as such has the advantage of having much lower pulse to pulse variability than a standard CDM test with an air spark. The CC-TLP method also allows correlation between peak current levels and pulse width settings to CDM stress parameters which can be used to evaluate CDM type failure modes [8, 9]. In this study, two CC-TLP setups were used for testing. The first tester used to perform testing at IFX, uses a circular ground disk with a diameter of 5 cm. The length of the probe tip is adjusted to 0.3 mm [10]. A TLP system with 1 ns pulse width and 100 ps risetime is connected as excitation source. The second CC-TLP tester, manufactured by and used to perform testing at ESDEMC, uses a test head with a square, rather than circular, ground plate the same size as a JS-002 CDM tester’s ground plate. The length of the probe tip is adjusted to 0.5 mm. The bandwidth of both CC-TLP measurement chains were limited by the pick-tee cutoff at approximately 10 GHz. Both testers integrate S-parameter compensation of the measurement chain in software. The same pulse parameters were used for both testers. A “dummy” device was used to determine the charging voltage necessary to achieve the desired peak current on each pin of each device tested.

III. Correlation Study

A. Device Information

Two different test devices are used for the correlation study of RP-CCDM, ACRP-CCDM, CC-TLP and CDM in terms of the failure level. Both devices are designed in 130 nm CMOS technology. Device A is packaged in a TSSOP, device B as eWLB. The expected failure mode is the excess of a critical potential level leading to gate oxide damage at one or more transistors. The failure mechanism of device A is a GOX failure triggered by a cross-domain issue and is located at an internal interface in the core. Device B shows several GOX failures and increased IDDQ currents after the damage occurring at the transistors on the edge of the digital core.

B. Transmission Line Connected Pins

As observed in measurements on the JS-002 verification modules, the peak current of the RP-CCDM and CDM testers was measured to be nearly identical on a reference connected pin of the device as seen in Figure 6. However, this relation was found to not hold across all pins on device B.

The most sensitive pins on device B are high-speed I/O pins connected to the die via impedance controlled, transmission line (TL), traces, such as shown in Figure 7.

In Figure 8 two curves of a TDR measurement in a CC-TLP setup are shown. The probe tip of the CC-TLP test head is connected to the chip, so that the current path to the die can be analyzed such as shown in [11]. Once the current wave reaches the die, the capacitance formed by the package and die to the ground disk of the test head is charged and marks the end of the transmission path. This method enables to measure delay times of single pins. In case of a pin with a corresponding ball in the direct vicinity of the die pad the delay due to the transmission path can be neglected (Fig. 8, green curve). For the second pin the connected transmission line forms a stable impedance for about 120 ps (Fig. 8, blue curve).

The stress observed on these pins is paramount to determining the stress that the device can withstand. However, due to the high variability of air discharge CDM testing, it can be difficult to evaluate the difference between testers on these pins after a typical CDM validation test with only three discharges per polarity.

C. Peak Current Comparison of Pin Types

To evaluate these pins more accurately, a 100-pulse test was performed by stressing a reference connected pin and a TL pin 100 times each. All testers were tested at a 500 V field charge voltage to prevent any spark differences that may occur if the JS-002 voltage factor method was incorporated. The pogo pins and dielectric surface were cleaned with isopropyl alcohol prior to testing and the testing was performed below 10% relative humidity to minimize peak variation due to the air spark. Due to the charge distribution over the whole chip and high current levels with ESD devices operating in the on-state, no difference is expected in the discharge waveforms from before failure to after failure of the device. An additional CDM tester head with a replaceable pogo pin was incorporated to evaluate the influence of various pogo lengths on the observed discharge peak. This new test head was used alongside the RP-CCDM and CDM heads used in all device testing. The CDM head used for device testing is indicated as “large diameter” since it has a diameter of 1.5 mm compared to the new test head’s 0.4 mm pogo diameter. Table 2 displays the maximum peak current measured within the 100-pulse test for each setup and the relative percentage of the TL pin peak current to the reference connected pin peak current.

As can be seen in Table 2, there is a correlation between the length of the pogo pin and the discharge current ratio between the TL connected pin and the GND pin. For a given pre-charge voltage (with voltage factors applied such that the RP-CCDM and CDM peak currents match on JS-002 verification modules) where a CDM stress induces 5 A peak current on the studied TL pin, the RP-CCDM stress will induce a 5.7 A peak current. This additional current can be clearly seen in the measured currents shown in Figure 9, which was taken during a qualification test of device B. The cause of the increased peak current of RPCCDM with respect to CDM for the same pre-charge voltage on TL pins can be explained by the input impedance of the CDM head. Figure 10 displays the input impedance of the CDM heads used in Table 2 as measured in [6], denoted as ZDUT. Due to higher input impedance in the 600 MHz to 2 GHz range, where the majority of the spectral content is contained (Fig. 5), a larger reflection back into the device trace will occur in the case of the RP-CCDM. As discussed in [12, 13], the stress the die experiences is a result of the reflected pulse off this discontinuity. As a result, the stress a TL connected I/O receives will be greater for a CDM head with a higher input impedance, given a matching peak amplitude on a calibration coin.

D. Simulation of Transmission Line Pins using ZDUT

To determine if the measured ZDUT values alone could predict the difference, a simulation using the measured ZDUT data was done in ADS by Keysight. A simplified circuit model, developed in [12], was adopted to represent a CDM event on a TL pin where the current must travel through the impedance-controlled trace and encounter an impedance discontinuity at the pin/pogo-pin interface.

As can be seen in Figure 13, the ADS simulation produces the same relationship in measured current as the measured data. The current measured using the measured RP-CCDM ZDUT to represent the test head structure results in a higher current measurement on the TL connected pin. Figure 14 shows the current measured on the die side of the transmission line and indicates an increased current peak with the RP-CCDM head. Further development with a less simplified model of the TL pin case is necessary to determine the precise stress difference that occurs due to this effect.

IV. Failure Analysis Results

A. Device A Failure Results

Device A was tested using RP-CCDM, CDM, and CC-TLP testers. To test if that the failure levels of device A are risetime dependent, CC-TLP tests were performed using 100 ps and 300 ps risetimes. The determined failure levels of the device A are shown in Table 3 and Table 4. The devices were stressed at increasing test conditions until failure. The recorded withstand current indicates the highest current that all tested devices were able to withstand. Failure analysis on device A was carried out via DC leakage testing.

Table 3 and Table 4 display the failure levels for the device A. The RP-CCDM and CDM were observed to correlate well on this device, inducing failures at TC750. Additionally, CC-TLP setups at ESDEMC and IFX both induced failure at 8 A. Figure 15 displays a comparison of each tester’s discharge waveforms recorded at the failure threshold of device A. As seen in Figure 16, a clear jump in the leakage current is evident for each device stressed at its failure threshold.

B. Device B Failure Results

Device B was tested with the RP-CCDM and ACRP-CCDM at test conditions of 400 V, 500 V, and 625 V. Additionally, tests with CC-TLP setups were performed at 4 A, 5 A, and 6 A with a 100 ps risetime and 6 A, 7 A, and 8 A with a 300 ps risetime.

Failure analysis on device B is carried out via DC leakage testing and verified via IDDQ testing. The failure is expected for pre-charging voltages higher than TC500 on CDM and located on the edge of the digital core. The IDDQ analysis measures the current consumption in the quiescent state on 200 vectors in the digital core.

The quiescent current into VDD for all vectors is below 100 uA in case of an unstressed reference device. Slight deviations in this range are traced back to normal variations. A significant increase of the current compared to the reference device indicates a gate-oxide failure on the edge of the digital core. Significant deviations between vectors in the IDDQ sweep are also an indication of failure on the edge of the digital core.

Table 5 and Table 6 display the failure levels for device B. Figure 17 – Figure 20 display the IDDQ readouts indicating the failure thresholds for each tester.

As shown in Table 5, the RP-CCDM induced failures below the TC500 withstand voltage of the device on a CDM tester. Figure 21 displays the measurement of the largest amplitude stress discharge for the CC-TLP, ACRP-CCDM, and RP-CCDM stress sets at 5 A, TC500, and TC500, respectively.

As shown in Figure 21, the ACRP-CCDM and RP-CCDM have similar pulse shapes and amplitudes on the sensitive I/O pin studied previously and produce failures at the same test condition. The RP-CCDM IDDQ sweep shows a more larger failure, which may be due to the more controlled spark environment and therefore slightly higher peak currents. Both the RP-CCDM and ACRP-CCDM testers produce increased amplitude pulses on TL pins when compared to the CDM tester due to the higher input impedance as discussed in detail in section III. The failure of both the ACRP-CCDM and RP-CCDM to correlate to the CDM at TC500 indicates that the geometry of the test head is likely responsible for the early failures on device B, rather than the spark event in the relay environment. The geometry contributes to a higher stress in the case of ACRP-CCDM and RP-CCDM due to the TL pin effect studied in section III.

As shown in Table 6, the peak current failure thresholds of both CC-TLP testers correlated well with each other by producing repeatable failures at 5 A peak current with a 100 ps risetime pulse and at 8 A with a 300 ps risetime pulse. It was observed during the correlation study that a failure at 5 A could not be reliably achieved until the risetime of the incident TLP pulse at the CC-TLP probe port was slightly decreased and approached 90 ps on the ESDEMC tester. This observation reasserts that the risetime of the stress is a critical stress parameter of device B and that the exact risetime of the incident TLP pulse is an important factor to consider when correlating CC-TLP systems.

V. Conclusions

In this study, the RP-CCDM test method was evaluated in comparison to the CDM and CC-TLP test methods using high bandwidth measurement and spectrum analysis, input impedance measurement and circuit modeling on TL pins, and device failure analysis on two devices.

It was shown that a longer pogo pin can induce a larger amplitude current discharge on a TL pin, given a matched peak current on a reference pin, due to the larger input impedance seen at the pogo-pin/device pin interface. This effect was replicated using a simplified model in ADS.

The RP-CCDM showed perfect correlation to CDM stress tests on one device, but consistently showed failures at a lower threshold on a second device. Although construction and excitation sources of both CC-TLP testers are different, they correlated well with the failures induced by the CDM and were helpful in indicating whether risetime was a critical stress parameter of the test devices.

The RP-CCDM was also used to perform air discharge tests, when the relay in the pogo-pin was closed during the entirely of the test and resulted in failure levels that matched RP-CCDM results. These results indicate that the RP-CCDM structure is likely responsible for the early failures on the second device due to the increased currents induced on TL pins. Analysis of the spectra between CDM (air spark) and RP-CCDM (relay spark) suggest that there is no significant increase in spectral content other than that caused by as more stable, low impedance spark. This observation suggests that the RP-CCDM may represent a “worst-case” air spark, that is the spark that would occur between two very clean surfaces at low relative humidity. More testing and statistical analysis of the RP-CCDM is necessary to make a conclusion about the “worst-case” analogy.

VI. Acknowledgments

The authors would like to thank Dr. Kai Esmark of Infineon Technologies AG for providing the testing devices, for his support regarding the failure analysis and for sharing his wide knowledge of ESD, and in particular, of CDM. The authors would also like to thank Michael Reardon of ESDEMC for his assistance and input during the CC-TLP testing portion of this study.

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PB2021.10 Analyzing the Influence of Imbalanced Two- or Three-Wire VHF LISN on Radiated Emissions from AC Cables

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Abstract—This article investigates using imbalanced two- and three-wire terminations for ac main cables, as suggested by the standard group. These terminations provide the basis for a new line impedance stabilization network (LISN) whose objective is to improve test repeatability between labs while also providing better estimation of real-world emissions. Standard balanced LISNs do not reproduce the imbalanced terminations seen in practice. An imbalanced two- or three-wire very high-frequency LISN was built, which can handle up to 15 A on each line. The LISN operates from 30 to 200 MHz and provides greater than 50-dB isolation between the input and output. The imbalanced termination allows the device to create a specified degree of conversion from differential-mode to common-mode current, which can increase radiated emissions. This conversion was evaluated to be as high as 12 dB in measurements of a power line communication device. 3-D full-wave simulations of two- and three-wire applications demonstrate that the radiated emissions from the prototype LISN and the ideal imbalanced termination are nearly equal. The new LISN was further evaluated to show promise for improving measurement reproducibility, reducing the standard compliance uncertainty by 6 dB in this study, from 15.5 dB in CISPR 16-4-1 to 9.5 dB with the LISN.

Index Terms—Common-mode impedance, radiated emissions, termination device, very high-frequency line impedance stabilization network (VHF LISN).

I. INTRODUCTION

Common mode conducted emissions are typically measured using a line impedance stabilization network (LISN) [1]–[9]. An LISN is a filtering device providing a) isolation of the device under test (DUT) from ac power lines and related radio frequency (RF) disturbances, b) a well-defined reference impedance at the LISN DUT port; and c) the necessary power to the DUT. Standard LISNs use a balanced termination structure [3]–[9]. Round-robin testing for radiated emissions show that the average emissions differ by 4 dB when using a traditional balanced LISN (see Fig. 1) [3], [4], but those deviations in measurements were as large as +18/−10 dB when the DUT was plugged directly into the building mains [3], [4]. Although a goal of the balanced very high-frequency (VHF) LISN is to reduce variations among tests [1]–[9], a balanced termination is rarely available in practice, so real-world emissions may be higher than seen in many standardized measurements.

The LISN forms an impedance between the wires of the power cable and the chamber ground and, thus, can be used as a common-mode absorption device above 30 MHz. If the common-mode impedance of the LISN is between 50 and 300 Ω, most of the common-mode resonances of the power cable will be suppressed. Suppressing these resonances reduces the dependence of the emissions on the power cable routing, the specific impedance of the chamber’s power connection, and the length of the power cord. While reducing this dependence is attractive for minimizing chamber to chamber variations, it also hides an important effect that causes radiation. In real installations, the differential-mode noise current is often larger than the common-mode noise current in a power cable, and real installations will have asymmetric common-mode impedances [10]–[12]. This asymmetry will convert differential-mode current into common-mode current, which can radiate. To mimic this effect, a defined asymmetry can be introduced into the VHF LISN.

Using an imbalanced termination will increase the common-mode emissions by about 10 to 15 dB up to 200 MHz (depending on the DUT) compared to using a balanced termination [11]. About 10-dB higher emissions were also reported for an imbalanced two-wire LISN compare to a balanced LISN over 0.5 to 30 MHz in [11]. To address the differential- to common-mode current conversion in a VHF LISN (30 to 200 MHz), the termination impedance should have a controlled imbalance to provide a defined degree of conversion from differential to common-mode current. The standard group introduced an imbalanced termination for this purpose and suggested that an LISN with similar performance should be created for the 30- to 200-MHz frequency range [10].

In this article, an imbalanced LISN with the characteristics suggested by the works in [10]–[12] was designed, built, and analyzed to serve as the termination of the mains power during radiated EMI CISPR16/CISPR 35 testing [1]. This LISN was designed in Section II to supply power for imbalanced two- or three-wire measurements up to 15 A over a frequency range from 30 to 200 MHz. In Section III, a 3-D full-wave simulation with both differential- and common-mode excitations representing the DUT was used to illustrate the effect of the VHF LISN on radiated emissions on a typical test setup for two- or three-wire application. A study of differential- to common-mode current conversion was performed to verify the conversion ratio for an ideal imbalanced termination. In a real test setup, the differential to common-mode current conversion is geometry dependent but not a fixed number. Measurements of a pair of power line communication devices were performed in Section IV to validate the performance of the LISN in a typical test setup and to demonstrate the level of differential- to common-mode current conversion for a real-word application. Discussions are presented in Section V. Finally, Section VI concludes this article.

II. DESIGN OF AN IMBALANCED TWO- OR THREE-WIRE LISN

The following section will introduce the imbalanced two-wire and three-wire terminations suggested by the working group and the literature [10]–[12], provide evidence of the suitability of the proposed impedances, show the characteristics of the actual LISN that was built to use these terminations, and give the value of differential- to common-mode conversion for a practical test setup connected to the imbalanced two wire termination.

A. Imbalanced Two- or Three-Wire Termination

The imbalanced two- and three-wire terminations proposed by the works in [10]–[12] are shown in Fig. 2(a) and (b), respectively. The termination characteristics for two-wire applications were specified as follows.

1) Common-mode impedance ZCM of 150 Ω ± 10% from 30 to 200 MHz, which defines the impedance between the line (L) and neutral (N) wires and the ground-plane, when the line and neutral wires are shorted together.

2) Differential-mode impedance ZDM of 100 Ω ± 10% from 30 to 200 MHz, which defines the impedance between the line and neutral wires when the neutral wire is shorted to the ground plane.

3) Impedance between the line and ground plane of 250 Ω ± 20% from 30 to 200 MHz.

The termination characteristics for three-wire applications were specified as follows.

1) Common-mode impedance ZCM of 90 Ω ± 10% from 30 to 200 MHz, which defines the impedance between the line, neutral, and protective earth (PE) wires (shorted together) and the ground plane.

2) Differential-mode impedance ZDM of 100 Ω ± 10% from 30 to 200 MHz, which defines the impedance between the line wire and the neutral and PE wires, when the neutral and PE are shorted to the ground plane.

3) Tertiary-mode impedance ZTM of 60 Ω ± 10% from 30 to 200 MHz, which defines the impedance between the line and neutral wires shorted together, and the PE wire and ground plane shorted together.

The working group [10]–[12] chose a 150-Ω two-wire common-mode impedance to suppress standing waves in the DUT power. The geometry of a power cable does not allow for easily assigning a common-mode impedance, as the wave structure deviates strongly from a TEM mode wave, but it has been shown that termination impedances in the range of 50 to 200 Ω suppress standing waves well [13]. Although not exact, using a common-mode impedance of about 150 Ω [see Fig. 2(a)] will provide results similar to those observed in [13] and minimal common-mode resonances will occur [13]–[15].

A 90-Ω termination was selected for the slightly thicker three-wire cables [10]. The 100-Ω differential impedance was chosen to mimic the impedance of a typical transmission line (TL) formed by the line and neutral wires [10]. To provide evidence for the validity of this selection, 48 different power cables were measured using a time-domain reflectometer (TDR) (see Fig. 3). Eleven were two wire cables, and 37 were three wire cables.

The impedance value was recorded between the short discontinuity at the beginning of the coax to cable transition and the end of the cable, which was left open. As shown in Fig. 3, a small adapter was made to connect the coax cable to the power cord, which causes a short discontinuity but does not affect the TDR measurement, as we record the differential impedance between the two lines after that discontinuity. The length of the cables is not important as we look at the differential-mode impedance provided by two wires (L and N).

The distribution of the characteristic impedances is shown in Fig. 4. The distribution shows the typical value of the differential impedance is close to 100 Ω, as suggested by the working group [10]–[12]. In the tertiary mode, the line and neutral wires are shorted and driven against the PE and ground (shorted). The line and neutral wires together as a larger “signal” conductor compared to the differential mode case, so the TL impedance is expected to be smaller. A value of ZTM = 60 Ω was chosen for this reason [10].

B. Prototype Imbalanced Two- or Three-Wire LISN

An imbalanced LISN was designed to meet the specifications of the working group. Additional requirements for the designed LISN are listed in Table I. Fig. 5 shows the LISN’s circuit diagram. The capacitor inductor networks in Fig. 5 (L1, C3, L4, and L2, C4, L5) were built to provide the required 50 dB of isolation of the DUT from the mains network at higher frequencies and provide a good connection to the building mains at 50 to 60 Hz. The capacitors C1 and C2 were made sufficiently small to isolate the line and neutral wires from each other and the PE at 50 to 60 Hz, but to allow resistors (R1, R2, and R3) to define the termination from 30 to 200 MHz. While the schematic in Fig. 5 should meet the specifications of the working group, validation is required since parasitics could alter the actual impedances looking into the LISN.

The six impedances specified by the working group could not be measured directly, since they require a floating measurement and different parasitics will be involved in each measurement. To determine the impedances, a combination of measurement and postsimulation was used. Three-port S-parameter measurements were made looking into each terminal of the LISN. A test fixture (see Fig. 6) was built to connect the LISN to the vector network analyzer for the three port S-parameter measurement. The measured S-parameter matrix was imported into advance design system (ADS) [16] to calculate the six specified impedances. The measured impedances and those suggested by the working group are shown in Figs. 7, 8, 9, and 10. The magnitudes of the measured impedances are all within the ranges proposed by the working group [10]–[12]. While the working group does not explicitly specify the phase, the measured phase is within about 30◦ of the ideal 0◦ phase for a resistive termination. More important than the variations in the actual impedance is its impact on the radiated fields. It will be shown in Section III that up to 30◦ variation in phase plus 10% variation in the magnitude of the LISN impedance will cause less than ± 3 dB variation in the radiated emissions, which is acceptable in EMC applications. These results suggest a ± 10% change in magnitude and ± 30◦ in phase is an appropriate limit for defining the impedance of an imbalanced VHF LISN.

C. Impact of Imbalance on Differential- to Common-Mode Conversion

An LISN is a filtering device providing the following:

1) isolation of the DUT from ac power lines and related RF disturbances;

2) a well-defined reference impedance at the LISN DUT port, which is isolated from the main network;

3) the necessary power supply to the DUT.

Looking from the DUT side, the common-mode impedance in the two-wire imbalanced LISN investigated is 150 Ω [see Fig. 2(a) and 13]. However, the common-mode impedance of a balanced LISN is about 50 Ω as seen from the DUT side. For both LISNs, the differential-mode impedance in the two-wire setup is 100 Ω [11], [12].

Testing without an imbalanced termination misses the important differential- to common-mode current conversion that may occur when the product is connected to a real ac mains network. The impact of the imbalanced LISN on differential to common-mode conversion was demonstrated using a 3-D full-wave model of a typical test setup. The model shown in Fig. 11 illustrates a typical radiation test setup [1]. The DUT is represented with a solid metal box (30 cm × 10 cm × 30 cm) located 1 m above an infinite ground plane. The box is connected to a 1.5 m power cable. The wires in the cable were driven with a 1-V differential source with zero-output impedance, as shown in Figs. 12 and 13. The sources were connected to the DUT chassis with a low impedance (10 Ω). This impedance is intended to represent a poor connection of a shield to the chassis. This connection was compared to a 1-Ω connection, which showed that this selection of the connection impedance does not significantly influence the conclusions drawn from the simulation.

A typical power cord geometry was used having a 1.62-mm wire diameter, a 0.89-mm-thick PVC insulation, and a PVC jacket with a diameter of 9.5 mm. The metal to metal distance between the wires was 2.35 mm. This distance forms a TL of about 80 Ω between the line (L) and neutral (N).

Circuit schematics of the full-wave structure with balanced and imbalanced terminations are shown in Figs. 12 and 13, respectively. The balanced or imbalanced terminations were chosen similar to those recommended for the LISN (see Fig. 2). The capacitance between the DUT enclosure and ground is about C ≈ 50 pF, depending on the size of the DUT. This capacitance creates an impedance of about 15 to 100 Ω from 30 to 200 MHz, which is on the order of the 150-Ω common-mode termination RCM, so that nonnegligible common-mode current could flow. Simple models without TLs and an estimated value of the coupling capacitance between the DUT and ground can be evaluated in [11]. Each wire is driven with an identical 0.5-V voltage source if opposite sign is creating a 1-V differential-mode source, which drives differential-mode current. As indicated in Fig. 12, there is no common-mode current when using a balanced termination, whereas the imbalanced termination will cause differential- to common-mode conversion of current (see Fig. 13), which will increase radiated emission. According to the works in [10]–[12], real installations have imbalances, which should be reproduced by the EMC test setup.

To calculate the amount of differential- to common-mode conversion, the full-wave model in Fig. 11 was simulated with an imbalanced two-wire termination (see Fig. 13) over a frequency range from 30 to 200 MHz, as shown in Fig. 14. The differential-mode current reduces with frequency since the 80-Ω TL is terminated into 100 Ω. Of course, for a different cable geometry, the differential-current (blue curve in Fig. 14) might be slightly different but that should not affect the current (< 10% variation) as long as the differential-mode impedance is between 80 to 100 Ω.

The common-mode current is affected by the structural length and fluctuates around 1 mA. The differential- to common-mode conversion can be measured by the ratio of the incident differential-mode power to the resulting power in the common mode as

The differential- to common-mode conversion ratio has been reported to be about −10 to −15 dB for an imbalanced CDNE-M [11]. The actual conversion ratio obtained through full-wave simulation, however, is somewhat geometry dependent and varies from −9 to −25 dB, as shown in Fig. 14. For a threewire application [see Fig. 2(b)], the maximum differential- to common-mode conversion was similarly evaluated to be about −19 dB. The conversion is smaller for three wires than two, because current will return not only via the ground plane, but also in the PE wire. The portion that returns in the PE wire does not contribute to the common-mode current.

III. RADIATED EMISSION USING THE IMBALANCED TWO- OR THREE-WIRE VHF LISN

To demonstrate the impact of the imbalanced LISN on radiated emissions, emissions were simulated using the fullwave model shown in Fig. 11. As shown in Section II-B, the impedances of the actual LISN vary about the ideal values due to unintended parasitics. Simulations were performed using the ideal LISN termination impedances and the realized values, as well as short and open terminations to show performance at the extremes. Table II summarizes all the settings used in the computer simulation technology (CST) Studio Suite. Simulation with the realized termination impedances was accomplished using the cosimulation feature of CST with the measured Sparameters. This feature combines the 3-D full-wave simulation with a circuit simulation or measurement [18] to simultaneously solve for the EM fields and the circuit characteristics. To ensure correct cosimulation, the following simulation procedure was used.

1) The setup shown in Fig. 11 was simulated with the ideal termination impedances represented as lumped elements [see Fig. 15(a)]. This simulation demonstrates the ideal performance of the imbalanced LISN and provides a reference for validation of the cosimulation approach.

2) A second simulation was performed using the ideal terminations with cosimulation [see Fig. 15(b)], where the excitation and the loads were replaced with S-parameter ports. Using the CST design studio cosimulation feature shown in Fig. 16, the excitation was connected to the source port and an S-parameter block representing the loads was connected to the load ports. An S-parameter block evaluated for ideal terminations [see Fig. 17(a)] was used to verify the procedure against the reference result from step 1.

3) After successful validation, the S-parameter matrix measured on the prototype was used to calculate the radiated emissions.

Radiated emissions were also evaluated for short and open terminations, when all the impedances on the termination side were replaced with open or short. The radiated emission was evaluated for all cases at a distance of 10 m. Results were evaluated for both common- and differential-mode excitations.

A. Common-Mode Excitation With Imbalanced VHF LISN

The schematic for the simulation setups with a common-mode excitation and ideal imbalanced two- and three-wire terminations are shown in Fig. 18. The maximum simulated far-field radiation for the three-wire setup with the studied terminations is shown in Fig. 19.

shown in Fig. 19. Strong resonances were observed for open and short terminations. The first peak is around 50 MHz, which is below the quarter wavelength frequency for a 1.5-m wire length, because the 50-pF capacitance between the DUT enclosure and the surroundings. At resonances, the radiation can exceed the radiation from the ideal termination by up to 15 dB. The 90-Ω commonmode termination impedance effectively damps resonances and in that regard seems reasonable with respect to repeatability. These results are in agreement with the previous study on the effect of common-mode impedance on radiation [2]. As shown in Fig. 19, the termination impedance is important at lower frequencies, but is not as significant at higher frequencies due to the increasing electrical length of the wire and the impact of damping due to radiation.

The black and blue curves in Fig. 19 show the results using the cosimulation technique and using standard simulations with ideal terminations. The two curves are nearly identical (< 1 dB difference). The green curve shows the radiated emissions using the measured termination S-parameters from the prototype. Comparing the blue and green curves, the radiated emissions from the real LISN is nearly equal to the radiation seen for the ideal termination case. Similar results were seen for the two-wire common-mode case [e.g., using terminations as in Fig. 18(a) and (b)]. The radiated emissions from the prototype LISN are close to the emissions from an “ideal” imbalanced LISN with less than 2-dB error up to 200 MHz (red curve in Fig. 19).

B. Differential-Mode Excitation With Imbalanced VHF LISN

Fig. 20 shows the differential-mode source excitation and the imbalanced termination in two- and three-wire setups. For both setups, the DM excitation was 1 V with 0-Ω output impedance. A low impedance (10 Ω) was selected to connect the wire to the DUT to represent a moderately poor connection to the enclosure. The radiated emissions from the two- and three-wire setups with differential-mode excitation are shown in Figs. 21 and 22, respectively.

When the ends of the wires on the termination side are open or shorted to the ground plane, the structures are symmetric. In this case, there is little common-mode current flowing in the circuit and very low radiation is observed. Large resonances are shown with open or short terminations because the source impedance is 0 Ω and there is little loss in the system. Resonances would be damped in this case with a larger source impedance. When using imbalanced terminations, there is noticeable differential to common-mode conversion for both the two- or three-wire case, which significantly increases the radiated emissions. As shown in Figs. 21 and 22, the results using cosimulation and using the standard EM simulation with ideal terminations are nearly identical. The difference between the radiation evaluated using the measured S-parameters from the prototype and using ideal terminations was less than a 3.2 dB up to 200 MHz (red curves in Figs. 21 and 22).

C. Tertiary-Mode Excitation With Imbalanced VHF LISN

balanced terminations for the three-wire setup. The excitation is 1 V with zero output impedance. The radiated emissions with a tertiary-mode excitation are shown in Fig. 24. When the wires are open or short, the structure creates a highly resonant system. In the presence of terminations, these resonances will be dampened, regardless of their source. The radiation of the prototype is very close to the radiation with an ideal termination, with less than 3-dB error up to 200 MHz (red curve in Fig. 24).

D. Impact of Termination Condition on Measurement Uncertainty of Imbalanced VHF LISN

The results of radiated emission measurements are affected by the uncertainties listed in [20] and [21]. This section investigates the impact and degree of influence of mains cable termination conditions on the standards compliance uncertainty (SCU) [20], [21]. The SCU is dependent on termination conditions over the frequency range where power cable radiation dominates [20]. Considering the tolerance of the termination impedance, the variation of the emission levels can be calculated, which also allows calculation of the measurement uncertainty influence [20].

The sensitivity of the radiation behavior of the LISN to deviations in the magnitude and phase of the terminating impedance from the ideal case should be analyzed to understand their impact on the SCU. Uncertainty is considered in the CISPR 16-4-1 standard [21]. Here, the average combined standard uncertainty (Uc-scu), including the terminating condition of the main cable, is defined to be

where CISPR/TR 16-4-1 specifies [19], [20] the following.

1) Uc,MIU, combined measurement instrumentation uncertainty, of 2.5 dB.

2) Ua, uncertainty from the main cable arrangement, of 3.5 dB. This value will depend on the termination conditions.

3) Uc, uncertainty in the operating condition of DUT, of 1.7 dB.

4) Ub, the uncertainty in termination conditions.

Assuming a rectangular probability distribution for the uncertainty of the cable terminating conditions, which is considered in CISPR 16-4-1 [21], the uncertainty in the terminating condition is given by [20]

where Emax and Emin are the maximum and minimum electric field strengths in dB µ V/m, respectively. If we consider the maximum deviation due to the termination condition of the prototype up to 200 MHz to be 3.5 dB (see Fig. 22 for a three-wire termination with DM excitation), the uncertainty in the terminating condition Ub is only 1 dB. Using (2), the average combined standard uncertainty (Uc-scu) is 4.7 dB. The expanded standard uncertainty Uscu, VHF-LISN is [20]

Compared to the 50-Ω LISN in [20] with an expanded standard uncertainty Uscu, VHF-LISN = 12˜dB, the expanded standard uncertainty of the imbalanced two- or three-wire VHF LISN has been improved by about 2.5 dB. Compared to the 15.5-dB uncertainty defined in CISPR 16-4-1 [21], the SCU for the imbalanced two- or three-wire VHF LISN is improved by about 6 dB. It should be noted that only a single device was studied here, and results may change with other devices.

IV. VALIDATION THROUGH MEASUREMENT

The effect of the differential- to common-mode conversion was investigated using a power line communication device. The goal was to investigate the impact of termination conditions on emissions with a DUT that uses a strong differential-mode signal to transmit data over power lines [11], [12]. The test used different termination conditions, a balanced LISN, an imbalanced LISN, and no LISN. A balanced LISN (see Fig. 1) was prototyped to compare with the imbalanced LISN. The balanced LISN had a 50-Ω impedance on each line with less than 1.5-Ω variations in magnitude and less than 5◦ variations in phase over the frequency range from 30 to 200 MHz.

A block diagram of the measurement setup inside the semianechoic chamber is shown in Fig. 25. The two DUTs are HD power line adaptors (PLA5456), which communicate with each other through power lines. The measurement setup is shown in Fig. 26. The DUTs and LISN are mounted on the floor such that the power cable produces a loop with the maximum radiated emissions toward the antenna. A personal computer (PC) was needed to communicate with the DUT. To generate the highest differential-mode current, the DUT was operated under its maximum data rate. The measurement was performed for both horizontal and vertical polarizations and with 1- to 4-m scan heights of the antenna. The table was also partially rotated to capture the maximum radiation.

The goal was to show the differential- to common-mode conversion by using an imbalanced LISN, but also to show the impact of connecting the LISN to different power nets, as well as to show the impact of the power nets on emissions when no LISN was used. Connecting the LISN to different power nets helps to show if it has reproducibility issues. Different power networks were created by adding a soldering iron, a linear dc power supply, different wires with terminations, such as 2 nF, power cords, and strip lines, to the outlet inside the chamber.

Changing the power net before the LISN should have no effect, as the LISN isolates well. With different termination impedances, however, the radiation should change noticeably if no LISN is used. While different emissions are expected from a balanced or imbalanced LISN, both are expected to generate somewhat stable curves because both LISNs isolate the DUT from the power net. Higher radiation is expected using an imbalanced LISN rather than by using a balanced LISN, since the imbalanced LISN converts differential-mode current into common-mode current. Radiation results for all power networks and using three different termination conditions (balanced LISN, imbalanced LISN, and no LISN) are shown in Fig. 27. When both power line communication devices are ON, the broadband signal below 80 MHz is representative of the data transfer from the DUT. The DUT has no differential-mode energy above 80 MHz. Some observations are (a) when not using an LISN, the radiated emissions vary by up to 12 dB, since the termination is not controlled. (b) with a balanced or an imbalanced LISN, radiation has less than 3-dB variation, because the LISNs isolate the network and provide a well-defined termination. (c) the conversion with the imbalanced LISN is as high as 12 dB. (d) the imbalanced LISN generates emissions that are close to the worst of the measured emissions when connecting directly to the power networks, and (e) both LISNs have no reproducibility issues.

Neither impedance, nor conversion, has been characterized for the chamber used for measurement. Therefore, the observed variation in radiated emission is expected to be large ΔE > 10 dB. However, both balanced and imbalanced LISNs have controlled terminations and will not cause reproducibility problems because the data have less than 3-dB variation for different power networks. In general, the data show that for a device that has a strong differential-mode current, the imbalanced LISN brings the emissions to a more realistic level. The result from the balanced LISN ignores the differential- to common-mode conversion and gives unrealistically lower emission.

The conversion of course should correlate to the currents on the wires. The common-mode and differential-mode currents have been measured with a F65 current clamp at a few points along the cables. The maximum current has been captured and the conversion was calculated as the difference between the maximum common-mode current when the cable was terminated with balanced and imbalanced LISNs.

Similarly, the radiated emission conversion was calculated as the difference between the maximum radiated emission when the cable was terminated with balanced and imbalanced LISNs. Fig. 28 shows differential-mode to common-mode conversion, which is calculated from both current (blue curve) and radiated emission (red curve) measurement using balanced and imbalanced LISN. As shown in Fig. 28, the conversion calculated from radiated emission and the common-mode current are quite similar, i.e., this plot validates the conversion ratio with two different quantities, e.g., current, and radiated emissions. Above 80 MHz, the observed differences between the common-mode current for both balanced and imbalanced LISNs are almost zero because the DUT has no transmit energy. At the lower frequency band, the conversion is as high as 12 dB for both radiated emission and common-mode current.

V. DISCUSSION

Imbalanced LISNs can be designed for different target impedances. The LISN analyzed in this article was designed for a 150-Ω common-mode impedance, as suggested in the literature [10]–[12]. This impedance can strongly attenuate cable resonances [13]. Since actual power networks show strong resonances, one would underestimate the actual radiation at these frequencies. An alternative would be to design the LISN for a 25-Ω common-mode impedance. While this smaller impedance would strongly increase the radiation at resonances, there is no certainty that the resonances would occur at the same frequencies in the real installation since the actual power line impedances are unknown. A far-reaching design of an LISN might allow one to adjust the common-mode impedance along the Smith chart to identify the worst-case common-mode impedance for a given DUT. The impact of common-mode impedance on the radiation at resonances should be investigated in future.

Alternatively, it may be worthwhile to further study the PE line impedance in a variety of application areas, for example, in an urban area or in light industry area, and then adjust the LISN impedance according to the application.

VI. CONCLUSION

An analysis of an imbalanced two- or three-wire VHF LISN was conducted in terms of its mode conversion and termination impedance. It was demonstrated that an imbalanced termination impedance provides a specified degree of conversion from differential to common mode, which can lead to more representative radiated emission test results. To ensure spectral emission control, an imbalanced LISN is needed. An imbalanced two- or three-wire VHF LISN was prototyped. The impedances in the prototype had less than 10% error in magnitude and 30◦ in phase compared to the impedances for an ideal imbalanced LISN, as specified by the working group. A 3-D full-wave simulation was performed to investigate the maximum radiation of a twoor three-wire setups using an imbalanced termination. It was demonstrated that the performance of the prototype leads to less than 3.5-dB error as compared to an ideal imbalanced LISN. In EMC applications, this error threshold is acceptable. It is therefore suggested that the impedance of an imbalanced VHF LISN vary by less than ± 30◦ in phase and ± 10%. For the main cable termination, the standard compliance uncertainty has been considered in CISPR 16-4-1 to be 15.5 dB. This uncertainty has been improved to about 9.5 dB for the proposed prototype. The differential- to common-mode conversion for an imbalanced termination was measured with two power line communication device to be as high as 12 dB considering both current and radiated emissions. Using different power nets inside an anechoic chamber, it was demonstrated that the chamber-tochamber reproducibility will be much better if an imbalanced LISN is used in every chamber.

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PB2021.10 1 Ω Disk Resistor Full-Wave Modeling for JS-002 Standard

Download PDF – 1 Ω Disk Resistor Full-Wave Modeling for JS-002 Standard

Abstract –A 1 Ω disk resistor is specified in the CDM standard as the current sensing element. However, its transfer impedance is frequency dependent which is not considered in the standard. In this work, a full-wave model and a simple equivalent circuit model is provided to explain the root cause of the variation the transfer impedance of the 1 Ω disk resistor.

I. Introduction

When the pin or pad of a charged IC approaches an external metal object, and the breakdown voltage is exceeded a Charged Device Model (CDM) event occurs. During CDM testing, the discharge current of the CDM event is measured by a 1 Ω disk resistor sensing element that is located at the top of a pogo pin probe as described in the industry standard ANSI/ESDA/JEDEC JS-002 [1]-[3]. The resistance of this element is specified to have a value of 1.0 Ω ± 10% and a transfer impedance that does not have a deviation relative to the DC value greater than 3 dB up to 9 GHz [3]. The standard does not consider frequency variations of the transfer impedance when calculating the current from the measured voltage. This work investigates this assumption by characterizing the sensing element (1 Ω disk resistor) of a field induced CDM tester in the frequency domain. Additionally, a simple circuit model and a full-wave model are presented to explain the variation of the transfer impedance up to 27 GHz.

II. CDM tester

A. Discharge Circuit

The cross section of a CDM tester [3] is shown in Figure 1.

To charge the device, the field plate is brought to the specified charge voltage, then the pogo pin is lowered to contact the DUT pin. A spark is initiated and the current flows via the pogo pin to the 1 Ω disk resistor (Figure 2). The transfer impedance, properties of the oscilloscope and cable losses will determine the voltage that is displayed at the scope. The voltage is measured across the 1 Ω disk resistor from which the discharge current waveform is then calculated. However, the transfer impedance of the 1 Ω disk resistor is not constant over the frequency range and deviates from the DC value of the 1 Ω resistor [5].

B. 1 Ω Disk Resistor Measurement

As shown in Figure 2, the disk resistor consists of a resistive sheet on one side and a ceramic substrate made from beryllium oxide (BeO) on the other side that provides mechanical strength. In a CDM test head, the resistive sheet can be mounted downward (Figure 3a, resistive sheet towards pogo tip) or upward (Figure 3b, resistive sheet towards coaxial line).

Figure 4a shows a fixture to measure the disk resistor. The fixture is composed of two 50 Ω surface mountable connectors and a plate that aligns the disk resistor. The thickness of the plate was chosen to prevent any gap between the 50 Ω connectors and the surface of the disk resistor. The surface mount connectors were connected to ports 1 and 2 of a VNA and port extensions were performed up to the connector surfaces (Figure 4a). Figure 4b shows the definition of current and voltage of the two-port measurement setup (disk resistor setup measured with VNA). Knowing the S-parameter across the disk resistor, the transfer impedance of the disk can be calculated as in [6]:

As shown in Figure 5, the S21 and S12 of the disk are nearly identical which gives evidence for the accuracy of the measurement. However, the S22 and S11 are different (Figure 6). Port 1 of the measurement fixture (Figure 4) is toward the resistive sheet of the disk resistor, and port 2 is connected to the ceramic side of the disk. The reflection coefficient S11 is nearly flat but S22 has lower value at higher frequencies. The difference between S11 and S22 is important in understanding the CDM system behavior at high frequencies. Ringing was observed in the time domain discharge waveform if the substrate is mounted toward the pogo-pin but it reduced if the disk was flipped. The ringing will be discussed in Section IV of this paper. At low frequencies, the transfer impedance equals the disk resistance. Thus, the impedance measured with VNA should match the measurements obtained by an LCR meter (1 Ω @ 1kHz).

As shown in Table I, both LCR Meter (@ 1kHz) and disk measurements (Figure 4) show about 1 Ω for different orientations of disk (up to 1GHz). For each sample, both methods showed nearly identical low frequency values (Figure 7). At higher frequencies, the transfer impedance obtained using (1) is increasing with frequency (Figure 8) for all disks. Additionally, manufacturing tolerances lead to variations between disk samples. The behavior of the S21 can be explained using a simple circuit model in the next section.

III. Device Modeling

A. Simple Circuit Model

Although different disk resistors showed slightly different transfer impedance values versus frequency, they all behave similar (Figure 8). The transfer impedance of the disks increased with frequency from 1 Ω @ 1 MHz to about 3 Ω @ 20 GHz. This behavior can be explained by the influence of the ceramic substrate. It forms a short, 13 ps delay transmission line (see Figure 2) which acts as transmission line transformer and changes the match of the 1 Ω disk side to the 50 Ω system. The substrate has a relative permittivity of around 7. However, the structure is not easy to model in 3D due to possibility of higher order modes if they are excited. Only considering TEM modes, a simple circuit model is created in Advanced Design System (ADS) [7] to evaluate the influence of the short ceramic transmission line (Figure 9).

Based on the geometry and permittivity of the Beryllium Oxide (BeO) substrate, the characteristic impedance of the ceramic portion was calculated to be roughly 17 Ω. A 13 ps long 17 Ω lambda/4 transmission line transformer converts 50 Ω to transfer impedance of about 3 Ω at 20 GHz which can be calculated with (1).

This transmission line behavior explains the observed increase of S21 and transfer impedance. As shown in Figure 10, S11 is almost flat over the entire frequency range whereas S22 decreases with frequency as the short transmission line changes the match to 50 Ω. A comparison between measured impedance and calculated from the simple circuit model will be discussed in the next section.

B. Full-wave Model

The simple circuit model gives a qualitative insight into only the dominating effects, excluding the influence of the skin effect, higher order modes, and details of the geometry. A full-wave model can reveal additional details about the frequency-dependent impedance. Figure 11 shows the core elements of the full-wave model: the 50 Ω connectors, the geometry of the disk resistor, and two waveguide ports which are placed across the 50 Ω connectors. Two short 50 Ω connectors are placed on both sides of the disk. As shown in Figure 2, the 1 Ω disk resistor has a resistive sheet on one side and a ceramic carrier made of beryllium oxide on the other side. A thin resistive sheet material (this does not model skin effect) and BeO were imported from the library of CST Studio Suite [8].

C. Comparison Between Measurement and Simulation

Figure 12 and Figure 13 compares the magnitude and phase variation data for the measured, circuit model, and full-wave model of the 1 Ω disk resistor. Both models and the data agree on the increase of the impedance above 1 GHz and the peak around 20 GHz. This increase and the peaking may cause some error in the peak current measurement for CDM if the actual current contains relevant spectral content in this frequency range.

The fact that the simple circuit model and the measured data match up to 20 GHz can be seen as indicator that the short transmission line is the dominating reason for the observed increase in transfer impedance and the behavior of S11 and S22. The full-wave model predicted a higher peak value, 3.3 Ω relative to 2.6 Ω in the measurements (Figure 12 for resistive sheet down). The reason is not known, but as the frequency matches the other data one can be assured that the dielectric constant of the BeO was correctly estimated from literature data. The full-wave simulation shows additional resonant behavior around 25 GHz which is also seen in the measurements in the same frequency range. We have not investigated the field distribution at these frequencies within the full-wave results to identify the nature of these resonances. Furthermore, the transfer impedance of the disk may decrease at higher frequencies when skin effect starts to decouple the front and the back side of the very thin resistive sheet. As the authors do not know the exact thickness and material of the resistive layer, it is not known above which frequency the decoupling effect of the skin effect would reduce S21. The data indicates that this is not the case below 20 GHz, as the simple ADS model matches the measurement in its principle behavior. Our full-wave model is also not able to simulate skin effect as an infinitely thin electrical layer was used to model the resistive sheet. The metallization of the resistive layer may not be fully homogeneous. This would cause a current flow that is not radially symmetric. As known from current shunts, this would increase the mutual inductance between both sides of the resistive disk. Such a behavior is not observed which leads to a tentative conclusion that the resistive sheet is homogeneous within the boundaries of the analysis.

IV. Effect of Disk Orientation on CDM Event

To investigate the effect of disk orientation, both measured and simulated results have been compared in a CDM test setup.

A. Effect of Disk Orientation on Measured Discharge Current

CDM classification levels have been reduced [9] and that further reductions are to be expected. This will lead to a faster rise time in CDM. This, paired with faster I/O on ICs may lead to measurement problems in CDM testing due to the mounting direction of the disk resistor. To investigate the effect of disk orientation, CDM discharge tests have been measured using a 23 GHz bandwidth oscilloscope [10] with different orientations of disk resistor as shown in Figure 3. One disk resistor was used within one test head by flipping the orientation between tests to prevent any unwanted effects or variation in the test setup. Discharge data from multiple pogo-pins with different length and discharge currents have been captured for charge voltage of 500 V (Figure 14 through Figure 17).

As shown, all plots have a low frequency component around 1 GHz which is the main CDM discharge current. However, there are some high frequency components as well which create ringing waveform over the low frequency waveform. As shown, high frequency ringing was observed in discharge current when the resistive sheet of disk resistor was mounted upward (Figure 3b).

However, the ringing is weaker if the resistive sheet of disk resistor is mounted downward (substrate toward oscilloscope and the resistive sheet toward DUT as shown in Figure 3a). To isolate the ringing from the familiar low frequency response, a Maximum Overlap Discrete Wavelet Transform based Multiresolution Analysis (MODWT MRA) was used [11]. This method yields excellent decomposition and reconstruction while maintaining sharp edge definition and minimizing non-causality introduced by traditional high pass filtering. The high frequency ringing signal was found to be well isolated from the rest of the signal by using the db7 wavelet with a scaling factor of 2. Furthermore, the Wigner-Ville distribution [12] of ringing is used to visualize the time dependent frequency composition of the time dependent current.

The time domain signal, the power spectral density and time-frequency scalogram of ringing for different pogo-pins and for resistive sheet up and down is shown in Figure 18 and Figure 19. As indicated in timefrequency spectra of Figure 18, when the disk resistor is mounted upward for pogo pin length of 8.25 mm, 9.4 mm and 10.5 mm, there are two main high frequency component which make up the ringing with the corresponding interference term between the two main components.

However, in all time-frequency spectra of Figure 19, there is only one frequency component. Similarly, when the resistive sheet of disk resistor is mounted upward the power spectrum has two main frequency components for pogo pin length of 8.25 mm, 9.4 mm and 10.5 mm. Table II summarizes the two observed frequencies if the resistive sheet of disk is mounted upward (Figure 18).

Two sinusoidal signals are used in Figure 20 to reconstruct the ringing for pogo pin of 10.5 mm (blue curve in Figure 20) and is compared with the original ringing (red curve in Figure 20).

Therefore, it is possible to reconstruct the ringing by summing two sinusoidal signals e.g., f1 and f2 as shown in Figure 20. This motivates us to consider the nature of ringing and determine the physical agents which correspond to these responses.

Figure 21 shows the half wavelength versus frequency (blue curve) and is compared with the length of the pogo pins versus the first sinusoidal signal (f1) from Table II (black curve). As shown, the first sinusoidal signal (f1) is directly related to the length of pogo pin and can be calculated relative to the length of the pogo pin. The second sinusoidal component is related to the disk orientation. As shown in Figure 18 and 19, the second sinusoidal signal (f2) exist for resistive sheet upward for pogo pin 8.25 mm, 9.4 mm and 10.5 mm. However, this signal disappears when the resistive sheet is mounted downward. For the pogo pin 6.6 mm, two sinusoidal signals cannot be distinguished since f1 is very close to f2. When the resistive sheet of disk resistor in mounted downward (resistive sheet toward DUT), only one frequency can be observed in time-frequency spectrum of ringing signal (Figure 19) which indicate the effect of disk orientation.

B. Effect of Disk Orientation in Simulation

As shown in Figure 18 through Figure 20, two sinusoidal signals contribute to the high-frequency ringing of the CDM discharge current. A full-wave model is created for CDM test setup (Figure 22) to obtain a qualitative insight into the dominating effects up to 30 GHz. Two discrete ports are placed on both sides of the pogo pin providing the corresponding connection for co-simulation simulation in ADS which is shown in Figure 23. Measured S-parameters of the 1 Ω disk resistor from Section II or simulated S-parameter file from Section III can be imported into ADS model of Figure 23. It is also possible to use the simple circuit model of the disk resistor (Figure 9) into the circuit model of Figure 23. As shown in Figure 24 and Figure 25, if the orientation of the disk is changed, the high frequency ringing also changes. The first ringing in the discharge current relates to the length of the pogo pin which exists in the discharge current regardless of disk orientation. However, the second ringing corresponds to the disk orientation and will disappear if the resistive sheet of the disk is mounted toward the DUT (red curve of Figure 24 and Figure 25). If the substrate of the disk is mounted toward the DUT (blue curve in Figure 24 and Figure 25), the waveform has more ringing (high frequency contents).

The effect of disk orientation in simulated data (Figure 24 and Figure 25) is not as strong as the measured waveform (Figure 14 through Figure 17), but in principle they follow the same behavior, i.e., ringing is stronger if the ceramic substrate is mounted toward the DUT and gets weak if the resistive sheet is mounted toward the DUT.

It is known that the current measured at disk is not necessarily equal to the current at the DUT [13]. Ultimately, the current at the DUT is the stress that the device experienced. For accurate comparison between measured and simulated data in this paper, only current at the disk resistor was studied. Future work should incorporate current at the DUT to get a more accurate measurement of the stress that the device experiences.

A. Discussion

The fundamental question is how important is the frequency response of the transfer impedance of the disk resistor above 10 GHz?

Present ICs have data rates up to 50 GHz and more. Thus, their I/O can be damaged by high frequency content of every strong signal [14]. The charge voltages of CDM will be further reduced such that the rise times will further reduce [9]. Thus, the importance of the larger than 10 GHz spectral content will increase. Right now, CC-TLP testers can be based on a 40 ps or less transmission line pulser [14]. A 30 ps rise time equates to 10 GHz. To avoid problems in testing of future ICs and for comparing test methods, the analysis > 10 GHz is suggested.

V. Conclusion and Further Investigations

The frequency response of the transfer impedance of a 1 Ω disk resistor has been investigated through measurement, full-wave modeling, and a simplified equivalent circuit. The transfer impedance increases with frequency and shows a maximum of about 3 Ω at 20 GHz for disks mounted downward (resistive sheet toward DUT). However, the transfer impedance increases with frequency and shows a maximum of about 15-20 Ω around 20 GHz for a disk mounted upward (resistive sheet toward oscilloscope).

This is explained by considering the inner structure of the 1 Ω disk resistor. Only one side of the resistor’s ceramic carrier contains the resistive sheet material. Thus, it is asymmetric. The thin ceramic carrier creates a short transmission line. The effect of this short transmission line section is clearly visible in measurement, simplified and full-wave simulation both in S11, S22 and S21 data. It cannot match the 1 Ω but it strongly changes the match and causes an increase of the transfer impedance. The CDM current has been captured with different pogo pin lengths. High frequency ringing was observed. It can be explained as the sum of two sinusoids. The first sinusoidal signal was directly related to the resonance frequency of the pogo pin structure, i.e., its length and the second one was created due to the transfer impedance of the disk orientation.

VI. Acknowledgements

We would like to thank Dr. David Johnnsson and Dr. Timothy Maloney for their useful discussions and comments.

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PB2021.02 An Analytical Method to Evaluate the Spectrum of Multicarrier Multipactor Discharge

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 Abstract—Radio frequency (RF) noise can severely degrade the performance of electronic circuits and wireless systems. This article proposes an analytical method to evaluate the spectrum of RF noise caused by multicarrier multipactordischarge.First, a simplified model is developed to analyze the electric current characteristics of the resonant multicarrier multipactor discharge. Then, an analytical formula for the spectrum of the resonant multicarrier multipactor discharge is derived. Finally, the theoretical method is evaluated for dual-carrier operation inside a silver plated rectangular waveguide. Simulation results coincided well with theoretical findings show that the proposed method is encouraging.

Index Terms—Multicarrier, multipactor discharge, parallel plate model, rectangular waveguide, RF noise

I. INTRODUCTION

Multipactor is a nonlinear phenomenon which is caused by the interaction between the charged particles and the applied RF fields [1], [2]. Multipactors are generally classified into two types on the basis of the carriers of the applied RF fields, namely, single-carrier and multicarrier multipactor discharge. The main effort of this work is focused on the multicarrier mutipactor cases; the theoretical analysis and the resulting equations developed in this article are valid only for monoenergetic secondary emission.

As is well known, when there is an electric field between two small parallel plates, the initial electrons of the parallel plate region will be accelerated by the electric field and then impact against the surface of the plate. One or more electrons are released after impact. If some of the electrons synchronize with the electric field, such process as aforementioned is repeated until a steady state is reached (the growth of multipactor electrons ceases to continue) [3]. Multipactor discharge causes a number of negative influences such as the RF noise, passive intermodulation, impedance mismatch, and signal distortion, which can severely degrade the performance of microwave circuits [4]–[6].

In the past decades, various models and analytical methods were proposed to suppress or predict multicarrier multipactor breakdown in microwave devices [7]–[11]. For example, in [7], a new quasi-stationary (QS) prediction method for multipactor breakdown determination in multicarrier signals has been presented; the experimental results show that the QS prediction method offers better predictions than that the popular 20-gap-crossing rule. In [8], the performance of the most popular multipactor breakdown prediction method, i.e., the 20-gap-crossing rule, for multicarrier signals, has been checked by experiments. In [9], the Monte Carlo method has been proposed to find the thresholds and the global “worst case” waveforms of both single-event and long-term multipactors. However, in practical situations, it is almost impossible to completely suppress multipactor discharge for all cases. Therefore, it is necessary to understand the spectrum characteristics of multipactor discharge, as it is useful for designing the noise compression components and filters to eliminate the RF noise generated by multipactor discharge.

The spectrum characteristics of the single-carrier multipactor discharge have been well investigated by some works [12]–[15]. For example, Sorolla et al. [12] presented a model to evaluate the power spectrum of a single-carrier multipactor discharge. Semenov et al. [13] analyzed the amplitude spectrum of the multipacting electrons in rectangular waveguide with single carrier signal. Jimenez et al. [14] measured the power spectrum of the multipactor event excited in a single-carrier microwave circuit based on rectangular waveguides. However, a specific theory, which is used to analyze the spectrum characteristics of multicarrier multipactor discharge, attracts little attentions to the best of the authors’ knowledge [15].

In this article, a theoretical analysis method is presented to analyze the spectrum characteristics of the multicarrier multipactor discharge. It should be noted that the multipactor electrons are considered to resonate with the fundamental RF carrier. This article is organized as follows: Section II analyzes the frequency characteristics of the multicarrier RF field briefly; it will be used to find the period, harmonics, and subharmonics of the resonant multicarrier multipactor discharge in later Sections. In Section III, a simplified model of the multipactor electrons is stated first, and then a numerical expression for evaluating the spectrum of multicarrier multipactor discharge is derived. In Section IV, simulations are conducted to demonstrate the effectiveness of the proposed theories. Section V draws a conclusion of this article.

II. FREQUENCY OF MULTICARRIER RF FIELD

In this section, the frequency characteristics of multicarrier signals are proposed. A multicarrier signal u(t) (RF field) is composed of k carriers with frequencies ωi , angular phases ϕi , and amplitudes Ui , mathematically

where ωi = 2π fi , i are integers, and I = 1, 2…k. Furthermore, as detailed in [16], if fi are integers, the frequency f of the multicarrier signal u(t) is the greatest common divisor of the set carrier frequencies fi , mathematically

In practical microwave circuits, the precision of fi is usually limited to decimals; thus, the integer frequencies can be obtained by normalizing fi . For example, when f1 is equal to 2.33 GHz, the normalized integer frequency of f1 will be written as 2330 MHz.

Three cases (A, B, and C), when ϕi = 0, Ui = 1, and the carrier numbers are 2, 2, and 3, are shown in Table I to explain the analytical results in (2). As illustrate in Table I, the frequencies of cases A, B, and C are 0.5, 0.6, and 0.05 GHz, respectively. These demonstrated results will be used to analyze the period, harmonics, and subharmonics of the multicarrier multipactor discharge.

III. NUMERICAL ANALYSIS METHOD

In this section, the analytic model and mathematical expression are developed to analyze the spectrum characteristics of the resonant multicarrier multipactor discharge.

A. Analytical Model

As shown in Fig. 1, a parallel plate model is adopted to investigate the spectrum characteristics of the resonant multicarrier multipactor discharge. The length, height, and width for the parallel plate model are defined as d, h, and w, respectively. As shown in Fig. 1(a), the electrons resonate with the applied electric field and grow exponentially. The parallel plate model will be filled with the resonant electrons after a few nanoseconds, and the current of those resonant electrons is directly related to the multipactor noise [12]. Therefore, the cruces of eliminating the multipactor noise are the analysis on the spectrum characteristics of the resonant electron current.

B. Mathematical Expressions of the Spectrum Characteristic

As shown in Fig. 1(b), we assume that all resonant electrons are localized in a thin sheet L, and L is located at zL . Here, the bottom and top plates of parallel plate model are located at z = 0 and z = h, respectively. The distance between the thin sheet L and the bottom plate is |zL |. Because the resonant electrons are driven by the RF field u(t), the motion of the thin sheet L is repeated with the period of the RF field u(t). Furthermore, the direction of this thin sheet L orients only in the z-axis, when d L and w L are assumed; the theoretical model of this article is developed in Fig. 1(c). Therefore, the current density of the thin sheet L can be calculated as [13]

where v(t) is the instantaneous velocity of the thin sheet L, in the units of meter per second (m·s−1);


z is the motion direction of the thin sheet L (does not carry units); ρ is the volume charge density, measured in coulombs per cubic meter (C·m−3), and ρ can be further measured with putting a positive probe in the multipacting components [14]. Since the thin sheet L is directly derived by the RF field u(t), according to the Newton–Lorentz force law, the relationship between the instantaneous velocity v(t) and the RF field u(t) can be written as

where m and e are the electronic mass and the electronic charge, respectively. As Ui = U0 and ϕi = 0 are first assumed in (1), and then integrating (4), the instantaneous velocity v(t) can be expressed as

where t0 and v0 are the initial time and the initial velocity of the thin sheet L, respectively, and v(t0) = v0. T is the period of the RF field u(t). N is the multipactor discharge resonance order, and N = 1, 3, 5, 7, … odd.

Equation (5) consists of two parts, which are the oscillation velocity vosc(t) and the constant velocity vcon(t). As shown in (6), vosc(t) changes continuously with time t and thus contributes only to the basic carrier frequencies of the current density J [14]. vcon(t) represents an antisymmetric square-wave function with period NT, which changes in a step-like way after each impact against the surface of the parallel plate; the instantaneous jump of vcon(t) will lead to distortion of the carrier signals. Therefore, the harmonics and subharmonics of the current density J are completely determined by vcon(t).

As also shown in (6), vcon(t) is an antisymmetric step function with the period of NT. Therefore, vcon(t) can be expanded by Fourier series; the Fourier series is an expansion of a periodic function in terms of an infinite sum of harmonically related sinusoids [17]. Specially, the Fourier series of vcon(t) can be rewritten as

Furthermore, the Fourier coefficients a0, an, and bn of vcon(t) can be calculated as

Substituting (8) into (7), vcon_FS(t) can be rewritten as

where n is the orders of harmonics and subharmonics, and s belongs to positive integers. Since vcon_FS(t) is an expansion of vcon(t), vcon_FS(t) is equal to vcon(t), then v(t) = vosc(t) + vcon_FS(t).

When taking both vcon(t) and vosc(t) into considerations and ignoring the motion direction


z, the current density J can be rewritten as

Equation (10) shows an analytical expression to evaluate the spectrum of the current density of multicarrier multipactor discharge. The following conclusions can be drawn from (10): 1) in the first-order multipacting resonance N = 1, the odd harmonics ( f , 3 f , 5 f,…, and f = 1/T ) of the RF field u(t) are generated. For example, the harmonics are determined by the last term in (10) and expressed in
∞ n=2s−1 sin[2πn/T (t − t0)], where s belongs to positive integers, and n = 2s − 1; therefore, the harmonic components are 1/T , 3/T , 5/T,··· , n/T (i.e., f , 3 f , 5 f , ··· , nf, f = 1/T ). 2) in the higher order multipacting resonance N ≥ 3, the subharmonics are generated and can be described by 2πnf/N. It means that the frequencies of the subharmonics are directly related to the order of multipacting resonance N and the frequency f of the RF field u(t). 3) the magnitude of the multicarrier multipactor noise, including harmonics and subharmonics, decreases with the order n. For example, in (10), the amplitudes of harmonics and subharmonics are expressed in
∞ n=2s−1[v0 − (U0e)/(hmωi)
k i=1 sin(ωi t0)]4/(nπ ), and thus for a particular case of multicarrier multipactor discharge (i.e., the coefficients of v0, U0, k, h, and ωi are fixed), the amplitudes are only affected by n and decrease with it.

Two cases, which are used to further illustrate the frequency components calculated by (10), are shown in Fig. 2. The data employed to analyze the frequency components in the above two cases are set as follows: k = 2, t0 = 0, U0 = 30 V, v0 = 6.68 eV. Form the example, we see that the third, fifth, harmonics (3 f , 5 f ) and the seventh, eleventh, thirteenth subharmonics (7 f /3, 11 f /3, and 13 f /3) are very close to carrier frequencies and need to be addressed carefully.

IV. SIMULATIONS

In this section, a dual-carrier multipactor discharge, which occurs in a rectangular waveguide, is designed to demonstrate the proposed theories in Section III. The length and width of the rectangular waveguide are 10 and 8 mm, respectively. The height of the waveguide covers two different sizes, 0.6 and 2.4 mm, in order to provide the multipactor orders of 1 and 3. Silver-plated waveguide surfaces have been assumed; thus, the standard silver parameters in ECSS [18] are used as follows. δmax = 2.22, Emax = 165 eV, E1 = 30 eV, and taking v0 = 6.68 eV, SEY at low energies of 0.5.

The multipactor noises are investigated in the time domain and the frequency domain, respectively. A conformal time domain finite integration theorem (TDFIT) and particle in cell (PIC) hybrid method are used to simulate the dual-carrier multipactor discharge in the time domain [19]–[22]. Furthermore, two separate simulations, electromagnetic (EM) simulation and dual-carrier multipactor, are conducted in this work. Except for the difference of seed electrons, other simulation conditions such as RF fields, SEY, and material parameters are the same in both cases. In the dual-carrier multipactor simulation, the number of seed electrons is set as 600, which is employed to analyze the multipactor noise. In the EM simulation, the number of seed electrons is set as 0, which is employed as a controlled experiment to confirm that the RF noise only relates to the multipactor discharge.

The simulation results are shown in Figs. 3 and 4, where Fig. 3 illustrates the changes of the total electrons in the silverplated rectangular waveguide. It is easy to see that there is a significant increase in the number of the resonant electrons after 6 ns, which means the multipacting resonance occurs at t > 6 ns

Fig. 4 shows the results of the EM simulation (no multipactor) and dual-carrier multipactor discharge simulation in a silver-plated rectangular waveguide. The red dashed line represents the simulation result of the EM simulation, where the multipactor discharge is not presented due to the absence of seed electrons. The blue dashed dotted line represents the simulation result of the dual-carrier multipactor discharge. It is important to notice that a time-varying convection current is generated in the dual-carrier multipactor discharge simulation. This convection current is caused by the resonant electrons and always treated as multipactor noise because they can affect the integrity of the propagating signals [23], [24]. Comparing the results between Figs. 3 and 4, it is easy to see that the intensity of multipactor noise increases with the total number of the multipactor electrons.

In order to study the spectrum characteristics of the dualcarrier multipactor discharge, the simulation results in Fig. 4 are further analyzed in the frequency domain using a standard Fourier transform algorithm, and the corresponding results are shown in Fig. 5. The blue dashed dotted line and the red dashed line represent the power spectrum of the dual-carrier multipactor simulation and EM simulation, respectively. We can clearly see that the odd harmonics ( f , 3 f , 5 f , …) and subharmonics ( f /3, f , 5 f /3, …) emerge and decrease with the frequency ft, and ft is the frequencydomain variable of time t. As also shown in Fig. 5, a good agreement between the simulation results and the theoretical analysis results (i.e., the cyan open circles) is observed.

V. CONCLUSION

Although it is well known that the RF noise could be caused by the multicarrier multipactor, the frequency components of the multicarrier multipactor noise have not been sufficiently investigated. In this article, an analytical method of evaluating the spectrum characteristics of the muticarrier multipactor has been proposed. According to our investigation, the frequencies of the multipactor noise can be described by 2πnf/N, which are directly related to the multipactor discharge resonance order N and the frequency of the RF field. This conclusion is useful for designing the noise compression components or filters to eliminate the RF noise caused by multicarrier multipactor discharge.

ACKNOWLEDGMENT

The authors would like to thank prof. V. E. Semenov, Institute of Applied Physics, Nizhny Novgorod, Russia, for his helpful discussions in the theoretical analysis. The authors would also like to thank Dr. Yiming Zhang, Maritime Institute, Nanyang Technological University, Singapore, for his helps in the simulations and in the proofreading of this article.

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PB2020.11 A Relay Discharged FICDM Method for Improved Repeatability

Download PDF – A Relay Discharged FICDM Method for Improved Repeatability

Abstract – A new design for CDM testing is proposed that retains the field charging DDT method while providing a consistent discharge inside of a reed switch. The method is shown to adhere to the current JS-002 standard and to perform at low voltages, but JS-002 failures could not be exactly replicated.

I. Introduction

A CDM event occurs when the pin of a charged device approaches an external metal object such that the potential difference exceeds the breakdown voltage of the air gap between them. The device generally becomes charged by either E-field charging, in which electric fields near the device cause the potential of the device to change without changing its net charge, or Tribo-charging, in which a static charge is generated when the device slides on another surface [1]. The field induced CDM method (FICDM) is one of the best methods to simulate a true CDM event. In this method, the device is placed on a dielectric sheet, under which a plate of varying voltage levels changes the potential of the device, thereby emulating the E-field charging method. However, current FICDM testers are plagued with repeatability issues due to the variable spark resistance of the air discharge making the practice difficult to standardize [1 ][2]. As CDM testing voltages decrease, the variability of the air discharge increases, causing concern over the ability to meaningfully classify devices at lower voltages [3]. This is becoming increasingly problematic as the necessity for classification at lower levels is becoming greater with advances in IC technology [1].

This work presents a CDM tester that incorporates a relay into the pogo pin structure and maintains adherence to the Joint CDM Standard ANSIIESDA/JEDEC JS-002 [2] for FICDM testing. The use of a mercury wetted reed switch in the pogo pin allows for a more consistent spark resistance during low voltage pulses when compared to discharges in air. The method also preserves the field induced charging method which closely replicates the real world CDM charging mechanism. This method may produce failures that cannot be exactly replicated by other contact first CDM testers [4]. The new CDM tester is evaluated in comparison to a standard FICDM system through discharge waveform comparisons on calibration modules and device failure analysis.

II. RP-CCDM Tester

A. Discharge Circuit

The RP-CCDM [5], or Relay Pogo-Contact First CDM is a design of the CDM discharge head that allows for the use of a repeatable relay discharge while largely preserving the design parameters of the JS-002 standard. Figure 1 shows a cross section of the RP-CCDM head.

As shown in Figures 1 and 2, the RP-CCDM uses the field charging method as well as a similar discharge path to the one specified in the JS-002 standard. To charge the device, the pogo pin of the RP-CCDM ground plane is lowered to contact the DDT pin, then the field plate is brought to the specified charge voltage. At discharge, the reed switch is closed and the current flows up the pogo pin, through a high bandwidth In resistor, and to ground. The voltage is measured across the In resistor from which the discharge current waveform is then calculated.

B. RP-CCDM Testing Procedure

The RP-CCDM charges the DDT after the pogo-pin has contacted the pin to be tested. This is to ensure failures due to non-measured currents passed through the capacitance between the lower pogo and the ground plane or through the capacitance inside the reed switch like the currents observed in [6][7], do not occur when the non-charged pogo tip touches the DDT. By contacting the pin ofthe DDT first, the potential of the lower portion of the pogo-pin is slowly increased concurrently with the potential of the device. Thus, no high frequency transient can pass through the capacitances as might occur if the neutral pogo tip touched a higher potential pin on the DDT. The single and double discharge methods specified in the JS-002 standard can still be used for pulsing in the RP-CCDM depending on when the discharge relay is closed. The process for the single discharge method, which was used for all tests in this work, is as follows:

Single Discharge Method

1) Test starts with reed switch open; field plate grounded

2) Descend and touch DUT

3) Switch field plate relay to HV at specified TC voltage x voltage ratio

4) Wait for DDT to charge

5) Close reed switch, measure the CDM current

6) Switch field plate to ground

7) Open reed switch

8) Rise and move to next pin

C. Reed Switch

The reed switch used in the pogo pin structure was chosen specifically for its small form factor. The switch was soldered directly to the center of the In current sensing resistor. A small 3mm pogo pin was soldered directly to the bottom lead of the reed switch to keep the length of the pogo structure as small as possible such that the inductance of the structure would not increase drastically. To analyze the impact the new structure would have on the capacitance and inductance of the RLC discharge circuit, a ZDUT measurement was taken of the system. This measurement setup can be seen in Figure 3. The outer rim of a SMA connector was soldered into a cutout on the center of a copper plated FR4 sheet, which is much larger than the CDM head ground plane, approximately 30 cm x 20 cm, and connected to Port 1 of the VNA. The CDM head to be analyzed was attached to Port 2. The pogo pin of the CDM head was placed on the center pin of the Port 1 SMA with the ground planes parallel and the S11 measurement was extracted from which the ZDUT was extracted. Figure 4 shows the ZDUT measurements of a standard FICDM and the RP-CCDM discharge heads. The measurement displays three clear regions where each of the components in the circuit dominate. The first positIve slope represents the frequency range where the inductance of the VNA ground loop dominates, the negative sloping region represents where the capacitance between the plates dominates, and the third region represents where the inductance of the pogo structure dominates [8].

The values of the capacitance between the plates and the inductance of the pogo structure were estimated by fitting the impedance curves of capacitance and inductance values to the ZDUT measurement. This was done by finding a linear best fit line between the peak and trough of the ZDUT and matching the capacitance or inductance value to the center frequency of the best fit line. The fitted lines provide rough estimates but allow for a general assessment of the differences between the discharge heads. This method yielded a significant increase in the inductance from approximately 4.5nH in the CDM pogo structure to approximately 8.9nH in the RP-CCDM pogo structure. Little difference was noted between the capacitance created by the RP-CCDM and standard FICDM head.

D. Charge Stored in the Pogo Tip

The tip of the RP-CCDM pogo structure is electrically isolated from the upper portion of the structure and the ground plane. As a result, there is a small charge that is stored in the tip when the DDT is charged. When the relay is closed the small amount of charge travels through the 10 current measurement resistor with the true stress current. To measure the extent to which this would be a factor in the discharge, the large verification module was charged at a field plate voltage of 500V with the pogo touching. After the module was fully charged, the head was raised up and the relay was closed. Figure 5 shows the discharge waveform measured from repeating this procedure ten times compared with the discharge from a JS-002 small verification module. The current measured is most likely negligible if the DDT is large. However, this could be of significance when testing a small DDT since the current produced from this extra charge is independent of DUT size. The possible effect on failure levels of small devices has not yet been evaluated.

The charge transferred during one discharge of the tip was compared to the charge transferred during one discharge of the small JS-002 module as a reference of the impact the additional charge could have, this is shown in Figure 6. Over 10 pulses the average charge transferred in a discharge of the pogo tip was 0.029 nC, whereas the charge transferred in a discharge of the small module was 2.593 nC on average. Thus, the charge stored in the tip represents approximately 1.14% of charge discharged from small verification module.

III. RP-CCDM vs FICDM Discharge Characteristics

A. Comparison of Standard Test Conditions

To test the discharge characteristics produced by the RP-CCDM head, it was tested using the small and large verification modules defined by the JS-002 standard [2]. The comparison data was collected using a standard FICDM head, also manufactured by ESDEMC Technology. The modules and pogo tips were cleaned with isopropyl alcohol before testing as well as the field plate dielectric surface. The humidity of the test environment was lowered to below 10% RH during testing of the standard FICDM head using a desiccant and compressed air system. As per the JS-002 standard a voltage factor was used to correlate the charge voltage with the desired discharge current. The voltage factor used for the RP-CCDM was 1.08 and the voltage factor for the standard FICDM was 1.02. The true 10 current measurement resistor values were 1.026 and 1.030 for the standard FICDM and RP-CCDM heads, respectively. All waveforms were measured using a 6GHz Bandwidth Oscilloscope.

A full test of both setups verified that they complied with the JS-002 standard measurements. The pulse width of the RP-CCDM was considerably longer than that of the standard FICDM head, especially with the larger module. This can be attributed to the increased inductance of the pogo pin. However, the RP-CCDM head easily fits into the pulse width specification in the JS-002 standard. Some distortion in the peak area is also seen across both modules. It is not clear yet whether this distortion has any impact on the failure levels of devices.

B. Linearity of Discharge Current

The main advantage of the RP-CCDM is the ability to produce a repeatable discharge inside of the reed switch portion of the pogo pin. Figures 9 and 10 were created by normalizing the current and voltage relationship of the TC125 test to 1, for both the standard FICDM and the RP-CCDM. A value of 1 represents a perfectly linear relationship. The highlighted region around the centerline represents where the highest and lowest pulses fell at each test level. To illustrate the repeatability benefits.

In addition to a more repeatable discharge, Figures 7 and 8 show the RP-CCDM is also able to produce a peak current that is more linear with respect to increasing voltage. The much lower pulse to pulse variation of the RP-CCDM would make it easier to standardize the failure levels of devices, which has been a large issue with standard FICDM testing [1].

C. Low Voltage Performance

Since the peak current variation is less in RP-CCDM configuration, this will provide better repeatability at low voltage levels. Table 4 and Figure 11 show the results of 100 discharges performed with a field plate charge voltage of 75V using the JS-002 small verification module for both the standard FICDM head and the RP-CCDM head.

As shown in Figure 12, the RP-CCDM can produce repeatable pulses within a +/- 5% window of the peak current even at voltages well below the lowest test condition used for classification.

Further, the RP-CCDM was tested at lower voltages to find where it could no longer produce repeatable pulses (at these voltages the standard FICDM was too unstable to trigger properly). The RP-CCDM tests were run in two ways: first, with the pogo pin sitting on the small verification module, charging and discharging without moving, and second, with the standard single discharge procedure. These results, tabulated and shown in Table 5 and Figure 12, showed that the pulse was less repeatable when the pogo pin re-contacted the disk every pulse. This difference is most likely due to small differences in contact resistance between pulses and highlights the impact contact resistance can have at very low voltages.

At 10V, over the course of 100 pulses there were many extraneous pulses for both stationary and moving tests, likely making the RP-CCDM pulse unclassifiable at this level. These results are tabulated and shown in Table 6 and Figure 13.

IV. Device Failure Analysis

Test ICs were used to investigate the failure correlation between the standard FICDM and the RP-CCDM test setups. Pre-charging voltage values are 500 V, 625 V and 750 V, while two devices are tested per each method using three discharges per polarity. The chip offers several power and 10 domains that are all stressed either in the FICDM test or RP-CCDM test, respectively.

The device failure analysis of the correlation study between FICDM and RP-CCDM is carried out via IDDQ testing. The failure is expected for pre-charging voltages higher than 500 V and located on the edge of the digital core. The IDDQ analysis measures the current consumption in the quiescent state on 200 vectors in the digital core.

The quiescent current into VDD for all vectors is below 100/lA, in case of an unstressed reference device. Slight deviations in this range are traced back to normal variations. A significant increase of the current compared to the reference device indicates a gate-oxide failure on the edge of the digital core.

The device stressed at 500V using FICDM method shows a current consumption below 100 /lA, indicating the device can withstand the stress. The device stressed at 625 V using FICDM method, shows an increased current consumption up to 180 /lA, which indicates a failure. The failure analysis of the devices stressed at 500V using RP-CCDM method, showed an increased current consumption between 210 /lA and 250 /lA, indicating failures. The device stressed using RP-CCDM method at 625 V, the measured current level is higher compared to the reference, and higher than the IDDQ values of the devices tested at 500 V using RP-CCDM method. Both failure analysis results for RP-CCDM method are interpreted as a device failure.

By comparing the IDDQ measurements for the failing devices, analyses show a very similar change for the same vectors. This is a strong indication that both test methods trigger the same failure mechanism. In order to get a deeper understanding of the failure mechanism and find out the pass level, a new device is tested with RP-CCDM at 400 V. The IDDQ analysis shows that the device can withstand this stress level. The IDDQ analysis is shown in Figure 14.

The discharge waveforms of a sensitive 10 pin are plotted for FICDM and RP-CCDM in Figure 15 and Figure 16, respectively. FICDM waveforms are recorded with 23 GHz bandwidth, RP-CCDM waveforms with 12 GHz bandwidth (different bandwidth is simply due to the RP-CCDM test being run at a later date with a different oscilloscope). The discharge waveforms are symmetric regarding the polarity, therefore, for simplification, only the positive waveforms are plotted. By comparing the peak currents of the discharges on the 10 pin, a dependency of the failure level on the peak current can be determined. The peak currents of each stress corresponding to the shown waveforms are listed in Table 7. The IDDQ analysis and the peak current values lead to the conclusion that the failure is triggered from exceeding the maximum peak current the device can withstand. According to the peak current values, the failure threshold is located between 4.1 A and 4.7 A.

The failures are reproducible for all tests with a statistic of four devices each, while all pins of the device are stressed.

Even if the waveforms for RP-CCDM are characterized by a longer pulse width and a slightly increased peak current, the total exchanged charge during the discharge event does not offer a significant difference between the different pins and testing methods. This is visualized with a box plot for twelve positive discharges on two devices and various pins in Figure 17. Further, the box plot shows that the RP-CCDM method produces less variation.

The EMMI scan for a failing FICDM and RP-CCDM device indicate that the spot of the failure is located in the core at the same place, meaning both methods trigger the same failure mechanism. Pictures of the failure signature are shown in Figure 18.

The failure level is further investigated by using Capacitively Coupled TLP (CC-TLP). This method allows correlating peak current levels or different pulse width settings to CDM stress parameters and can be applied to investigate CDM type failure modes [7, 9]. For the test device used in this study, the failure can be reproduced at about 5 A, using CC-TLP. FICDM and RP-CCDM failure levels are slightly different concerning the pre-charging voltage, but the CC-TLP test result supports that the failure mechanism is the excess of a certain peak current value.

The increased peak current of the RP-CCDM compared to the standard FICDM test could be adjusted with the test condition according to JS-002 in the future. RP-CCDM waveforms are very stable and the variation between several discharges is negligible, which is a benefit compared to FICDM.

Variations between standard FICDM discharges can be referred to the statistical influence of the spark that again varies with multiple parameters, such as the charging voltage or physical dimensions of package pins or balls. The spark limits the peak current and the oscillation, because of the resistive characteristic, which is considered as a series resistor and inductor in a circuit simulation [8]. Further, a slightly higher effective device capacitance could be assumed in the case of the RP-CCDM test, since the pogo pin is already touching the device before the discharge. This increase in capacitance is due to the fact that field plate and ground plate are closer together. The interaction between the device capacitance and tester capacitances are material for further investigations, including the altered resistance and inductance relationships.

V. Conclusion and Further Investigations

The RP-CCDM demonstrates that it can produce CDM pulses that closely match the pulses produced by a standard FICDM head within the testing framework of the JS-002 standard. However, device failure levels produced by the RP-CCDM head did not directly correlate to failure levels produced by the standard FICDM head. In the case study, the gap between failure levels at 500 V and 625 V can be referred to as a slightly higher peak current in the case of the RPCCDM waveforms. Further investigations into the current that could flow from the capacitance between the pogo pin and the ground plane or within the reed switch when the uncharged pogo tip contacts a charged DDT are needed. Full-wave simulations of the RPCCDM system are planned in order to better understand the effects any unmeasured currents may have on the test results.

VI. Acknowledgements

We would like to thank Dr. Kai Esmark from Infineon Technologies AG for providing the testing devices, for his support regarding the failure analysis and for sharing his wide knowledge of ESD, and in particular, of CDM.

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PB2020.09 Effect of RF Signals on TVS Diode Trigger Voltage for ESD Protection

Download PDF – Effect of RF Signals on TVS Diode Trigger Voltage for ESD Protection

Abstract— Discrete transient voltage suppressor are used in addtion to the on-chIp ESD protection to protect the ICs from ESD damage. In applications involving snapback TVS devices, the trigger voltage is selected to be higher than the desired signals on the net. The presence of RF on the net affects the TVS behavior, even the RF levels are less than the snapback trigger voltage. Known affects are RF intermodulation and harmonic generation, which diminish HNR. This work describes the other effect on the TVS diodes, the observed reduction of the snapback trigger voltage, monotonically dependent on the amplitude of the RF signal. This translates into snapback triggering at low stress levels than specified in the datasheet or expected by the design engineer. TLP testing was performed using a 100 ns pulse with RF signal from 100 MHz to 2 GHz present at the diode terminals. The result show that the higher frequencies have a weaker impact on the reduction of snapback trigger voltage, and the phase of the RF signal impact the amount of reduction in the trigger voltage. It is also observed that certain TVS diodes recover from snapback even when the RFamplitude is higher than the holding voltage of the diode.

Keywords— Electrostatic discharge(ESD); radio frequency(RF) signals; snapback devices; transmission line pulse(TLP); TVS.

I.INTRODUCTION

ICs are designed with internal protection elements to protect them for component level electrostatic discharge (ESD) stress events. In addition to the component level protection circuits, external transient voltage suppressor (TVS) devices are necessary at system-level to provide sufficient ESD robustness to a device [1]. Based on the signal interface type, appropriate TVS device are selected based on various TVS parameters and the signal interface design requirements. In [2], various TVS devices such as diodes, varistors, spark gaps, and polymers were analyzed using a custom designed board and the pros and cons were discussed for different use cases. The PIN limiter diodes which are typically used for power limiting applications, were analyzed in [3] to quantify their ESD robustness on RF paths and compared against the protection capability of a TVS diode. In [2]-[3], methods for characterization of protection devices were evaluated. ESD simulator, 100 ns TLP and VF-TLP are common measurement approaches to evaluate various devices for component-level ESD characterization. VNA measurement is used to evaluate impact of the protection device on signal integrity.

In [4], the harmonic generation of the diodes is characterized to understand their RF large signal behavior. RF was applied, but no TLP pulses have been applied at the same time. The authors of [5] propose a system that combines TLP and RF, but not simultaneously. It subjects the device under test (DUT) to TLP pulses, then followed by RF measurement (S-parameters, IIP3, noise figure, etc.) to characterize the DUT. The work presented in [6] characterizes the RF devices before and after ESD event. It was shown that the performance of RF circuits and devices can degrade at ESD stress levels below the failure levels proposed by the commercial human body model (HBM) testers. However, none of these works address the possibility of RF signals being present at the time of the ESD pulse.

In this paper, the ESD protection capability of the TVS diodes was experimentally characterized during the presence of RF signals at the diode. The goal is to quantify the change in the TVS behavior. Two types of TVS diodes were investigated: the non-snapback and the snapback type. The snapback type diodes are designed to have a holding voltage Vh lower than the trigger voltage Vt1. An example of snapback behavior in the I-V curve is illustrated in Fig. 1.

It is shown that non-snapback diodes are largely unaffected, but snapback device Vt1 is changed by the RF. At 100 MHz it is observed that Vt1 reduces proportionally to RF amplitude. The effect decreases with increasing RF frequency. A new measurement method was proposed which applies both the RF and the TLP pulse at the DUT simultaneously. The transient voltage and current, and the quasi-static I-V curve are analyzed. Based on the experimental results, an additional consideration is proposed for the TVS diode selection on RF interfaces.

II.MEASUREMENT SETUP

A. Traditional TLP characterization process

The industry-defined standard [7]-[8] 100 ns TLP setup consists of five main parts: a pulse generator, a voltage probe, a current probe, an oscilloscope, and a DUT – e.g., an ESD protection TVS diode. The simplified block diagram is shown in Fig. 2. The quasi-static I-V characteristic of the TVS diode under test is extracted from 70-90% window of the transient V(t) and I(t) waveforms captured by two channels of an oscilloscope.

The typical testing approach is to perform a sweep of the TLP charge voltage, and establish several characteristics: a) diode breakdown voltage Vbr, b) diode dynamic resistance Rdyn; in case of snapback TVS diodes: c) holding voltage Vh, d) snapback trigger voltage Vt1. In addition, device self-heating effect and physical failure levels can be observed.

The very fast TLP (VF-TLP) variation [9] of the characterization setup is often used for evaluating transient behavior of the protection devices (e.g. switching speed) for shorter pulses (1-10 ns) and shorter rise times (100-600 ps). This work, however, focuses on the 100 ns TLP test configuration.

B. RF+TLP characterization process

The 100 ns TLP setup allows for a wide variety of test results, but assumes no RF signal present across the diode terminals. A novel testing method is proposed; it allows to force RF signal on the DUT during characterization. ESD protection devices are evaluated in this scenario and the effect of RF on their performance is observed.

The RF+TLP test setup modifies the 100 ns TLP measurement system by ESDEMC [10]. The simplified block diagram is given in Fig. 2. The signal generator RF Source output is amplified to 15 W using AMP1. The 20 dB attenuator ATTEN1 reduces the stress seen by AMP1 output terminal, as TLP pulse is injected via a T-junction TEE1. As the pulse is injected, part of it propagates towards the amplifier and is subsequently dissipated and absorbed, while the other part is forced on the DUT.

Oscilloscope Channel 3 with a CT1 probe is used to determine the current that is forced into the DUT. Oscilloscope channel 4 with attenuator ATTEN2 measures the voltage at the DUT terminal. The original voltage pick-off tee and the CT1 probe on oscilloscope channels 1 and 2 respectively measure total injected current and voltage close to the injection point. Captured VDUT(t) and IDUT(t) are processed in the same way as the standard TLP in order to produce quasi-static I-V curves.

 

III.RESULTS

Four TVS devices are evaluated in this work, as mentioned in Table I.

A. Effect of RF on non-snapback TVS diode I-V characteristic

TVS1 is a non-snapback diode with Vbr = 9 V and Rdyn = 2.1 Ω. The effect of RF at 100 MHz, 1 GHz, and 2 GHz on this non-snapback diode is negligible. As an example, the effect of 100 MHz on the I-V curve is depicted in Fig. 3.

Figs. 4 and 5 illustrate the time-domain voltage and current waveforms during the presence of RF signals. To obtain the quasi-static I-V curve, the 70-90% window is applied to the time-domain waveforms. The voltage and current values during the 70 ns to 90 ns time are averaged to obtain the I-V curve plot. For a 100 MHz RF signal, the period is about 10 ns, which covers 2 cycles within the 20 ns long averaging window. Similarly, the period for 1 GHz RF signal is 1 ns and about 20 cycles are superimposed on the TLP signal in the averaging window. Lastly for a 2 GHz RF signal, the period is about 0.5 ns and about 40 cycles are overlapping in the I-V curve averaging window. Therefore, for each RF signal a full number of periods fall in the averaging window, thus the effect of added RF voltage is zero in average. In case of other frequencies, incomplete cycles within the 70-90% averaging window may affect the I-V curve values depending upon the phase of the RF signal and the TLP pulse. Furthermore, it is expected that lower frequencies may introduce more change in the I-V curve. In this case, the cycle is wider, resulting in stronger contribution to the average value calculation, as opposed to a narrower incomplete cycle (i.e. of a higher frequency signal).

B. Effect of RF on snapback TVS diode I-V characteristic

TVS2 is a deep snapback diode with Vt1 = 18.1 V and Vh = 2.6 V. The effect of RF with varied Vpp at 100 MHz on this snapback diode is depicted in Fig. 6. The effect on I-V curve is not strongly observed at 1 GHz and 2 GHz RF. Contrary to the non-snapback TVS diodes, the snapback diodes do exhibit reduction in their snapback trigger voltage Vt1 in the presence of RF signals. The reduction in the Vt1 also reduces with the frequency of the RF signal. At 3 Vp 100 MHz RF signal, a maximum reduction of 2.8 V is measured on the Vt1 of TVS2. TABLE II gives a summary of the effect for TVS2 snapback trigger voltage.

A deep snapback device showed reduction in the snapback trigger voltage, though a non-snapback TVS diode did not exhibit any change in its clamping behavior. To investigate this unique snapback TVS behavior, additional snapback TVS diodes are measured. TVS3 is a shallow snapback diode with Vt1 = 4.6 V and Vh = 2 V. The effect of RF with varied Vp at 100 MHz, 1 GHz, and 2 GHz on this snapback diode is depicted in Fig. 7. TABLE III gives a summary of the effect for TVS3 snapback trigger voltage.

 

The time-domain voltage and current waveforms of TVS3 during the presence of 100 MHz RF signal are plotted with and without RF. Fig. 8 illustrates the voltage and current waveforms prior to the snapback trigger. Fig. 9 illustrates the waveforms after snapback occurs. Contrary to the voltage time-domain waveforms in Figs. 4 and 5 for a non-snapback device, the voltage waveforms in a snapback device exhibit two key differences in their response. Consider the TLP waveform from 0 to 100 ns as the reference. For non-snapback TVS, the Vpp cycles are superimposed equally above and below the TLP pulse. However, for snapback type devices, the RF signal is not superimposed equally on the TLP pulse. Secondly, the Vpp swing on the non-snapback during the TLP pulse is not the same as the Vpp prior to the application of the TLP pulse. These two observations suggest why the two types of devices respond differently to the same RF signal.

The effect at lower frequencies is due to superposition of the voltage waveforms, so that the diode snapback triggers as , thus snapback occurs at lower TLP stress than nominally. At higher frequencies, the effect is weaker and does not follow this rule. A negative monotonic relationship between the RF frequency and reduction in Vt1 is observed.

When each measurement is repeated multiple times, another effect on Vt1 is observed: the voltage varies with the phase of the RF at the moment of the rising edge of the TLP pulse. The effect is illustrated in Fig. 10, and summarized for TVS4 for 100 MHz RF and swept RF amplitude. The figure shows positive monotonic relationship between reduction in Vt1 and RF amplitude. However, the trend does not follow the expected linear reduction of Vt1 with amplitude increase, caused by superposition of RF and the TLP pulse.

C. TVS device appears to not recover from snapback

TVS4 is a shallow snapback diode with Vt1 = 4 V and Vh = 1 V. The effect of RF with 1-7 Vpp at 100 MHz on the diode is depicted in Fig. 11. In this case, the TVS4 was only measured at 100 MHz, as maximal reduction in other snapback TVS diodes was observed at this frequency. The Vpp was increased to observe the trend in the reduction of the snapback trigger voltage. At 5 Vpp and higher, the TVS diode appears to not recover from snapback, but rather appears to stay in that regime for all consecutive pulses as long as RF is present on the net. Normally, this happens if Vdc > Vh and leads to diode damage. While a detailed understanding requires knowledge on the type and implementation of the snapback structure within the TVS a preliminary explanation is suggested. The RF voltage causes currents for two reasons:

Conduction current: if the peak amplitude of the RF current is large enough before diode turn-on, carriers are injected into the base regions (assuming SCR snapback TVS). Thus, even a weak excitation can trigger the snapback. Fig. 12 (b) compares transient voltages and describes the diode triggering and switching to low-impedance regime (i.e. snapback). It is evident from the curve corresponding to 5 Vpp RF, that triggering happens at a much lower voltage than in nominal conditions (i.e. “No RF”). Although not fully understood, it is reasonable to assume that the time needed to flush out charge carriers will influence the severity of this effect.

Displacement current: the RF voltage will cause a current in the parasitic capacitive paths within the TVS. This current may also inhibit the return from snapback.

TVS2 and TVS3 were tested for similar effect, but only reduction in Vt1 was observed. This suggests that specificity of die layout defines whether the appearance of snapback latch-up will occur.

IV.DISCUSSION

In the process of interface protection design, it is important to account for the reduction in the trigger voltage of snapback TVS diode due to the presence of the desired RF signals. The following difficulties can be anticipated and avoided if the diode is well characterized:

As observed in Fig. 12 (a) the current through the diode at RF Vpp = 5V is much higher than Vpp = 4 V prior to the arrival of the TLP pulse. Thus, the RF signal voltage will drop across the diode and reduce SNR at the receiver.

The increased current at higher RF Vpp = 5 V is only observed after the snapback device is triggered once by the transient event. The device remains in this state (conducting current) at large RF Vpp as long as the RF signal stays across the device.

Various non-linear effects of a TVS diode (e.g. voltage- dependent capacitance, etc.) cause intermodulation distortion (IMD) and harmonic generation [11], which degrade receiver performance. It is likely that a diode that behaves like TVS4 will cause stronger harmonics, leading to antenna desense. This behavior is an avenue for further investigation.

As RF Vpp increases, the snapback diode behaves effectively like a non-snapback TVS as observed in the I-V curve in Fig. 11. The figure shows an effective trigger voltage of Vbr < Vh. From the quasi-static behavior of the device, it appears that the TVS does not recover from snapback for the cases where Vpp = 5 V, 6 V, and 7 V. However, the time-domain waveforms in Fig. 12 depicts that the TVS goes into snapback at Vdiode << Vt1. It should be noted that the RF signal was constantly applied at the TVS device throughout the testing. This behavior was only observed for consecutive TLP pulses.

The root cause of the RF frequency dependence on device behavior is not well understood and needs further investigation. Device transient behavior simulation using SPICE-based models [12], [13] and TCAD are a possible tools to further analyze the reduction in trigger voltage due to presence of RF signals. Particularly for the lower frequency RF signal such as 100 MHz, the phase alignment of the RF pulse with the TLP pulse affects the reduction in the trigger voltage.

V.CONCLUSION

While selecting a snapback TVS diode for providing ESD protection on RF interfaces, the effect of RF signals on the trigger voltage of the diodes must be taken into consideration. Based on the proposed TLP + RF characterization setup, it was observed that in presence of RF signals, the TLP voltage that is needed to trigger snapback is reduced. The sample size of 4 diodes is limited and no generalizations can be made, however the trends show the following: 1) the effect of Vt1 reduction is positively dependent on RF amplitude, 2) reduction in Vt1 shows negative dependency on RF frequency, 3) non-snapback TVS diodes are largely unaffected by the RF signal.

For one of the investigated TVS diodes a sufficiently large RF signal makes the TVS appear to not recover from snapback. Due to the presence of RF, even weaker ESD stress can easily trigger the TVS diode into snapback. This effect is expected to take place when Vp > Vh, but the results suggest that this is not necessarily the case for all diodes. Each protection device should be evaluated separately. The system designer must account for a lowered trigger voltage for the snapback TVS diodes. A typical data sheet of a protection device does not provide information about the change of protection characteristics under various operating conditions. Including the effects observed in this work would lead to a more accurate understanding of the devices.

ACKNOWLEDGEMENT

This paper is based upon work supported partially by the National Science Foundation under Grant No. IIP-1916535.

 

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PB2019.08 Robustness of PIN Limiter Diodes to an ESD Event Based on VF-TLP Characterization

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Abstract—PIN limiter diodes are primarily used for protection from excess RF power in RF circuits. These diodes are positioned onboard at the I/O lines of the RF circuits. If an ESD event occurs, the first line of protection is offered by the PIN limiter diode. The main questions addressed in this letter are: Can the PIN limiter diode protect the RF circuit against ESD? If yes, then what is their ESD robustness? How do they compare against the standard ESD protection TVS diodes? This knowledge can guide the reader to understand whether or not the PIN limiter diode can help prevent ESD damage. The robustness of the diodes is investigated experimentally using a very fast transmission line pulse tester with a 10 ns pulse width and about 300-400 ps rise time. These diodes are tested for their withstand current, turn-on time at 1 A current, turn-on voltage, voltage clamp at 1 A current, capacitance, signal bandwidth, and effective package inductance. These diode parameters are essential in quantifying the component-level response of a device under test. This letter shows that the PIN limiter diodes are not a suitable replacement for the TVS diodes as an intentional ESD protection device. In case an ESD event occurs, these diodes are robust to ESD current levels up to 2.5-9 A and offer limited protection. They may effectively complement the TVS protection by offering a fast turn-on time and protection up to a certain ESD level, after which the (slower) TVS takes over.

Index Terms—ESD, PIN limiter diodes, TVS, vector network analyzer (VNA), very fast transmission line pulse (VF-TLP).

I. INTRODUCTION

Electrostatic discharge (ESD) protection has become a necessary design element in high-speed RF and microwave circuits. However, introducing ESD protection elements on RF circuits may cause RF performance degradation [1]. To prevent RF performance degradation, devices with low capacitance are designed and implemented [2]. Protection elements can be designed and implemented internally to the high-speed RF ICs, or they can be implemented using onboard external devices such as TVS components [3]. Onboard protection methods involve the use of primary and secondary protection devices [4]. The ESD protection device is placed before the component/part to be protected from ESD as shown in Fig. 1. Here, the primary onboard protection is placed near the source of the ESD stress, and the secondary protection diode (on-chip) is inside the protected device.

Under normal operating conditions, the protection devices offer high impedance and behave as a capacitance to the signal path. When an ESD event occurs, the onboard primary protection device is intended to carry a majority of the ESD-induced current while the secondary protection device carries the remaining current. During the event, the protection device turns on and clamps to its clamping voltage. At this clamped state, the impedance of the device is low, and it diverts the ESD current from signal trace to the ground. As a result, the device is protected from the ESD event.

PIN diodes are used in various applications such as switches, attenuators and phase shifters [5]. PIN limiters differ from the PIN diodes based on the doping of gold atoms in the I layer (middle layer) of the diode. The gold doping in the I layer reduces the minority carrier lifetime. The time the diode takes to recover from the low impedance state back to high impedance state (after the application of RF input signal bursts) is proportional to the minority carrier lifetime. Therefore, a lower minority carrier lifetime represents a faster diode recovery time [6]. A protection device from Keysight [7] known as an integrated diode limiter, consists of two limiters which can provide both power limiting and ESD protection; i.e., utilizing limiters for an ESD protection application. The ESD robustness of PIN limiters has not been reported in the literature. The PIN limiters may also provide ESD protection, even though they are typically used as power limiters.

In this letter, the ESD protection robustness was experimentally investigated for the PIN limiter diodes with low capacitance and surface mount style packages. The diodes were tested using a VF-TLP tester with a 10 ns pulse width, and about 300-400 ps rise time. This setup has a faster rise time and a shorter pulse width than the 100 ns standard TLP waveform. The IEC 61000-4-2 specification [8] stipulates that an I/O trace of interest on the PCB or an RF-circuit will not be subjected to a direct ESD discharge. The IEC pulse is expected to occur at a different location in the system. A regular TLP pulse has a rise time of approximately 10 ns. More important parameter than the pulse width is the rise time to assess the voltage overshoot during an ESD generator discharge. A VFTLP pulse [9] has a much faster rise time, typically 0.6 ns. A TLP waveform with a 100 ns pulse width and a rise time of 0.6 ns could be used, but it would not be possible to distinguish between two potential failure mechanisms, over-voltage due to the fast rise time and thermal damage due to the long pulse width. Thus, a narrow fast rising pulse is considered a better match than 100 ns TLP or IEC pulse.

II. ESD PROTECTION COMPONENTS

A. PIN Limiter Diodes

Fig. 2 (a) depicts a typical power limiter application using the PIN limiter diodes. These diodes are soldered from trace to ground, which is similar to the implementation to the ESD protection implementation shown in Fig. 1. PIN limiter diodes from different vendors such as Macom/Aeroflex, Skyworks, and Microsemi were investigated.

B. TVS Diodes

TVS diodes are specifically designed to protect devices against damage from ESD events. PIN diodes can be a part of the internal structure of a low capacitance TVS diode [10] as shown in Fig. 2 (b). In this TVS configuration, PIN 1 and 2 would typically be designed such that ESD robustness for both polarities is approximately equal.

The TVS diodes are one of the most effective ESD protection devices amongst the other TVS components [3] such as varistors, spark gaps, and non-linear polymers. The focus of this letter is to investigate the robustness of various PIN limiter diodes to an ESD event and compare it against a TVS diode [11].

III. VF-TLP TEST SETUP

The device under test (DUT) I-V curve was measured using an ESDEMC VF-TLP tester [12] illustrated in Fig. 3. The I-V curve was used to extract diode parameters described in detail in Section IV. To evaluate the performance of the diodes, a grounded coplanar waveguide (GCPW) prototyping PCB board was used. The VF-TLP measurement setup details are as follows:

Non-overlapping time domain reflectometry method was used to measure the DUT current and direct voltage measurement method to measure the DUT voltage [13].

A VF-TLP pulse width of approximately 10 ns was applied to the DUT, to evaluate the first few nanoseconds response.

An oscilloscope with 20 GSa/s sampling rate and 6 GHz bandwidth was used. The rise time of the VF-TLP pulse measured at the oscilloscope was approximately in the range of 300 to 400 ps.

To determine the quasi-static I-V curve, the measurement window was set at 70% to 90% of the pulse width. The measurement window setting was applied to the flat region of the waveform. A measurement window is the range of time within the pulse width where the voltage or current of the pulse is measured to calculate the DUT voltage or current in response to the applied VF-TLP pulse [14].

• VF-TLP pulse polarity: An ESD event can have both positive and negative polarities. Emphasis was placed on the reversed bias diode clamping and its ESD current carrying capacity. In reversed bias orientation, the turn-on voltage is higher than the forward biased (p-n junction) turnon voltages approximately in the range of 0.7 to 0.8 V. It should be noted that the forward biased polarity is much more robust than the reverse biased polarity. This argument is based on the lower power dissipation of the forward biased orientation against the reverse biased orientation. For example, for the same TLP clamp current, the forward bias diode clamp voltage is lower than the reversed bias voltage and their turn-on voltages are different. In addition, this is strictly true if the current for the forward and reverse polarity are flowing through the same device (internal to the package).

The source measure unit (SMU) measured the leakage current of the DUT when 1 V was applied to the reverse polarity of the DUT after each TLP pulse.

IV. DIODE PARAMETERS AND MEASUREMENT RESULTS

The measurement results are shown for one PIN limiter diode Microsemi 4701-206 [15].

A. Capacitance

The capacitance is determined to be 0.25 pF at 50 MHz. The frequency point is determined from the 20 dB per decade region of the Z21 vs. frequency plot shown in Fig. 4 (a).

B. Frequency Bandwidth and Effective Package Inductance

A 3 dB cutoff point is chosen as the usable frequency bandwidth of the diode. The dotted line in Fig. 4 (b) represents the diode’s frequency bandwidth (approximately 14 GHz). The dotted two-sided arrow is a visual representation of the 3 dB insertion loss of the diode in excess of the trace insertion loss. The diode is modeled as a series RLC circuit in the passive (non-conducting) state. The LC resonance of the diode (approximately 19 GHz) is used to calculate the effective package inductance (0.27 nH) given by the formula:

C. Turn-On Time, I-V Curve, and Leakage Current

1) Turn-On Time: Using the VF-TLP tester setup, the diode time-domain voltage and current waveforms were measured for each VF-TLP source excitation voltage. In general, the DUT voltage waveforms can have inductive overshoot, snap back behavior or the non-inductive overshoot [16] for the very first nanoseconds and then followed by a relatively flat voltageclamping region. The non-inductive overshoot is caused due to the conductivity modulation in the silicon [17]. The qualitative illustration for the overshoot and the non-overshoot response of a diode is shown in Fig. 5. The diode clamp current is determined from the diode current waveform by applying the measurement window setting. The measurement window of 70% to 90% was applied to the diode voltage waveform, and the time-averaged voltage value was determined (VDUT). Vtrack refers to the voltage amplitude 30% above in case of an overshoot response and 30% below in case of non-overshoot response in the measured diode voltage waveform. The time associated with Vtrack voltage is called t2. The difference between the two times t2 and t1 is calculated as the turnon time. It should be noted that if a different % criteria is used for Vtrack, the turn-on time values for different diodes would change, but the overall trend and conclusions will not be affected. The diode current of 1 A is chosen as a comparison unit for the turn-on time parameter. A current of 1 A through the diode is typically used by TVS vendors for determining the diode clamp voltage [11]. In Fig. 6 (a) the vertical dotted lines represent the two time values that result in the turn-on time of 2.16 ns for the TVS diode and 0.21 ns for the PIN limiter diode. It should be noted that for the PIN limiter diode at 1 A current, the waveform was considered as a non-overshoot waveform to determine the turn-on time parameter. It was observed that the TVS diode [11] voltage waveform has an overshoot response in the initial nanoseconds followed by the flat clamping region.

2) I-V Curve Plotted for a Measurement Window of 70% to 90%: The VF-TLP pulses are applied to the DUT. Each pulse generates a diode current and diode voltage waveform. The measurement window is applied to the diode voltage and current waveforms to determine the average voltage (VDUT) and current (IDUT) values. The VF-TLP currents are in the range of 10 mA to 20 A. In this measurement range, the instrument applies about 50 pulses to the DUT. This generates an array of 50 voltage and current values, which are represented in the form of an I-V curve plot as shown in Fig. 6 (b).

3) Withstand Current: The VF-TLP pulse voltage at which the leakage current increases 10x to 100x from the initial leakage current value of the diode is chosen as a selection voltage. A VF-TLP pulse voltage lower than the selection voltage is chosen as the maximum withstand voltage. At this particular VF-TLP pulse voltage (maximum withstand voltage) the current at DUT (diode) is determined as the maximum withstand current the diode can handle. It should be noted that the SMU measures the diode leakage current after the application of every VF-TLP pulse. A withstand current (IDUT) of 3.7 A (using a 10 ns VF-TLP pulse width) is determined for the diode shown in Fig. 6 (b).

4) Turn-On Voltage: The voltage at which the diode current is in the range of 1-10 mA is determined as the diode turn-on voltage. Using this definition, a value of 21.8 V is obtained from the I-V curve plot shown in Fig. 6 (b). Here, the turn-on voltage refers to the quasi-static voltage measured at 70% to 90% of the pulse width, and not to the maximum dynamic voltage.

5) Voltage Clamp at 1 A: The voltage corresponding to a diode current of 1 A is used to determine this parameter. It is a parameter provided in TVS datasheet [11] to quantify the clamping behavior of the diode. The voltage clamp for different current levels can be determined from the complete diode I-V curve shown in Fig. 6 (b). Using this parameter definition at 1 A diode current, a voltage of 28.8 V is obtained from the I-V curve plot. This voltage value indicates that for a 1 A current through the diode, this diode will clamp at a voltage of 28.8 V.

V. DISCUSSION AND CONCLUSION

Table I summarizes the different diodes tested, and their performance based on critical parameters. The diode capacitance, inductance, and frequency bandwidth parameters are essential to quantify the influence of the diode on signal integrity while the diode is in a passive state (during a non-ESD event). ESD withstand currents of about 2.5 A to 9 A have been observed, as well as turn-on voltages in the range of 20 V to 50 V. A frequency bandwidth of 6 GHz to 16 GHz is achievable, based on the different diodes tested in this letter. Diodes having smaller packages may offer larger bandwidths, due to the lower capacitance and inductance. The PIN limiter diode data was compared with an industry standard ESD TVS protection diode. Although most of the PIN limiter diodes that are shown in Table I may have faster performance for the turn-on time parameter than the ESD TVS diode, the ESD TVS diode has better performance in all other ESD diode parameters. Still, a PIN limiter diode may be part of a circuit design to protect against accidentally coupled high RF power. In this scenario, the PIN limiter diode will offer a moderate level of ESD protection.

Considering a system level ESD requirement for PIN limiter diodes, based on the faster turn-on time parameter, they can complement the TVS diode for the initial low-current ESD event. However, the TVS diode needs to turn on before the current through the PIN limiter crosses the withstand current. It should be noted that the turn-on voltage of the PIN limiter diodes are higher than that of the TVS which may limit the applicability of the PIN limiter and TVS combination. Thus, a system efficient ESD design (SEED) [4] will be needed further to evaluate a specific PIN Limiter and TVS diode combination for ESD protection application on a desired I/O trace.

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PB2018.10 Pin Specific ESD Soft Failure Characterization Using a Fully Automated Set-up

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Abstract – A fully automated system is developed for the systematic characterization of soft failure robustness for a DUT. The methodology is founded on software-based detection methods and applied to a USB3 interface. The approach is extendable to other interfaces and measurement-based failure detection methods.

I. Introduction

In order to mitigate ESD-induced soft failures (SF) of a system, its robustness must first be evaluated. In light of the various parameters that influence the response of the system, it is best to use an automated characterization process. The outcome helps system-level and IC designers, and firmware developers.

The world of soft failures is diverse and has been studied in [1]-[8]. In this work, the device under test (DUT) is an Intel Joule 570x Internet of Things (IoT) platform. The USB3.0 interface was selected for characterization. USB3 related SFs were studied in [7]. Several disturbance methods were evaluated: system-level IEC, magnetic loop probe, conductive TLP injection, and directional injection. Soft failures were correlated to the stress parameters: the pulse rise time didn’t seem to affect the failure threshold, while pulse width was found to be inverse proportional to it. The authors found no correlation between CPU stress and failure modes, but no other DUT load was explored. Furthermore, the root-cause analysis of more severe modes were performed and a strategy for SF-SEED was proposed. This work confirms some of the earlier findings and extends others. The main idea is to develop a software-based method for an automated and systematic pinspecific characterization, and to explore methods for such data processing that can extract useful information.

The automated system is able to provide quantitative information on the dependence of different failure thresholds on the injected pulse level, polarity, rise time, system load and state, pin-to-pin variation, etc. Eight failure types across four severity levels were identified for the given system and failure dependence on various system loads was established.

II. Characterization Process

The TLP injection system by ESDEMC [9] was used to deliver repeatable pulses to the DUT. The TLP system combined with an oscilloscope allowed the injected currents and consequential voltages to be measured. The TLP was controlled through GPIB and COM interfaces to the “Control PC”, as shown in Figure 1.

Additional in-house software on the “Control PC” handled:

The detection and recognition of failure modes,

Sweeping of injected stress levels and polarities,

Controlling the DUT over secure shell (SSH) protocol through the network (either through cable – LAN, or WiFi – WLAN), and

Controlling other peripheral hardware (MCU).

A microcontroller unit (MCU), controlled over a serial interface, was used to switch two power relays: one for power cycling the DUT, another for tripping the power of the USB3 client device plugged into the host DUT port (interface under test).

A. Set-up description

1. Measurement set-up

The Intel Joule system consists of two separate parts – an expansion board and a compute module, as shown in Figure 2. The compute module contains all the key ICs (CPU, RAM, eMMC, Bluetooth, WiFi, etc.), while the expansion board provides power and fan-out to various interfaces (HDMI, microSD, USB3, USB-C, GPIO) with respective ESD protection devices. The compute module plugs into the expansion board through a 100-pin HiRose (HRS) surface-mount SF40 interconnect. In order to isolate the effects of the IC itself, rather than the effect of external ESD protection, an interposer board was developed. It was placed between the expansion board and the compute module, allowing injection of TLP pulses into the running (i.e., “hot”) USB3 interface data lines of the DUT, without significant loading of the USB3 signals. This was achieved by using lowcapacitance TVS diodes, an injection technique developed in [8]. The circuit is shown in Figure 3 and the board is shown in Figure 4.

In the current work, three pulse lengths were used in the robustness evaluation: 100 ns, 6 ns, and 2 ns. The injection and measurement setup for the 100 ns pulse is presented in Figure 5. Figure 6 shows the setup for the 6 ns and 2 ns injections.

For the 100 ns injected pulse width, a current probe and deconvolution code was used to capture the injected current; for short pulses, a pick-off T combined with a delay line were used to separate the incident and reflected pulses (vf-TLP method). The DUT and the peripheral hardware layout are depicted in Figure 7. The USB3 client device was a USB3.0 SanDisk memory stick. It is reasonable to expect that client-to-client variation will be minimal if TLP injection directionality is sufficiently high (i.e. the largest portion of the stress is injected towards the DUT, while the plugged in client experiences minimal stress).

2. Test Procedure for One Pulse

After calibrating the TLP injection and measurement system, the characterization procedure starts. For each injection level the following steps are taken:

1. Set the desired TLP voltage level;

2. Confirm that the DUT is in the “nominal” state (i.e. idle running and reporting);

3. Confirm that the interface under test is in the “nominal” state;

4. Inject a TLP pulse into the target pin;

5. Measure the waveforms and extract quasistatic voltage and current points;

6. Acquire kernel logs from the DUT;

7. Check if logs contain error messages;

8. Check if the interface under test is still in the “nominal” state;

9. If any abnormality is detected, classify and log the signature;

10. Detect soft failure mode;

11. Reset the USB interface to the nominal state (re-plug and check interface state);

12. If needed, reset the system to the nominal state;

13. Repeat for the next pulse level.

Each of the listed steps contains several sub-steps which complicate the characterization process. The full algorithm is discussed in the subsequent sections.

B. Automation Algorithm

The algorithm flow is almost fully depicted in Figure 8. The whole automated characterization process is run mostly from the “Control PC” by two separate software programs, along with an additional software program running on the DUT. One is the TLP software, and another is an inhouse Python script. Voltage level, polarity, number of pulses, and number of injections for each level are set in the TLP graphical user interface. The TLP GUI also controls each injection and measurement, calibration, and current deconvolution. Upon a successful TLP injection, the GUI reports measured data to the Python script via an interface ASCII file, and proceeds to wait until the next injection is initiated. A “successful TLP injection” means that the current and voltage waveforms were measured without oscilloscope clipping and triggering problems. If clipping occurs, the TLP has to fire again in order for the scope to retrigger. This may cause system upsets without a proper V-I measurement. However, this happens only when the system transitions to a new stress injection level. Since each pulse is repeated ~100 times, sufficient information is collected to measure enough points for a quasi-static IV curve. Upon receiving the data from the TLP software, the Python script pulls the kernel logs from the DUT via the SSH interface. The DUT runs Ubuntu GNU/Linux operating system, so by running the dmesg command [15] and filtering for USB-related events with grep command, the algorithm is able to establish whether a USB-related SF has occurred or not.

Some difficulty in the algorthm arises in three areas:

1. Bringing the DUT and the interface under test into the “nominal” state at every pulse;

2. Making sure that connections to the DUT and peripheral hardware are correctly opened and closed.

3. Differentiating between certain failure types based on the recovery method when the log message is unclear (e.g., failures that have similar signatures, but one requires a reboot, while the other – a power cycle).

These complications are caused by the SF and often manifest in the following ways:

a disrupted connection to the DUT;

causing a lost connection to the DUT due to a reboot;

a need to reboot or power cycle the DUT to overcome the failure;

a SF occurs, but no kernel message appears in the logs; the USB client device must be replugged to re-establish connection and reevaluate the state of the DUT USB interface.

Obscurity of kernel messages can cause the algorithm to branch out and spend time “Detecting Soft Failure Type”, as depicted in Figure 9. The detection is rather simple: for each failure mode, there is a condition that needs to be satisfied. In the overall structure, there is a hierarchy of conditions that stack up from less severe to most severe. The left brach detects USB2 fallback-related failures, the right one detects USB3-related ones.

Because SF behavior varies somewhat randomly, each test is performed up to 100 times. The data points (TLP voltage, injected current, voltage, polarity, state of the system, SF type) from each test are recorded in a *.csv file and later processed by a Python script using Pandas (code library used for big data analysis) [13]. The multi-dimensional data analysis is aided by constructing pivot charts grouped by the desired characteristic (e.g., injected current, pulse width, rise time, etc.) and calculating how often an SF type has occurred for each variation.

III. Results

A. ESD Gun testing

The Intel Joule development system was mounted inside an enclosure and a series of ESD gun tests were carried out. The purpose of the tests is to establish the range of soft failures when systemlevel stress is applied to different parts of the DUT: a) shield of USB3 port, and b) DUT chassis. An ESD Gun, Noiseken ESS-2000 TC-815R, was used to inject impulses in the range between 1 kV and 9kV, in contact discharge mode. The DUT and the injection points are shown in Figure 10. Each injection was repeated 100 times, while the operator monitored and logged occurring soft failures. Discharging into the DUT chassis (point 1 in Figure 10) was relatively robust, causing the HDMI screen to flicker several times at higher discharge voltages, but having no reported USB failures. Screen flicker is a kind of SF within the system, but unrelated to the USB3 interface, so it is not discussed in detail.

The results of the ESD gun testing for system-level stress injected into the USB3 shield are shown in the Figure 11. Most of the soft failures are related to the HDMI screen (flickering, tinting with colors, screen turning off until HDMI cable replug). USB3 soft failures occur after 6kV, with a likelihood of

B. Soft Failure Classification

Observed soft failures can be categorized sufficiently well by Table 1 from [7], repeated here as Table 1. Category “A” is the least severe – the user does not notice the effect of failure and no intervention is required on their side. Category “B” is noticeable, but the system recovers without intervention (data transfer speed drops, the system reconnects to the client device, etc.). Category “C” is most severe and encompasses a varied family of failures, which may require as little as re-plugging the client device and as much as completely power cycling the DUT.

The failure modes observed for the DUT mostly fall in the most severe category C. The full list and corresponding descriptions are in Table 2.

The most common SF is “USB3 re-enumeration” (Mode 2), which means that the DUT has reestablished the connection with the client device without user intervention; in this case, USB3 functionality is preserved and no further action is required. Sometimes this failure mode is accompanied by a GUI error message which requires user interaction, making this variation a Category C failure. The next failure mode variation is “fallback to USB2” (Mode 3). It occurs as a result of negative current injection and requires user intervention. The milder case requires a mere re-plugging of the client device; a more serious case requires system reboot or power cycling. These take much longer than a re-plug: 60-90 seconds to reboot vs 5 seconds to re-plug, which may be a major inconvenience to the operator. In case of positive high-current injections, a rare failure occurs that disables the USB interface and requires re-plugging, rebooting or power cycling (Mode 4). Occasionally, Wi-Fi functionality is lost (Mode 5), but no correlation between injection level and its occurrence has been established.

The worst case for modern hand-held and wearable devices is the soft failure that requires physically disconnecting the power. For portable devices that would mean taking out and re-placing the battery or flipping a physical switch. Neither of these are an option for different design and policy reasons (waterproofing, warranty, security, etc.). This makes the requirements for such failures to be more stringent than less severe failure modes.

C. Variation of Pulse Length

The results for the Sandisk USB client for 2, 6, and 100 ns pulse width stresses are shown in Figures 12-14 respectively. The pulse levels are swept from -70 V to +170 V. The assymetry is explained by the high risk of hard failure if the negative stress is pushed to higher levels (at least for longpulse case). The vertical axis is the likelihood of soft failure occurrence in percent; i.e., how often a particular SF has occurred out of all injected pulses for each particular pulse level and width.

The horizontal axis is the TLP charge voltage. As expected, at lower injection levels, no failures occur. For all cases, there seems to be a threshold, beyond which SF probability jumps from 0% to a substantial amount (between 50% and 80%). For lower duration pulses, this threshold is higher due to lower amount of energy delivered into the system. There seems to be little to no occurrence of serious soft failures for positive injections across the board. For positive current injections, only USB3 re-enumeration errors were observed. This is consistent across DUTs and other configurations. Only one case for the 100 ns injection had a somewhat severe fail – fallback to USB2, requiring the client to be re-plugged.

Negative current injections have a lower threshold and a richer variety of severe failure modes. USB enumeration failure rates are very small for short pulses, but increase to 53% from 0% at -50V TLP injection for 100 ns disturbance. However, the most interesting observation is that enumeration errors fall in frequency

D. Variation of DUT System State

One of the parameters of interest is soft failure occurrence under different system load conditions. There is prior evidence that the CPU load doesn’t have a significant influence on the likelihood of failure [7]. In this work, additional load conditions are explored by using a package stress-ng [14]. The package fully loads a 4-core CPU by using FFT function, reading and writing to RAM and eMMC. This load increases noise within the system, causing it to draw ~2x higher current and increasing overall system temperature. Hence, there is reasonable expectation that soft failures become more frequent, or more severe overall.

Ideally, one would repeat the full parametric sweep for each load condition. That increases characterization time many fold and is largely unnecessary, as baseline tests already show that no failures occur at lower injection levels. Therefore, in the interest of time conservation, only the threshold region for the positive injection sweep is selected for characterization under various load conditions. The results are shown in Figure 15.

The failure threshold stress current is the same for all cases and the occurrence levels vary between approximately 50% and 80%. Marginal variation from load to load is observed (within 10%). This confirms that the CPU load has only a weak influence on soft failure occurrence. RAM and eMMC loading shows similar results.

It must be noted that the DUT load condition sweep was not automated in this case, but automation is possible with reasonably small effort. For this, during the stage “Set DUT State” in Figure 8, the operator defines several Linux command-line interface commands to be swept (one for each test condition) and one overarching loop is added that re-runs the algorithm for different load conditions.

IV. Discussion

The scope of this work is in automating the characterization flow and in expanding the knowledge about soft failure occurrence in complex systems. The root cause of specific soft failures is still being actively researched [3-6]. Specifically, with USB3 [7] [8] it has been found that more severe failures (fallback to USB2, etc.) occur due to power domain disturbances, while errors in data transmission are overwhelmingly consistent with lower-level pulses, where stress waveforms increase the signal peak-to-peak voltage.

One can draw practical conclusions from the obtained characterization data. From the expected ESD levels and the coupling paths, the designer can estimate the safe current waveforms and levels. These can be compared to the failure probability data from the IC characterization.

The system developer may establish a probability threshold for each failure mode and use the method for a “pass/fail” evaluation. Depending on the product purpose, 20% failure rate may be acceptable for SF not requiring operator intervention

If soft failures are grouped, an envelope may be used to check the satisfaction of the passing criteria, e.g. “Max Envelope” on Figures 12-14.

A drawback of continuous, extensive TLP testing (especially with longer pulses) is the risk of “wearing out” the interface under test. This means introducing latent hardware failures by applying numerous pulses that under normal circumstances would not cause physical harm to the DUT.

Once the DUT is well characterized, the system designer can use that information to “get it right the first time” and/or reduce the number of product development iterations:

1.Make system design changes to mitigate some SF (system-, circuit-, and IC-level). This is especially beneficial in the early design stages of a product, when a designer is able to introduce additional protection, filtering, shielding, etc.

2.Make firmware or software improvements that would reduce severity or frequency of specific failure modes.

In cases that require inclusion of a measurement-based method (e.g. spike in current consumption of the interface) [4] [11] [12], at first it should be tested independently to establish the reliability and efficacy of the measurement method. Once the clear detection criteria are established, a function within “Detect SF Type” in Figure 9 can check if the criterion for detecting the SF has been satisfied. In order to adapt this characterization method to a different interface, at first exploratory work must be done to establish the variety of soft failure modes. Then hardware and software efforts are carried out. In terms of hardware – auxiliary boards may need to be designed to facilitate replugging, power cycling the interface of interest, etc. In terms of software – a function set within “Detect SF Type” must be written. These functions inquire and establish whether the criteria for SF detection have been met. In addition, interface initialization functions may require change. The rest of the algorithm largely remains the same.

V. Conclusion

An automated system for SF robustness characterization was developed and applied to a USB3 interface of an existing development platform for a number of stress pulse lengths and system load conditions. Test results were processed and soft failure occurrence likelihood statistics were obtained for various levels of TLP injections, and both polarities. In the scope of this work, software-based detection methods were utilized, but the methodology is extendable to other interfaces and measurement-based failure detection methods as well.

The methodology has a wide application range, but is possibly most useful for high-reliability systems that could not tolerate soft failures. One of the directions for further research is a deeper investigation into SF occurrence depending on system states (CPU load, GPU load, etc.) and a wider range of disturbances. Characterization and data processing methods are well established and may be extended for further study.

Acknowledgements

The material is based upon work supported by the National Science Foundation, Grant IIP-1440110. The authors would like to thank Nicholas Erickson of Missouri S&T EMC Laboratory for constructive criticism of the manuscript.

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PB2017.12 Step-Response-Based Calibration Method for ESD Generators in the Air-Discharge Mode

Download PDF – Step-Response-Based Calibration Method for ESD Generators in the Air-Discharge Mode

Abstract—The current IEC 61000-4-2 (2008) standard does not provide calibration specifications for electrostatic discharge (ESD) generators in the air-discharge mode. This is largely due to the well-known fact of poor repeatability in air-discharge measurements. This complicates identifying an acceptable tolerance range of a reference waveform for air discharge. The variability of the discharge waveforms is caused by variations in the spark length. A novel air-discharge calibration method is proposed, which avoids sparking. The method is based on measuring the step response of an ESD generator in the air-discharge mode using a mercurywetted relay. Possible nonlinear effects are identified during the contact-mode ESD simulator calibration at higher voltages; thus, in combination, an air-discharge calibration method is provided. This letter explains the method and shows excellent repeatability.

Index Terms—Air discharge, electrostatic discharge (ESD) generator calibration, ESD gun, step response.

I. INTRODUCTION

Electronic products must comply with IEC [1] and/or ISO [2] electrostatic discharge (ESD) immunity standards before entering markets. Contact discharge and air discharge are considered in these standards and have been analyzed in [3]– [6]. During contact-discharge measurement, the ESD generator (also known as “ESD gun”) tip contacts directly with the device under test (DUT). The discharge occurs when the internal relay of the ESD generator closes. In the air-discharge measurement, the internal relay is kept closed as the charged ESD generator approaches the DUT. The discharge in the air gap between the ESD generator tip and the DUT can occur when the distance reaches a certain length. The current-carrying charge carriers within the spark can either originate from surface processes or a result of gas discharge processes [7].

For contact discharge, the discharge current waveforms are highly repeatable because the high-voltage spark only occurs inside the ESD generator’s internal relay. Thus, it is possible to specify a standard waveform for the contact-discharge measurement. On the other hand, for ESD air-discharge measurements, it is well known that the current waveforms repeat poorly due to the variations of the spark resistance, which results from the variation of the spark length. The variations of the arc length are a result of the approach speed and the statistical time lag. The statistical time lag is affected by speed of approach, humidity, surface conditions, voltage, etc. [8]. Thus, it is difficult to define a reference current waveform for the air-discharge calibration.

To produce better repeatability in the air-discharge mode discharge current, two approaches exist.

1) Discharge at a spark length given by the Paschen equation [8]–[12]. This can be realized by slowly approaching the ESD generator, possibly combined with methods that reduce the statistical time lag. Here, strong ultraviolet light, high humidity, and graphite layers on the electrodes can be used. If this method is selected, the discharge waveforms will repeat well, especially above 5 kV. However, the current rise will be rather slow (e.g., 3 ns at 10 kV), as the long arc length leads to a slow drop in the arc resistance. The current rate of changes will be for voltages above 3 kV in the range of a few amperes per meter. Thus, the arc is stabilized at a low threat level. Most fine structure of the step response of the ESD generator and high-frequency components of the current waveform and fields will be suppressed by the slow drop of the arc resistance. Thus, the test is more determining the selection of the main RC components of the ESD generator. In addition, Ishida et al. proposed an air-discharge calibration method based on fixed-gap discharge [13]. The idea is to use a fixed gap to replace the varying distance between the ESD gun tip and the ESD target of the typical air-discharge measurement. The process used spark gaps from Paschen length down to one-third of Paschen length. The shorter strongly overvoltage gaps lead to fast rise times and high peak currents. As the spark length is fixed, the waveforms are repeatable. However, they are still influenced by the time-varying spark resistance. Another condition for this method to work is that the voltage rise, which is initiated by closing the internal relay, is much faster than the statistical time lag. Otherwise, it could happen that the discharge already occurs while the voltage is rising.

2) If a low voltage is used and the ESD generator approaches the ESD target fast, the arc resistance may approach an ideal step function. One would hope that its resistance changes from infinite to nearly zero in picoseconds. Achieving this would allow capturing the step response of the ESD generator. The problem is that the spark gap formed between the ESD target and the ESD generator tip does not act as an ideal switch even at fast approach speeds. Here, the method suggested in this letter improves this concept by using a mercury-wetted relay that approaches an ideal switch much better.

The approach presented in this letter avoids testing ESD generators in the actual air-discharge mode that have a spark at the tip. The proposed method measures the step response of the ESD generator in the air-discharge mode using a mercury-wetted relay. The details of the structure and the measurement setup are explained in the following sections. Human body discharge step response was also measured using the same mercury relay setup. In this measurement, the tester is first charged to certain voltage (1 kV) and then discharges with the mercury relay. The measured human body discharge waveform can serve as a reference for the air-discharge mode waveform for the air-discharge calibration.

II. STEP RESPONSE METHOD

A. Mercury-Wetted Relay

To measure a good approximation of the step response of the ESD generator, a mercury-wetted relay is mounted between the tip and the ESD current target. The additional structure has a length of 16.4 mm. It substitutes the actual spark (see Fig. 1). ESD current targets have a discharge pad at their center [1]. In this measurement, the discharge pad is replaced with the mercury relay, which is enclosed into an epoxy filled tube to ensure mechanical stability. The relay is activated once a permanent magnet is brought into its proximity.

B. Step Response Measurement for the ESD Gun

The mercury relay tube is screwed onto the center of the ESD target (see Fig. 2). The selected relay cannot withstand voltage higher than 2 kV, so measurements were performed at 1 kV.

An Agilent DSO81304A Oscilloscope was used in the measurement. Three ESD generators from different manufacturers were tested. They will be labeled as “ESDGUN1,” “ESDGUN2,” and “ESDGUN3” in the measurement results section.

C. Step Response Measurement for Human Metal Discharge

The event of human discharging via a hand-held metal (human metal model, HMM) forms the reference event for the IEC 61000-4-2 standard, and it can be tested how similar the step response of the air-discharge mode generators is to the HMM events. As shown in Fig. 3, the person is standing on an insulator and is connected to a high-voltage supply. The tester holds the air-discharge tip against the mercury relay when the step response is measured. The discharge current and transient field of two testers were measured; the text refers to them as “Person1” and “Person2.”

D. Transient Field Measurement

Previous research has shown that the transient fields of ESD generators in the contact mode differ strongly, especially in the higher frequency region [14]. The variation in the transient field often causes different equipment under test failure levels when using different ESD generators. Thus, the transient fields during a step response excitation were captured. Fig. 4 shows the setup of the transient field measurement. A shielded loop probe having a loop diameter of 1 cm is used for H-field measurement. The E-field sensor, which was shown in [15], is used in the measurement. The E-field sensor has a flat response from 2 MHz to 2 GHz. On the other hand, waveform deconvolution [16] is needed for the H-field data as the sensitivity of the loop probe drops at lower frequencies by 20 dB/dec. The H-field probe is good for up to 2 GHz. The transient fields at 10 and 40 cm distance from the ESD target center were measured. The discharge current, E-field, and H-field are recorded simultaneously. It should be noted that the transient field of the ESD generator discharge event is not rotationally symmetric [14]. The E/H fields in this setup were measured at different locations (see Fig. 4).

III. EXPERIMENT RESULTS

A. Repeatability

Achieving repeatability is the main challenge for every airdischarge calibration method. The mercury-wetted relay is the best possible approximation of an ideal switch; thus, it has achieved excellent repeatability in both human metal and ESD generator discharges. Fig. 5 illustrates the repeatability of the current measurement. The variation in the peak values are within ±1% with respect to the average peak value.

B. Discharge Current

The data shown in Fig. 6 compare ESD generators and discharges from people holding the air-discharge tip in their hand. The waveforms represent the step responses and the initial rise of all waveforms is similar. The rise time is determined by the “ideal switch” formed by the mercury relay, and it is also limited by the bandwidth of the oscilloscope. Since the ESD target shows ideal impedance up to 5 GHz, the measured discharge current data will be filtered by a 5-GHz first-order low-pass filter. The discharge current of ESDGUN1 in the contact-discharge mode (black dotted line) is also shown in Fig. 6.

Core findings from the discharge current comparison in Fig. 6 are the following.

1) The measurement method gives repeatable step response information that allows characterization of the ESD generators in the air-discharge mode without having any effect of an arc.

2) The peak values of these three generators varied between 6.4 and 7.8 A, which are well within ±15% of the average measured ESD generator peak values for a charge voltage of 1 kV (a larger sample size of ESD generators may show higher variations between ESD generators).

3) Comparing the 1 kV ESDGUN1 air-discharge step response (yellow solid line) to the contact-mode discharge (black dotted line) reveals a 2.6 A larger peak current value, which is partially explained by the difference in rise time. There is also significantly more charge in the initial peak of the step response. This agrees with the observation in [9]. The authors reported that the total charge of the air discharge is higher than the contact discharge in the same level. This can be explained by the fact that all metal parts downstream of the relay are not charged in the contact mode, but in the air-discharge mode, they are charged to the set voltage. The later parts of waveforms (after 10 ns) almost overlap. This results from having the same RC network for the contact mode and the step response.

4) The human metal ESD (“Person1” and “Person2”) showed larger current values of 7–8.2 A. This is caused by the local capacitance of the hand that is close to the grounded wall. This structure is bulkier than the tip region of most of the ESD generators leading to a higher current in the step response (see Fig. 3). The total charge of the human metal ESD was less than the total charge of the ESD generators. This is to be expected as in most of the cases, the capacitance of a human to ground is less than the 150 pF as specified in the ESD standard. Human-toground capacitances can be as low as 70 pF in a wood frame house [17]. For a given tribo charge value, the voltage on a human may reach double the value in a wooden frame house relative to the human standing (insulated) on a conductive floor.

5) All air-discharge ESD generators showed some ringing; each shows ringing at a different frequency. The human metal ESD does not show the double peak structure, which is (for historical reasons) part of the IEC standard’s reference waveform. It is known and has been reported many times that the human metal ESD only rarely shows the clear double-peak structure [18].

C. Transient Field Results

The setup of the field measurement is shown in Fig. 4. The following conclusions can be drawn from Fig. 7.

1) The peak field strength at 10 cm is between 4.5 and 5.5 kV/m at a 1 kV charge voltage. In a real air-discharge situation, one could not expect that the field strength increases linearly with voltage, as the rise time would typically increase with voltage.

2) The human metal ESD shows a much larger electric field in the later time of the waveform as a result of having a charged body. The ESD generators store the energy of the charged body in a discrete capacitor. Thus, these fields are not visible outside the ESD generator. Furthermore, the ground return path for an ESD generator and that of a charged human body is quite different. This may also contribute to the differences in Fig. 7.

3) The rise time is determined by the relay and the field sensors’ bandwidth (about 2 GHz); thus, it cannot be attributed to properties of the ESD generator.

The magnetic field data in Fig. 8 show that the peak values are in the range 9–11 A/m for the cases investigated at 1 kV, the rising edge is determined by the mercury relay, not by the ESD generators, and the H-field waveform shapes are similar to the corresponding discharge current waveforms at this distance.

IV. DISCUSSION

The air discharge is well known for its poor repeatability due to the variation of the spark length for approaching electrodes. Several attempts have been made in the hope of defining a calibration method for ESD generators in the air-discharge mode. Greatly improved repeatability can be achieved either by a fixed gap [13] or by only considering discharges at spark lengths defined by Paschen’s law. Although carefully controlling the experimental parameters such as approaching speed, humidity, and air pressure can improve repeatability, it is not possible to achieve the repeatability of the contact mode as long as a spark is part of the testing. The proposed method overcomes this by avoiding the arc and capturing the step response of the linear ESD generator. The measured currents and fields repeat well in the contact mode, such that differences between different brands of ESD generators become clearly visible. The data also indicate that the peak current variation between different brand ESD generators (sample size of only three) is in the same range (within ±15%) as accepted for the contact mode. As the spark is substituted by a relay, no useful rise-time measurement can be performed. We do not consider this as a disadvantage, as the rise time in air discharge is determined by the drop of the arc resistance, and the arc physics is independent of the specific model of the ESD generator used. Another concern is nonlinearity. If there are nonlinear elements in the system, such as a saturating ferrite, sparking to some floating metal, or simply a wrong highvoltage supply value, this will be detected in the contact-mode calibration. For that reason, we believe that the air-discharge calibration does not need to repeat the high-voltage testing. A description by step response is sufficient, as nonlinear problems would be detected during the contact-mode calibration.

V. CONCLUSION

A calibration method is proposed in this letter for ESD generator air-discharge measurement. The method is based on the step response, which is realized by using a mercury-wetted relay. The mercury relay measurements are highly repeatable, and it excludes any arc effects. Thus, the data show the effect of the ESD generator structure. This method has the potential to be a calibration method of the ESD generator in the air-discharge mode.

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PB2017.05 ESD Spark Behavior and Modeling for Geometries Having Spark Lengths Greater Than the Value Predicted by Paschens Law

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Abstract—The insulation of plastic enclosures provides protection against direct electrostatic discharge (ESD) discharges to the system inside. However, seams between plastic parts are often unavoidable. To increase the voltage at which an ESD will penetrate the structure of the seam can be modified. Four plastic arrangements are constructed to investigate the spark length and current derivatives and to understand the ESD spark behavior for geometries having spark lengths longer than the values predicted by Paschen’s law. A two to threefold increase of spark lengths was found for sparks guided by plastic surfaces compared to spark length expected from the Paschen value at the same voltage level. In spite of the longer path, a faster spark development is observed for sparks along the plastic surface. Plastic arrangements that provide detour and fold-back paths hardly reduced the total spark length. No significant effects of the plastic materials or the polarity were observed. The spark length increased as the (absolute humidity) Absolute humidity (AH) increased, and the current derivative decreased by about 20% as the spark length increased with (relative humidity) Relative humidity (RH) changing from 9% to 65% at 29 °C. The spark resistance is modeled by a modified Rompe and Weizel’s law, which distinguishes the spark development in the air and along the plastic surface.

Index Terms—Electrostatic discharge, modeling, spark.

I. INTRODUCTION

One method to achieve ESD robust electronic system design is to prevent sparking into the system. This can be achieved by a sufficiently insulating barrier. While even 0.3-mm plastic is usually not penetrated by ESD up to 25 kV difficulties are introduced by seams between plastic parts and openings that expose the inner circuits. The design choice can influence the tightness of adjacent plastic parts, the plastic materials, the wall thickness, and the distance to the electronics. Further the designer can shape the seams of adjacent plastic parts such that detours lengthen the spark path, or introduce fold-back structures that force the spark to develop against the electrostatic field direction. This article analyzes the effect of such design choices and provides an improved simulation model for the spark resistance which also includes situations in which the spark develops parallel to plastic surfaces.

A good starting point is to remind ourselves of Paschen’s law. It describes the relation between the static breakdown voltage as a function of the gap distance for homogeneous fields,

where U is the voltage in kilovolt (kV) and d is the distance in centimeter (cm).

However, a few practical electrode arrangements offer a homogeneous field. They differ in the following aspects:

1) Electrodes, such as Printed circuit board (PCBs) may have sharp tips or edges.

2) The spark path maybe guided along plastic surfaces as the spark penetrates between adjacent plastic parts of the enclosure.

3) The IEC 61000-4-2 test standard asks to approach the (device under test) Device under test (DUT) while attempting to discharge to it, thus, this leads to a change of the electric field strength.

It is generally known that sharp electrodes and paths parallel to insulating surfaces increase the length the spark can bridge. Our study has shown that for the voltage range relevant to ESD these geometric factors can increase the length by twofold or more relative to the value predicted by Paschen’s law. For approaching electrodes the opposite can happen: the discharge occurs at distances less than the value predicted by the Paschen’s law. This discrepancy is explained by a delay of the onset of the spark due to the statistical time lag while the gap is closing due to the approach velocity. This phenomenon leads to spark lengths below the Paschen value, reduced rise times and larger peak values. For approaching electrodes, the spark resistance behavior and its simulation is well documented in the literature [1], [2]. However, the lack of information on the spark behavior for spark lengths longer than the values predicted by Paschen’s law requires more investigation. Spark lengths longer than Paschen’s value are certainly more likely for voltages exceeding 8 kV as the effect of sharp edges is more pronounced at higher voltages. Further plastic surfaces, metallic edges, sur face contaminations, and humidity will reduce the statistical time lag. With reduced statistical time lag it becomes unlikely to experience shortening of the spark length due to the interplay of the approaching speed and statistical time lag. To our knowledge there is no comprehensive study of the spark behavior for plastic enclosures in a voltage range relevant to ESD.

The main questions addressed in this contribution are: What is the distance that a spark will bridge if it is guided by insulating surfaces of different shapes? How large are the current derivatives? And how can the current rise be simulated for this type of geometries?

This knowledge can guide the designer in selecting gap shapes and geometries that maximize the voltage needed to breakdown through a gap into an enclosure. If the breakdown cannot be prevented, the simulation models will allow us estimating the peak current derivative, which has been shown to be strongly related to soft-failures in products [5].

II. MEASUREMENT SETUP AND RESULTS

A. Experimental Setup

The experimental setup allows us controlling and capturing the following parameters.

1) The charge voltage is set by the operator. The setup is limited to 25 kV. The ground of the high voltage supply is connected to the ground plane, which forms the transmission line’s return path. The ESD current target is also grounded, thus the voltage is applied between the tip and the ESD current target.

2) The electrode shape and the geometry of the plastic arrangement is set to allow us straight, detour, and reversing spark paths, see Fig. 3.

3) Four different types of plastic materials have been used.

4) Testing is performed inside a climate chamber. The climate chamber does not allow us changing the air pressure. However, it has been shown that the value predicted by Paschen’s law is proportional to the air pressure for typical values on earth’s surface, i.e., it is reasonable that the results for spark lengths longer than the Paschen’s value will scale proportionally with air pressure. The testing has been done at a height of 300 m above sea level at about 40% RH and 23 °C.

5) The setup measures the discharge current and the electrode distance in the moment of the spark. The discharge current is measured via a current sensor as described in IEC 61000-4-2.

6) For measuring the spark length the moving electrode is attached to a slider via insulating fiberglass, see Figs. 1 and 2. The slider’s position is captured using a resistive position sensor. The discharge current triggers an S/H circuit that records the position of the moving electrode in the moment of the discharge.

A 7.5 m, 165 Ω transmission line was selected as discharging structure to provide a long enough square pulse. A value of 165 Ω is used as a compromise between the impedance of 266 Ω derived from the peak current definition of the IEC 61000-4- 2 standard (3.75 A/kV), charged cable discharges and lower impedance seen for the discharge of body worn equipment [3].

If no plastic arrangement or a straight path arrangement [see Fig. 3(a) and (b)] is used then the spark length equals the distance between the moving electrode and the current sensor. If arrangements (c) or (d) are used then the extra length within the plastic arrangement needs to be added to the electrode distance to obtain the total length of the spark path.

In plastic enclosures different types of interfaces are used. Some are folded back to increase the length of the gap and to force the spark to propagate against the electrostatic field. This approach increases the voltage needed for breakdown. To reproduce a set of different interfaces, the plastic surface has been machined to be smooth and pressed tightly to reproduce the situation encountered on products. One might expect that a spark cannot penetrate the gap between two plastic parts that are pressed together. However, it is known that holes as small as 10 µm will allow us a spark to penetrate through a seam, thus machining the surfaces on a milling machine does not prevent sparking. The four different plastic arrangements used for this investigation are shown in Fig. 3. They differ in the path style and path length. Arrangement (a) and (b) offer a straight spark paths parallel to the electrostatic field. Arrangement (a) used 3.2 mm thick plastic parts, while arrangement (b) uses 6.4 mm thick plastic parts. Arrangement (c) is created by offsetting two stacked 3.2 mm plastic parts. This leads to a detour for the spark, in which it partially travels perpendicular to the electrostatic field. Arrangement (d) forces the spark to travel against the electrostatic field. The total path that the spark travels along the plastic surface is 7.3 mm for arrangement (d). To obtain the total spark length, the section the spark bridges between the electrode and the plastic arrangement needs to be added.

If the voltage is above the minimal breakdown voltage the spark will partially travel guided by the plastic, and then bridge the section from the plastic surface to the rounded electrode in air. The length ratio between these two sections of the total spark length, depends on the plastic arrangement and the voltage. This experiment used a flat electrode (from the ESD current target) directly behind the plastic arrangement and the air discharge ESD generator tip as moving electrode. During the experiment the voltage was set and the electrode was approached towards the plastic arrangement. The approach speed was less than 10 mm/sec. While this speed is much less than the typical speed during ESD testing, it was observed that increasing the approach speed did not affect the results strongly for experiments that included a plastic arrangement. This indicates that the plastic arrangements lead to short statistical time lags. A short statistical time lag will lead to a breakdown at the moment the gap distance is reduced to a length that allows us a breakdown [1], [6].

The current sensor captures the current waveform leading to a system bandwidth (scope + cables + target) of about 3 GHz. Besides the spark length and the waveform, the peak current derivative is analyzed. This parameter has been selected as it has been shown that the peak current derivative often correlates to soft-failure thresholds on electronic systems [5].

B. Spark Length

The experiments involved setting the plastic arrangement, the charge voltage, and then approaching the electrodes. Sparking occurred above a voltage determined by the plastic arrangement. The current and the electrode distance at the moment of the sparking were measured and analyzed. Fig. 4 shows the spark lengths for different arrangements. Additionally, spark lengths according to Paschen’s law are included as a reference. A second reference shown in Fig. 4, is the discharge distance between two razor blades, arranged at 90o. The spark lengths obtained without plastic arrangement are very close to the Paschen’s values. This behavior is expected, as the arrangement is similar to the requirement for Paschen’s law, thus this result can be seen as indication for the correctness of the voltage setting and spark length measurement.

On the other extreme, Fig. 4 shows the measured breakdown distances for the razor blade setup. Here, additional measures were needed to reduce corona at the corners of the blades. The blades have been encapsulated in rounded electrodes for all regions except the region in which the sparking occurs. In spite of these measures, corona occurring at the sparking location (the center of the blades front edge) prevented the measurement for voltages exceeding 10 kV in the razor blade arrangement.

Using 3.2 mm thick plastic [see Fig. 3(a)] the spark values increased by a factor of about 2 compared to the Paschen value. For example for 10 kV, the values increased from 2.8 to 6–6.3 mm. Results using the 6.4-mm thick plastic [see Fig. 3(b)] indicate a further increase of the distance the spark can bridge. For example the value at 10 kV increased to 6.5–7 mm.

Intuitively one may expect that forcing the spark to propagate perpendicular or even against the electrostatic field would significantly decrease the distance a spark can bridge. However, the data does not support this hypothesis. The reverse arrangement having a plastic guided path of 7.3 mm, the spark length is 9.8–10.5 mm. This falls into a similar range as the arrangement (b) having a straight plastic guided path of 6.4 mm. The distance between the ESD current target and the air discharge tip is reduced because of the detour and the fold-back.

The seemingly counterintuitive observation that even a spark path against the electrostatic field will only marginally reduce the bridged distance, can be resolved if one considers that the developing spark modifies the local field as the streamer advances as an electrode [6].

While the underlying physical processes may not be fully understood the results clearly show a strong increase of the spark length if the spark is guided by plastic surfaces. This indicates that thicker plastic walls, or detour and reverse arrangements may not achieve the expected result of preventing sparking.

C. Effect of the Plastic Material

Table I presents data on the effect of selecting different plastic materials investigated for 15 kV using arrangement (b). The data are typical for other voltages and arrangements and give evidence that the selection of the plastic material does not strongly influence the sparking behavior. However, an important effect common to all plastic materials, is that the plastic arrangements significantly reduce the rise time and increase the peak current derivative of the discharge current. The results repeated well, see Fig. 5. This indicates that effects of possible surface changes or charge accumulation over repeated testing do not influence the results significantly. This is probably a result of having short pulses that transfer charges of less than 5 µC.

Further evidence to this effect is given by a direct comparison of the discharge currents presented in Fig. 5. (The waveforms are obtained using an RC discharge network instead of the transmission line structure.) Similar discharge currents have been observed for different plastic materials indicating that the discharge currents are independent of the plastic material. This might be explained by the fact that all plastic materials investigated have a somewhat similar relative permittivity in the range of 2.4–3.7. The data shown in Fig. 5 are supported by measurements at from –18 to 15 kV. The second, more pronounced effect is a faster spark development for the cases in which the spark is along a plastic surface. While the reason for the faster spark development has not been clarified in this study, the data clearly give evidence that the current derivative is increased, thus, the likelihood of damage or upset by ESD may be increased by spark paths along plastic surfaces. However, it was observed that the total distance the spark needed to bridge, has been increased by at least twofold.

We did not observe a strong effect of the polarity. This can be explained by the rather symmetric setup used in this investigation. One electrode is formed by the flat ESD current sensor while the other electrode is formed by the rounded ESD simulator air discharge tip.

D. Current Derivative

As discussed in the introduction section it is known that approaching electrodes can lead to spark lengths much shorter than the value predicted by Paschen’s law. During the delayed onset of the spark, the electrodes continue to approach, which increases the field strength in the gap. Once the discharge is initiated, the spark resistance will drop faster due to the increased field strength. This will also result into large peak current derivatives that may reach values of 1000 A/ns or more [1]. However, a long statistical time lag is required for voltages exceeding 8 kV to reach such high current derivative values. This requires a quasi-homogeneous field, clean electrodes and dry air. Most spark gap topologies encountered during air discharge mode ESD testing on products do not fulfill these conditions, i.e., the statistical time lag will be short. Throughout all our measurements, the peak current derivative remained in the range of 3–10 A/ns. Care must be taken to generalize these numbers as they will certainly be influenced by the source impedance of the discharge arrangement which was set to 165 Ω. However, the values will remain much lower than the values published for spark lengths shorter than the Paschen’s value [1]. Thus, one can use this value range to estimate the current derivatives and consequently induced voltages during ESD testing.

After having shown that neither polarity nor the plastic material selection strongly influenced the spark behavior the attention is moved to the effect of the plastic arrangement on the current derivative. The scatter plot presented in Fig. 6 details the effect of the spark length on the current derivative for different voltages and plastic arrangements. Data points on the left side of Fig. 6 shows spark lengths equal to the Paschen’s length (no plastic). The peak current derivatives slightly reduced as the voltage was increased from 10 to 15 kV. The middle section from 6–8 mm spark length of Fig. 6 shows results for plastic arrangement (a) that allows us a straight spark [see Fig. 3(a)] guided by 3.2-mm plastic. Although the spark length has increased from about 2.8 to 6.2 mm for 10 kV, the peak current derivative increased on average by 2 A/ns. This again indicates that the plastic surface not only allows us the spark to bridge larger distances, but also confirms that the spark develops faster in spite of its longer length. The right section of the plot presents the data for the detour and the counter field arrangements [see Fig. 3(c) and (d)]. The data is only shown for 15 kV, as not all arrangement showed a breakdown at lower voltages. In spite of spark lengths of more than 10 mm (about 3× the Paschen’s value for 15 kV) the spark development led to peak current derivatives in the range of 5.5–8.5 A/ns.

In summary, we conclude that the peak current derivatives for spark lengths longer than the values predicted by Paschen’s are in the range of 3–10 A/ns. The plastic guided spark can bridge up to 3 times the distance predicted by the Paschen’s value. In spite of these longer distances, the spark develops faster, leading to moderately increased peak current derivatives.

E. Influence of the Humidity

An ESD is affected by humidity by three mechanisms: in high humidity, the tribo-chargining is reduced [8]–[10], the conductivity of many materials is increased, leading to a faster charge decay, and the statistical time lag is strongly reduced [1]. The measurements, shown in Fig. 7, were conducted in a climate chamber where the environmental conditions can be varied between a relative humidity of 9% to 65% in a temperature range of 24 °C to 29 °C. The 6.4-mm plastic [see Fig. 3(b)] is used for the presented data at the right of the figure. For sparks guided by the plastic surface, the overall effect of the humidity on the current derivative is not strong. The spark length increases from 9.1–9.3 to 10.5–11.1 mm at 15 kV as the AH increases from 0.003 to 0.019 kg/m3. The data at 12 and 15 kV both show that by increasing AH, the peak current derivative decreases as the spark length increases. Overall, humidity has a minor effect on the experimental results.

III. SIMULATION OF THE SPARK RESISTANCE

It has been shown that the spark resistance law from Rompe and Weizel predicts the maximal current derivative over a large range of voltages and spark lengths in the range of 1.5–25 kV [1], [2], [11],

Based on the measured discharges in air while trying to achieve a good match between simulation and measurement, the spark constant KR is typically selected in the range of 0.5–1e–4 m2/(V2 s). However, the shorter rise times observed for sparks guided by plastic, (shown in Figs. 5 and 6), indicate that the spark develops faster if it is guided by plastic surfaces. To maintain a good match between simulation and measurements the value of KR needs to be modified if the spark is guided by a plastic surface. As seen in Fig. 8, a value of about 4e–4 m2/(V2 s) is most suitable for predicting the spark resistance drop for plastic guided sparks.

A second aspect that needs to be considered is that the initial spark originating from an ESD simulator tip, may be partially in air, until it reaches the plastic surface. Thus, one needs to consider both the spark distance in air and the spark distance along the plastic surface. Rompe and Weizel’s spark resistance law needs to be modified to simulate these cases. This is achieved by introducing a weighting function:

where p is the portion of the spark along plastic, Kplastic is the constant for the section parallel to the plastic and Kair is the constant needed to describe the spark development for the section in the air. The best match was achieved when Kair = 0.7e − 4 m2 /(V2 s) is used to model the section not guided by plastic, and Kplastic = 5e − 4 m2 /(V2 s) is used for the plastic guided distance.

To apply the modified law one should take the following steps:

1) Know the maximal voltage one wants to protect for.

2) Know the length of the section that is parallel to the plastic. This can be obtained from the mechanical drawings.

3) Estimate the total length of the spark, based, e.g., on information shown in Fig. 3.

4) Subtract the plastic guided path length from the total spark length. This provides the length of the section of the spark which is in air.

Using this information the both sections of the spark path are calculated and the modified law can be applied.

Using this modified spark resistance law, discharge waveforms have been simulated and compared to measurements, (for a constant path length along the plastic, but varying path lengths in the air [see Fig. 9]). This is achieved by increasing the voltage beyond the minimal value required to spark along the plastic. If the voltage exceeds this minimum limit, the distance of the section in air will increase. In the experiment the spark length section in air was measured using the setup shown in Fig. 1.

The peak current derivative is an important parameter as it often determines the peak induced voltage. The peak current derivatives and associated spark lengths are shown in Table II.

The results shown in Fig. 9 and Table II indicate that the modified law can predict the current waveform and especially the peak current derivative for sparks that are partially guided along a plastic surface.

IV. CONCLUSION

This experimental investigation into spark distances, current rise times, and the modeling of the spark resistance showed that sparks guided along plastic surfaces can bridge distances two to three times longer than the distances predicted by Paschen’s law. The introduction of detour paths or paths against the electrostatic field did not increase the voltage needed to bridge a spark.

In spite of the longer spark path, a strongly reduced rise time was observed for sparks along plastic surfaces comparing discharges at the same voltage. This accelerated spark development requires a modification in Rompe and Weizel’s spark resistance law to allow us predicting the peak current derivative for arrangements in which the spark partially is guided by a plastic surface. Further the results indicate that using different types of plastic materials hardly affected the measured currents or sparking distance.

Increasing RH resulted in a longer spark and a slightly smaller current derivative. However, humidity was not a strongly influencing factor.

It is suggested that the seam structure of the plastic enclosure for the electronic system be carefully designed to increase the voltage at which ESD will penetrate into the system by providing detour paths or paths against the electrostatic field to allow us placing the electronics closer to the enclosure.

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PB2016.09 IEC 61000-4-2 ESD Test in Display Down Configurationfor Cell Phones

Download PDF – IEC 61000-4-2 ESD Test in Display Down Configurationfor Cell Phones

Abstract— During the IEC-61000-4-2 test the DUT is placed on a 0.5 mm insulating sheet, which is on the horizontal coupling plane(HCP). For discharge points on the back side of the phone this leads to a situation in which the display is facing the HCP. The phone or tablet  forms a capacitance between 50 pF and 300 pF to the HCP. The capacitance value depends on the size of the phone, its screen flatness, and the flatness of the insulator which may deteriorate over time. The discharges to the phone lead to a large displacement current flow through the display. This current has multiple paths to the body of the phone: via the touch electronics, via the display electronics and directly to the body of the phone. As these currents can reach 30A(at 8 kV contact mode), they can lead to upset and damage of both the display and the touch layers. This paper provides analysis of the display down test situation in order to show reproducibiliby problems. The effect of the capacitance variation is shown by the measurement and the PSPICE model. Full-wave model was used to help understand how much of the total current flows through the body of the phone. The Lichtenberg dust figure method was used to show the contribution of the corona discharge.

Keywords— Electrostatic discharge, mobile phone, display, IEC-61000-4-2

I.INTRODUCTION

Improving display and touch screen technology is often associated with thinner glass and smaller structure size. The displays have to pass ESD testing and test levels of 25 kV are not uncommon, especially if they may be used in an automotive environment. The IEC 61000-4-2 test standard instructs placing the DUT onto a 0.5 mm insulating sheet, which is placed on the horizontal coupling plane [3]. For discharge points on the back side of the phone this leads to a situation in which the display is facing the HCP. The phone forms a capacitance to the HCP in the range of 50-300 pF. This leads to a large displacement current flowing though the display. At 8 kV in contact mode the current reaches 30 A. The current flows through the top glass as displacement current and distributes as conduction current between the touch screen, display, and body of the phone. Improved technologies for displays aim at strengthening the top glass, which increases its dielectric constant, and producing thinner displays which also increases the current for sparkless discharge to the display. Further, smaller touch structures and a higher pixel count in the display increases the likelihood of fused touch traces, and damaged or upset of the display layers or the associated LCD driver ICs or mainboard ICs.

Every immunity test aims at reproducing a real-world situation in the laboratory to ensure robustness against the selected situation. For a cell phone it is an unlikely situation that it would be placed display down on a flat, metallic surface since most surfaces phones are placed on are neither metallic nor flat. However, the large capacitance between the phone and the flat surface leads to the fact that the initial current of the ESD pulse (3.75 A/kV according to the standard for contact mode) is nearly fully injected into the phone and passes on as displacement current through the phone. This geometry is hardly found in reality, but the present implementation of the test inhibits progress in display and touch technology [1-2].

The paper cannot completely describe the current flow and the parameters dependent on this test situation because of the complexity of phones and tablets and the variability in test situations, but it illustrates aspects of the set-up which may be novel.

II.UPSIDE DOWN MEASUREMENT SET-UP

The general set-up situation is shown in Fig. 1. The phone is placed on the HCP. The discharge to the body of the phone will force displacement current from the body of the phone to the HCP, and via the resistive/inductive networks of the display and the touch layers to the HCP. The currents depend strongly on the flatness of the insulating layer. The phone will reach a high voltage relative to the HCP. The final voltage depends on the capacitance ratio of the phone to the HCP, the ESD generator capacitance, and the capacitance value the HCP has to its surroundings. Nevertheless, for high test voltages the voltage between the HCP and the phone is large enough to cause corona discharge on the insulating layer which is explained in section III of this paper.

III.MEASUREMENT RESULTS

A. Discharge Current Measurement

The DUT is placed flat on the insulating layer and pressed down during the test to achieve a constant capacitance value, and to ensure that the distance to the HCP is 0.5 mm. In other cases the DUT is placed partially on a spacer (tilt configuration) to change the capacitance between the phone and the HCP, shown in Fig. 2. The measured capacitances for those two cases are 65 pF and 30 pF, respectively; the peak current versus voltage is shown in Fig. 3.

The discharge current is measured using an F65 current clamp, connected to a well-shielded oscilloscope. Both contact discharge mode and the air discharge mode are used for the measurement, shown in Fig. 4 and Fig. 5. The tilt configuration measurement waveform is presented to show the effect of possible corona discharge. In the flat configuration, in which the displacement current is larger, the contribution of the corona current to the total current may be invisible. The difference of the current due to the capacitance variation by the flat/tilt arrangement is shown in section IV. When the peak current is analyzed, there is a linear relationship between the peak current and the charge voltage for contact mode. This may sound obvious as this seems to be a direct result of the contact mode circuit definition. However, if at higher voltages the corona current would significantly contribute to the peak discharge current, the peak current would increase in a nonlinear fashion: It would increase faster than the voltage because of the contribution of the corona current. In measurement we observed a nonlinear current rise around 20 ns after the peak which indicates corona discharge, as shown in Fig. 4. Corona is a process that does not repeat well, this will also lead to the low repeatability of test results if the response of the display is affected by the corona. Thus, test setups which are prone to corona should be avoided. In general, corona caused by surface discharges on the thin plastic layer covering the HCP needs to be considered for higher voltage ESD.

For air discharge the additional parameter of the arc length will complicate the analysis. The arc length will vary from discharge to discharge even if the same voltage is used, thus, the current rise will vary [4-6]. In this case only Lichtenberg dust figures allow to identify the charge deposition caused by the corona, see Fig. 7 and Fig. 8.

B. Corona Discharge

An additional problem arises from surface discharges on the top surface of the insulating material, shown in Fig. 6. These surface discharges will cause additional currents at the edge of the phone and can spread multiple centimeters away from the phone.

The charges deposited on the surface can be visualized by using the Lichtenberg dust figure method [6-8]. An example of such charge deposition measured at 25 kV is shown in Fig. 7 and Fig. 8. The surface discharge begins at around 20 ns after the initial pulse and, according to the measured data, adds tens of Ampere which can increase the likelihood of fused bridges in the touch screen layer and other damages or upsets in the touch and the display.

 

The corona discharges form tree-like structures. Their propagation velocity is about 1 mm/ns and they can contribute to multiple amperes of additional currents. A detailed photo is shown in Fig. 8.

IV.SIMULATION

A. Full-Wave Model of the Upside Down Test

The full-wave model of the upside down test helps to understand the current flow in a more detailed LCD structure. Here, the final goal is to model the display, including its inner structure, the flex cable connections, and the first level of I/O on the phone. However, this publication only shows the first steps, which also include the touch structure. A general overview of the simulation domain is shown in Fig. 9. The HCP size and its distance to the ground plane (PEC plane) are proportionally reduced to maintain the HCP to ground capacitances. This proportional reduction maintains the capacitance ratios, but it does change the wave propagation on the HCP during the first nanoseconds of the discharge, such that this effect needs to be investigate. A variety of simplification, such as modeling the ITO layer by an equivalent thin sheet are verified using multiple simulations.

For the first 5 ns, until the reflected wave reaches the ESD generator, the HCP acts as infinite large ground plane. This is also verified by the measurement of currents for discharges to the ground and HCP, shown in Fig. 10. The downsized HCP cannot model the with respect to the wave propagation on top the HCP during the first nanoseconds. Although the difference is not large, it is better to use simulation data that is obtained by using an infinite large ground plane during the first nanoseconds, and then later use the simulation data that is dominated by the capacitance of the HCP, thus data obtained from a proportionally reduced HCP size.

The detailed phone model is shown in Fig. 11, the touch screen patches are connected by thin bridges for one orientation, and each array of the touch screen layer is connected to the main board using a 10 ohm resistor (30 in total), the total current through the touch screen is the summation of the current through each array.

An S-parameter voltage port substitutes the relay contact of the Noiseken ESD generator. The excitation signal at this port is a step function with fast rise which represents the rapid voltage collapse of the discharge process [8].

The simulated current distribution is shown in Fig. 12. This illustration compares the current at the tip and the current in all touch layer connections. The result is valid for this specific case, however, it is influenced by the glass thickness, touch structure, ITO layer conductivity, etc. Here, the full-wave model provides a numerical way to investigate the effect of those parameters and it allows simulating the current in the bridges which are prone to fusing due to the high current density. The numerical model had 9 billion cells before the lumping process [10] and the number of cells was reduced to 7 million which led to a simulation time of six hours for 40 ns on a computer having two Intel(R) Xeon(R) CPUs and 64 GB RAM installed. A GPU-based system will reduce the simulation time further, allowing more details of the display and the flex connection to be introduced.

The current distribution clearly indicates that the initial peak current is mainly flowing as displacement current through the glass directly into the body of the phone, while the later current is flowing into the touch layers. This is a result of the resistivity of the touch layers. It is known that the current flow in the touch layers can fuse the bridges (see Fig. 11). The simulation allows capturing the current in the bridges. The current in one of these currents path is shown in Fig13.

B. PSPICE Model of the Upside Down Test

The flatness of the insulating layer can have a significant effect on the discharge current. Two effects need to be considered: (1) because of the variation of the capacitance between the phone and the HCP, the total current can change;

(2) the current distribution can change as the areas with locally larger capacitance values will carry higher current. The effect of the capacitance has been investigated in both PSPICE simulation and measurements. Fig. 14 shows a circuit model that allows investigating the effect of capacitance variations between the phone and the HCP. The numerical modeling of the ESD generator is explained by [11]. For the first 5 ns, the HCP is shorted to ground, as the HCP acts as infinite large ground plane during this time frame. Later, the capacitance begins to dominate. Varying the value of the capacitance between the phone and the HCP (C4) from 40 pF to 300 pF affects the discharge current. With higher capacitance, the peak current reaches higher value and decays slower, as shown in Fig. 15. Section III indicated a similar behavior.

C. Comparison with the Measurement

The measured waveform (DUT pressed onto the insulator on the HCP, 8 kV) is compared with the full-wave simulation and the PSPICE result, shown in Fig.16. Both the full-wave and PSPICE simulation results are able to model the discharge current with respect to the peak current, rise time and the 30ns value within 20% tolerance. Thus the model can be used to investigate the aspects in the test setup which can lead to the variation of the current.

V.CONCLUSION

This paper analyzes aspects of the display down configuration for a cell phone in the IEC 61000-4-2 test. The paper shows measurement of linear and nonlinear behavior, including the surface corona which can increase the currents by multiple Ampere. It uses a long known (since 1776) method for visualization of surface discharges to demonstrate for the first time the effect of these surface discharges during upside down ESD testing.

It is further shown that the capacitance between the DUT and the HCP strongly affects the discharge current. This capacitance depends on the flatness of the insulator surface and is often not well controlled. Finally, the simulation of the current distribution in a touch layer obtained by full-wave simulation including the ESD generator, test set-up, cell phone and details of the touch layer, was presented.

The upside down test situation is somewhat unrealistic, as few phones or tablets will be placed on a flat metal surface in a display down position. Besides being unrealistic, the test set-up may also lead to difficult to reproduce results as the capacitance depends strongly on the thickness and flatness of the insulator used on the HCP.

VI.ACKNOWLEDGEMENT

This paper is based upon work supported partially by the National Science Foundation under Grant No. IIP-1440110.

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PB2016.09 ESD to the Display Inducing Currents Measured Using a Substitution PC Board

Download PDF – ESD to the Display Inducing Currents Measured Using a Substitution PC Board

Abstract— ESD to a display may upset or damage the display or the touch circuit. The ESD may have a visible spark carrying current to the frame of the mobile device, to the connecting flex cable, or into the display by penetrating the glue between the glass layers. It may also be a sparkless ESD that causes corona charging on the surface of the glass have currents as high as 10 A. A measurement technique is presented that allows the measurement of the currents on all traces, including ground of flex cables that connect from the display to the main board of a mobile device. The main board is substituted to a PCB that has the same connections to the body of the mobile device and the same shape, i.e., the same electromagenic affects. However, all connections to the display are terminated in resistive structures that allow measuring the currents in the flex cable individually. Beside measuring ESD currents, the substitution board offers various other applications with respect to the coupling and propagation of self-interference causing signals or EMI problems.

Keywords: flex cable, LCD; mobile device; sparkless ESD; substitution board; touch-screen.

I.INTRODUCTION

Electrostatic discharge (ESD) to portable electronic devices can cause hard and soft errors [1]-[3]. Typically in system level ESD testing, the ESD generator is discharged into the exposed metal parts of the DUT. The ESD generator voltage is incremented in steps and system level errors such as perturbation of the display, loss of touch functionality, system reset, etc. are monitored. Various measurement and modeling techniques have been used to study the effect of ESD discharge directly to different areas of the mobile device such as the main board reference ground, clock traces, power pins, metal chassis of the phone, and the LCD display [4]-[8]. The main limitation is that one notices a disturbance or damage to the ICs that connect to the display, but the currents that caused these effects are not known.

Sparkless ESD on the glass surface is the most likely ESD discharge to displays as cell phone design often provides sufficient isolation at the edges such that a discharge into the phone is not possible. These sparkless discharges [9] into an electronic product may also lead to various types of upsets and damages to ICs via induced current flow using any of the multiple coupling paths within the device, as shown in Fig. 1. Sparkless ESD to glass surfaces was studied in [9] and a method to visualize the surface charges using dust figures on the glass after a discharge event was analyzed in [10]. A discharge event on the glass may cause current coupling to the touch screen matrix and then to the traces of the touch controller IC on the flex cable. Similarly, current coupling to the LCD may induce currents to the LCD driver IC. The severity and type of upset/damage depends on the magnitude of the current flow to the sensitive ICs.

 

The measurement technique presented in this paper allows measuring the induced currents at the flex cable connectors on the substitution board due to an ESD discharge on the mobile phone screen/glass. These current values can help to understand the risk of damage to the driver IC or the display IC or disturbances of the data transfer. In some cases, ICs are mounted on the glass or the flex cable. In these cases the method will only measure the current that flows out of these ICs into the flex cable, as the measurement is done on the main board of the phone.

A substitution board is designed and fabricated to replace the main board of a mobile phone. Well shielded 0.8 mm diameter semi-rigid coaxial cables are used to probe the terminated flex traces individually on the substitution board. It must be noted that using multiple coaxial cables for probing also changes the electromagnetic behavior of the device being tested. These cables offer a path to ground. If ferrite clamps are not used on the coax cables, the cables act like a single ground connection similar to a short USB cable that would connect to a well-grounded system. The distribution of currents on the various I/O lines, flex cable shield, ground and power pins is obtained by this measurement technique. A contact mode discharge into a small copper patch on the glass was selected as the excitation because it approximates the sparkless discharges to the display from a current point of view. In contrast to a real arc it still is a linear system, as no arcing is involved in contact mode. We assume that the currents are strong enough to turn on all ESD protection within the ICs that are placed on the glass, such that only their dynamic resistance is visible. Testing at different voltages has verified the assumption of linear behavior.

II.DEVICE UNDER TEST: MOBILE PHONE

A four-layer PCB was designed for a mobile phone to demonstrate the substitution board methodology for measuring individual currents. The features of the phone that influence the electromagnetic behaviour of the phone (such as the main board ground structure, main board-to-phone body contact points, flex cable connector ground contacts, etc.) are identified and reproduced on the substitution board.

The details of the main board, its connections to the LCD and touch flex cables via board-to-board connectors, are shown in Fig. 2. The main board ground structure and its contact points to the mobile phone’s reference ground are shown in Fig. 3.

III.DESIGNED AND FABRICATED SUBSTITUTION BOARD

Based on the dimensions and ESD current flow relevant features of the mobile phone, a four-layer substitution board was designed and fabricated to replace the actual main board of the mobile phone. Fig. 4 shows the layout of the top layer of the substitution board. The board has the following main features:

Similar dimensions and thickness as that of the actual main board.

Similar ground structure and contact points to phone body as that of the actual main board.

Similar ground structure and contact points to phone body as that of the actual main board.

24-pin flex connector receptacle for connection to the LCD flex cable.

10-pin flex connector receptacle for connection to the touchscreen flex cable.

Pads for semi-rigid coax cable probing for all flex connector pins including ground connections.

Pads for resistive terminations for all flex connector pins including ground connections.

The ability to measure the current on the flex shield which is normally connected via a gasket to the main PCB ground.

IV.PROBING CIRCUIT & MEASUREMENT SETUP

Direct probing of the individual traces of the original main board and display flex cables was difficult because of the multilayer board design and thin flex traces. However, the substitution board allowed multiple probing coax cables. The currents in the individual traces of the flex cables were measured using well-shielded 0.8 mm diameter semi-rigid coaxial cables that are soldered on the pads that connect to the flex connector footprint via short (< 1 cm) transmission lines. The currents were measured in two different termination schemes depending on the assumption of the state of the ESD protection diodes on the main board ICs. The signal and I/O lines were loaded with the 50 ohm coax cables when the ESD protection was assumed to be turned off (scenario I). When the ESD protection was assumed to be turned on, the signal lines were terminated with a 1 ohm resistance (scenario II). In both the scenarios, each of the flex cable ground pins/connections was terminated with a 1 ohm resistance. The termination values were chosen as a compromise between the actual loading of the traces, and the ability to measure the currents well. The probing circuit diagram for scenario I and the termination circuit diagram showing all the signal and ground connections of the LCD and touchscreen flex connector are shown in Fig. 5 and Fig.6, respectively.

A photo of the substitution board mounted into the mobile phone’s body including the soldered semi-rigid coaxial cables and the connection of the touchscreen flex cable ground to the substitution board ground via a gasket is shown in Fig. 7.

The measurement set-up used for measuring the currents in the individual lines of the flex cable connectors on the substitution board for a discharge to a copper patch on the glass is shown in Fig. 8. The photo of the measurement set-up is shown in Fig. 9. The mobile phone with the substitution board and soldered semi-rigid coaxial cables is placed, with the display facing upwards, on a reference metal plate using a 1 cm thick Styrofoam spacer. Since the substitution PCB is well grounded by multiple coax cables, the height of the phone above the reference ground is not relevant. The currents were measured for discharges to a 2 cm x 2 cm copper patch on the glass in contact mode for three positive discharge voltages: 1 KV, 2 KV and 3 KV. The different voltages were selected to test the assumption of linearity which is based on the assumption that all ESD protection within the IC on the glass was turned on. As mentioned in the article, the discharge scenario is similar to sparkless discharges to the display [9]. Since there are 29 total coaxial probe outputs, the probe outputs were measured in sets of three. For each set of measurement, three probe outputs were connected to 50 ohm oscilloscope channels using an 8.7 V overvoltage protection device on each channel to limit the maximum voltage on the channel to 8.7 V. The rest of the coax outputs were terminated with 50 ohm each.

The discharge current into the patch was also measured simultaneously using an F65 current clamp, as shown in Fig. 10. The discharge current into the patch in each set of measurement was practically identical. The current clamp output was connected to the oscilloscope channel using a 20 dB attenuator and an overvoltage protection circuit clamping at 8.7 V.

V.RESULTS AND ANALYSIS

The main goal of the current measurements was to understand the relative distribution of currents within the mobile phone and on the various signals and ground connections of the flex cable for a discharge to the glass. The measured peak current magnitudes for scenario I and II on each of the different pins of the LCD and touchscreen flex cable connectors for all three discharge voltages are plotted in Fig. 11-Fig. 12 and Fig. 13- Fig. 14, respectively. As an example, the measured current waveforms for a set of measurements, in scenario I (50 Ohm termination for I/O), at the LCD and touchscreen flex cable connector for +1 KV discharge is shown in Fig. 17. The peak current plots in Fig. 11-Fig. 13 show that the currents in the LCD and touchscreen flex cable ground structures are more than 10 times larger than the currents that flow in the I/O lines while they are about 2-4 times larger for the case when each of the signal lines are terminated with a 1 ohm resistance.

Fig. 14 shows that most (1 A) of the peak patch current flows in the I/O (pin-9) on the touch flex connector when the patch is in the center of the glass. To investigate the dependence of the peak current on touch pin-9, the peak currents were measured for different positions of the patch, as shown in Fig. 15, effectively scanning the discharge location on the glass. The plot of the peak currents on touch pin-9 for different discharge positions on the glass, Fig. 16, indicates strong dependency of the peak current on the discharge location. The peak current magnitudes on the I/O lines might also cause various upset events in the actual system. Correlation of the currents measured using the substitution board to the upsets events on the actual mobile phone was not part of this study. However, the authors hope that the substitution board methodology can be used for such an investigation.

From the current comparisons, for scenario I and scenario II (Fig. 11 – Fig. 14), it can be inferred that the ESD protection turn on can significantly change the current paths within the phone and the current distribution between the I/O and ground pins. To obtain an approximate distribution of currents that flow into the flex cable and to the body of the phone via capacitive coupling after a discharge to the glass, all the measured currents on both the LCD and touchscreen flex cables were summed up and compared with the discharge current into the copper patch. The comparison between the patch current and summation of individual currents and the summation of the absolute magnitude of individual currents for scenario-I is shown in Fig. 18. The peak current magnitude of the discharge current is about 1.6 A and that of the summed-up currents is 1.2 A in scenario I.

VI.CONCLUSION

A measurement technique is presented that allows measuring the induced currents at the LCD and touchscreen flex cable connectors on a substitution board due to an ESD to the glass/screen of a mobile device. The design of a substitution board based on the EMC relevant features of the mobile device and the measurement set-up for measuring the currents on various I/O and ground connections individually was demonstrated. The use of multiple coaxial cables that are well connected to the reference plane presents a similar scenario as that of a mobile device connected by a single wide, short USB or charging cable. The resistive terminations for different lines are chosen so as to emulate the impedance of the actual main board terminations as close as possible. Here, one can change the values depending on the assumed status of the ESD protection at the IC I/Os. Preliminary measurements using the substitution board indicated that a large part of the discharge current flows to the PCB via the flex cables and a smaller part via capacitive coupling to the phone body. The current distribution may be different for different products. In addition, observations of the measured peak current magnitudes at various flex connector pins show that the turn on of the ESD protection circuits at the ICs I/O can significantly change the current paths within the phone. These ratios may be influenced by the status of the ESD protection circuits at the ICs I/O. The current values measured using the substitution board can help to understand damage to the driver IC or the display IC or disturbances of the data transfer and can be used to correlate the current magnitudes to system level effects. The applicability of the substitution board methodology is not limited to mobile devices and can be applied to other electronic products as well.

Besides measuring ESD currents the substitution board offers various other applications with respect to the coupling and propagation of self-interference causing signals or EMI problems.

VII.ACKNOWLEDGEMENT

This paper is based upon work supported partially by the National Science Foundation under Grant No. IIP-1440110.

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PB2016.07 System-Level Modeling Methodology of ESD Cable Discharge to Ethernet Transceiver Through Magnetics

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Abstract—When a charged cable is plugged into an Ethernet connector, a cable discharge event (CDE) will occur. Ethernet transceiver pins are often affected by CDE as they are usually unshielded. The discharge current couples via the transformer and common mode chokes to the physical layer-integrated circuit and may damage it. This paper describes a methodology for CDE system-level modeling in SPICE taking the cable geometry into account via full-wave modeling and cross-sectional analysis. A charged cable model, a nonlinear magnetics model, an Ethernet transceiver pin model, and the traces in the system are combined to create a complete model. An Ethernet system suffering cable discharge was selected to illustrate the methodology. The simulation is compared to measurements.

Index Terms—Cable discharge event (CDE), electrostatic discharge, Ethernet transmission line pulse (TLP), system efficient ESD design (SEED).

I. INTRODUCTION

Cable discharge event (CDE) robustness is a quality issue which network equipment designers should consider. Studies in [1]–[4] directly or indirectly determine the expected charge voltage, and studies in [5]–[7] give examples of possible discharge waveforms for a given voltage. Two CDE-producing situations can clearly be distinguished. The first is through triboelectric charging by pulling a cable over a surface. The authors of [2] reported voltages up to 1.7 kV in a setup that pulls cables from one spool to another while sliding the cable over insulating surfaces. In proprietary industry test standards, the use of 200 m LAN cable charged to 2 kV is suggested. The second scenario can be illustrated as follows. A person carries a laptop that is charged and inserts a LAN cable into the laptop. The voltage levels accumulated by a person can be derived from triboelectric charging by walking, sitting, and standing up from chairs or removing a garment [8]–[10] and can easily reach 10 kV or more.

When a charged cable is plugged into an Ethernet connector, the voltage and consequential current can damage the transformer, common mode chokes, and especially the Ethernet transceivers [1]. Because of the length of LAN cables, CDE discharges can be quite long and have the potential to stress the I/O more than those discharges described by the HBM or the IEC 61000-4-2 discharge model [4]. Most CDE will occur at voltages below 5 kV, leading to shorter rise rimes compared to the 0.85 ns of the IEC 61000-4-2 standard. These shorter rise times may require shorter turn on performance of the electrostatic discharge (ESD) protection circuit.

The electrostatic discharge association is now working on a CDE standard. However, no published CDE standard exits and complying with the system level IEC 61000-4-2 standard may not ensure sufficient robustness of a device or a system against CDE.

In order to characterize interface protection elements, the authors of many publications simulate or experimentally emulate cable discharge with long transmission lines [3]–[7]. The difficulty of creating a CDE standard test is complicated by the many parameters which influence the discharge, such as the charging and discharging mechanisms, pin mating sequence, cable geometry, height of the cable above ground, and the load conditions. In [4] and [11], CDE charging and discharging mechanisms were introduced. In [11], the effects of the pin mating sequence with respect to injecting a common and/or differential mode current were discussed. In [12], some effects of cable geometry were explained by a multibody capacitance model. Previous publications provide a basic understanding of the cable discharges, both from the theoretical and measurement’s point of view [11]– [13]. For system-level investigation, both a cable charging and discharging model need to be included. As many conductors are involved in LAN CDE, the model must be more complex than a single transmission line discharge scenario such as a transmission line pulse (TLP).

The Ethernet magnetic circuit is used to protect against noise, suppress common mode, and to provide galvanic isolation [14] and can come in several different configurations. The failure level of the PHY will depend on this magnetic module [15], which means that this magnetic circuit needs to be modeled correctly to understand its role in protecting the PHY. The performance of the magnetics depends not only on the winding inductances, but also on parasitic parameters such as leakage inductances and interwinding capacitances. In [16] and [17], the authors demonstrate examples linear magnetic modeling for such transformers. However, due to the large currents during an ESD event, nonlinear effects such as core saturation must be considered. Chiefly, the saturation of the magnetic cores can limit the amount of energy which is coupled into the transceiver circuit [18]. This requires a saturable B–H curve-based model [19], [20].

Finally, an Ethernet IC transceiver pin behavioral model is needed to predict its failure level during a discharge [21]. Such a model should be able to reproduce the VI curve behavior such that it can be used in simulation to model the pin [22]. A sudden strong change of the VI curve or an increase of the leakage current measured by a source measurement unit (SMU) is often regarded as an indication for the failure of the DUT [23]. The very fast transmission line pulse (VF-TLP) has been established as the best choice for the characterization of such VI curves and damage thresholds as it can also resolve the DUT behavior in the first nanoseconds of the stress stimulus.

This paper follows the concept of system efficient ESD design (SEED) [24] and uses a cable discharge system as an example to illustrate how to build the complete system-level model. Section II introduces the selected cable discharge system. Each part of the system modeling methods and results are shown in Section III. The models of each part were combined as a system circuit, and the comparison of simulation and measurement results is shown in Section IV. Section V discusses three situations which are not shown in the model. System level saturation situations, CDE versus ESD simulator discharging, and shielded cable influences are discussed in this section. Section VI presents the analysis of this modeling methodology.

II. CABLE DISCHARGE SYSTEM STRUCTURE

As shown in Fig. 1, the selected cable discharge system includes: 1) charged Cat 5 cable; 2) magnetic group with Ethernet connector; 3) interconnection between magnetics and Ethernet PHY IC; and 4) PHY IC transceiver media-dependent interface (MDI) pins. The primary-side center tap of the magnetics is connected to a Bob Smith termination circuit [25] which consists of a 75 Ω resistor and a 1 nF high voltage capacitor. This termination circuit is sometimes implemented using different component values. For example, if power over Ethernet is provided, the capacitor value may be much larger. Furthermore, many center taps from different pairs or even cables may connect together and share the same termination circuit. In this case, the secondary-side center tap is connected to ground through a 1 nF capacitor.

As this paper does not attempt to examine the specific charging processes which can lead to CDE, we simply assume that the cable was charged in common mode based on [2]; i.e., all eight conductors had the same voltage with respect to a ground reference plane. The first pin that contacts initiates a current flow into the LAN connector. This is referred to as a common mode discharge, as the current magnitude depends on the common mode impedance of the cable to ground and the common mode termination impedance on the other end of the cable (open circuit, for an unconnected cable). Although already described in [11], it is important to be reminded of the effect of PIN sequencing during the discharge of an unshielded LAN cable. In CDE, at least two different modes can be initiated by the second pin that mates. The second pin can either be from the same twisted pair as the first pin that contacted, or from another twisted pair. If it is from the same pair, a differential mode current will be initiated and the first pin will be the main return path of a differential current on this pair. In this case, the common mode chokes cannot suppress this differential mode current. Most discharge current will transfer to the PHY IC pins through the magnetics. As the differential discharge case forms the worst case scenario, it was selected as the basis for modeling.

III. MODELING METHODOLOGY

This cable discharge arrangement contains four parts; each part was simulated and tested separately, and then combined in the Allegro Design Entry CIS 16.6 SPICE solver.

A. Charged Cable Model

The charged cable model was built using CST Cable Studio’s hybrid method. The simulator analyzes the cable geometry by cross-sectional analysis and then places it into a 3-D solver to determine the effect of the surrounding on the cable currents. A geometric representation of the four twisted wire pairs (TWPs) of a Cat 5e cable 5 cm above the reference ground plane was first created and then the bundled to create the unshielded twisted pair geometry shown in Fig. 2. Placing a port on each side of all eight wires in the cable geometry results in a 16-port S-parameter matrix which represents the simulated cable. In practice, the wire pairs are twisted more closely together than in the simulated model but we are not aware of a method within CST to create such a closely bundled cable. Because the results shown in Sections III and IV indicate that the resulting error is acceptable, the super twisting of the cable bundle was not considered.

As the next step, the 16-port S-parameter file was converted to a circuit file using a commercial macro model generation tool [26]. This circuit file is suitable for the SPICE simulation as a 32 pin component.

Fig. 3 shows the cable charging and discharging circuit model. To experimentally verify the model, the ES631-LAN Ethernet CDE evaluation system provided by ESDEMC LLC was used. To reflect the inner structure of the CDE tester [27], two cables needed to be modeled. The 5.6 m long section is the external DUT and the 0.4 m long cable section is part of the CDE tester.

The cable charge voltage is set by the initial condition. The cable discharge sequence is determined by the voltage control switch S1 and the termination resistors on the right side in Fig. 3.

Although all wires are charged to the same voltage prior to the first contact, there will be a differential voltage after the first contact. This differential voltage will drive the possibly damaging differential current if the second pin that mates belongs to the same pair. The amount of the voltage depends on the ratio of the well-controlled wire-to-wire capacitance Cww of a pair and the capacitance of the second wire to ground Cwgnd . A simplified capacitive divider is shown in Fig. 4 to illustrate the charge redistribution after the first pin contacts. This is further analyzed in [28]. Measurements show that cables routed in a cable tray may have a capacitance ratio of Cww : Cwgnd up to 1:0.75. Thus, a common mode voltage caused by triboelectric charging of 2400 V will lead to a differential voltage of 1000 V after the first pin discharge.

To verify the cable model, simulated and measured results were compared for second pin discharge cases. The precharge differential voltage of the wire was set to 1 kV, and pin 1 and 2 (see Fig. 3) were shorted together to allow for differential current flow. The discharge current was measured using a CT2 current probe inside the CDE tester.

The results are shown in Fig. 5 together with currents simulated using a simple differential pair model having optimized per unit length parameters. This additional simulation has been performed as other publications have used a transmission line as approximation of the cable discharge pulse. The model consists of two differential lossy transmission lines connected in series. The long transmission line corresponds to the 5.6 m charge cable. Another short differential transmission line corresponds to the 0.4 m cable. The long transmission line was precharged to 1 kV. The switch is placed at the connection point of these transmission lines, similar to the cable model. The lossy transmission lines were defined by their per unit length parameters. In the model, L = 400 nH, C = 40 pF, R = {0.001 sqrt(2 s)}, G = 0 are used. R uses the Laplace variable “s” to model attenuation as a function of frequency. L and C have been derived from the propagation velocity and the characteristic impedance; the loss has been optimized for best match to the full cable model data. One can also use the method mentioned in [29] to create a twisted pair model.

As Fig. 5 shows, the differential currents which determine the discharge currents match well. The frequency of the current waveform oscillation is directly related to the cable propagation velocity and length. In this case, the 6 m total cable length corresponds to a pulse width of 60 ns. The measured data show more damping than the simulated data which is likely caused by additional losses in the CDE tester such as the discharge relays. From a damage point of view, the rise time, peak current, and duration of the first pulse measurement and simulation match.

However, when comparing the simulation using a differential transmission line to the multiwire model and additionally considering practical aspects in test implementation, one will realize that the differential transmission line is only a very good model for one specific case, and it loses generality if other pin sequences are analyzed.

For example, the first pin discharge current strongly depends on the height of the cable above ground; thus, it would require a TLP of adjustable characteristic impedance. A second case which is difficult to model by the differential transmission line is when the second pin to mate is part of a different twisted pair than the first. Experimentally, there is a fundamental difference between using a TLP to discharge to a pin and a differential transmission line discharge. The TLP is usually ground referenced; thus, it requires a high voltage pulse balun to attach the TLP such that a differential current is injected. Therefore, a full LAN CDE tester which has eight individual relays to model the pin mating sequences is preferable.

B. Magnetic Group Model

As shown in [15], the CDE performance depends on the type of Ethernet magnetics used in a product. A typical Ethernet magnetic circuit consists of a center tapped 1:1 isolation transformer and common mode chokes at the cable side and/or the physical (PHY) IC side. In the system investigated, the magnetic group contained three such magnetic components: a three-wire common mode choke at the PHY side, a balanced-to-balanced 1:1 transformer, and a two-wire common mode choke at the cable side (see Fig. 1). The magnetics are made from twisted wires, which form a twisted pair transmission line which is wrapped around a core (see Fig. 6). The 1:1 transformer was selected to illustrate this construction method. The Ethernet common mode chokes were created using the same method.

A linear 1:N transformer model usually contains parameters such as: primary and secondary winding inductance, primary and secondary winding capacitance, core loss resistance, leakage inductance, interwinding capacitance, primary and secondary loss resistance, among other characteristics.

Using a VNA and LCR meter, we obtained the linear parameters. Transformer linear parameter measurement theory and method are described in [30]. By measuring the transformer’s S-parameters, primary winding inductance L1 , primary winding capacitance C1 , core loss resistance RC , leakage inductance L5 , and interwinding capacitance C can be estimated by the equations in Table I. Primary and secondary loss resistance was obtained by measuring the resistance of the primary and secondary winding by LCR meter.

The B–H curve is needed to model the transformer’s nonlinear behavior. A measurement of the primary inductance L1 under different dc-bias currents is used to capture the change of the inductance as a function of dc current. To obtain the B–H curve, the initial permeability μi of the transformer toroidal core was determined from the initial inductance, the core size, and the number of turns (which is obtained from dissecting a transformer).

Allegro Design Entry CIS allows the user to define the magnetic core based on the Jiles–Atherton model [31] by directly importing the measured B–H curve data points to the model editor. Fig. 7 shows the B–H curve of the transformer core and the resultant nonlinear model.

The next step combines the two common mode choke models with the transformer model. The verification was performed in time domain using a TLP as the source (see Fig. 8). An oscilloscope was used to capture the output voltage at 50/100 Ω single/differential load and the input current is measured using a CT-2 probe. As the ac termination provides an additional current path in the real world, it was also added to the test circuit during the verification.

the verification. Fig. 9 compares simulation and measurement results for the input-side currents and the output-side voltages. At low-source voltage levels, the magnetic behavior is linear. The magnetics transfers the TLP pulse to the output side without distortion. However, as the injection source value increases, the nonlinearities begin to manifest. Saturation was first observed when the internal voltage source of the TLP is at approximately 600 V. At the onset of core saturation, the input current rapidly increases while the output voltage drops. Higher charge voltages lead to an earlier onset of saturation.

A comparison of the modeled and measured voltage and current waveforms shows very similar behaviors especially for the peak values and saturation onset time. Some differences are visible on the falling edges which could be explained by variation in material parameters from sample to sample, by the unmolded magnetic hysteresis, or similarly neglected frequency-dependent transformer parameters. Finally, it is known that even within one magnetic, the wire pairs have somewhat different behaviors, potentially due to subtle asymmetries in the geometry which can also contribute to differences between the real-world measurement and highly symmetric transformer equivalent circuit.

From the comparison of the simulation and measurements shown in Fig. 9, it can be seen that 100 ns 600 V excitation pulses inject 3 A into the primary side of the transformer and trigger saturation at 70% of the pulse width. Besides core material and size, the transformer saturation also depends on the secondary signals, but change to much lower impedances once the ESD protection circuits are triggered. Therefore, in order to simulate the system correctly, the transceiver pin impedances need to known side load. In the setup shown in Fig. 8, if the load was changed to 5 Ω saturation appears from 1400 V source voltage. In the application, the transformer is loaded by the Ethernet transceiver pins which provided a 50 Ω input impedance for in-band voltage.

C. Transceiver Pin Model

The PHY IC transceiver pin model consists of a linear and a nonlinear model. According to the VNA measurements, the parasitic parameters such as package inductance and input capacitance are rather small

The nonlinear transceiver pin model was obtained using the ES620 TLP VI-curve system from ESDEMC. Fig. 10 shows the test setup. To obtain the voltage and current waveforms during the first nanoseconds, the time-domain reflection (TDR) method was used [23]. In this method, the current is calculated from the forward and reflected waveforms. In order to distinguish the incident and reflected voltage waveforms, the TLP generator supply pulse width is limited by the length of the low loss coaxial cable which acts as a delay line. Using a 2 m long cable limited the TLP pulse width to less than 10 ns. The voltage at the pin side was measured by a 1 kΩ resistor. To gain direct access to the IC, the Ethernet connector and the magnetics were removed during the VI curve characterization. The PHY IC transceiver pin VI curve was measured in the unpowered state as it was known that this transceiver pin uses a dual diode protection circuit.

The leakage current was measured by the SMU B2961A after each pulse to identify if the I/O structure of the pin was damaged.

The VI curve was measured using an average window from 7 to 9 ns [23]. As the CDE pulse in the system level test is about 50 ns long, an additional VI curve measurement was performed using a TLP having 100 ns pulse length. Here, the average window was set to 70–90 ns. Both measurements yielded similar VI curves indicating that the VI curve of this dual diode-based protection structure is independent of the averaging window.

The VI curve was modeled by voltage-controlled switches, ideal diodes, and resistors where the resistors and switches were used to set the VI characteristics and the ideal diodes separate the positive and negative injection behaviors. Fig. 11 compares the IC transceiver pin modeling and measurement result. As expected in a dual diode protection, the turn-on voltage is about 0.7 V if not powered, and the curve is symmetric with respect to polarity. The diode’s dynamic resistance is about 0.4 Ω after turned on. Applying 1.6 V Vdd IC shifts the positive VI curve branch shift by 1.6 V.

Changes in leakage current are generally used as an indication of whether the IO pin has been damaged. During VF-TLP (10 ns pulse width), the leakage current was measured after each pulse by applying 1 V dc to the pin. The leakage current did not change. It remained at 300 μA for currents up to 40 A. Using a 100 ns wide pulse damage was observed at 23 A as indicated by an increase of the leakage current from 300 μA to 10 mA.

D. Traces and Other Influencing Factors

The traces between the Ethernet connector and PHY IC pins form a differential transmission line. Using a TDR, the trace length and impedance were determined. It is important not only to consider the inductance formed by the common mode choke, but to consider the fact that the common mode choke is made by winding a TWP around the core. Its electrical parameter also had been determined using a differential mode TDR. The effect of the pair is modeled as T1 and T2. Fig. 12 gives details of the traces and common mode choke transmission line modeling structure.

IV. SYSTEM-LEVEL MODELING RESULT

The model was completed by combining the cable model, the magnetic model, the interconnection, and the IC model. Fig. 13 compares the measured and simulated results for the second pin (pin 1) discharge case. A differential voltage of 1000 V was used and the current waveform was measured at the I_probe branch (see Fig. 3). The voltage waveform was measured at the MDI+ pin via a 1 k resistor, corresponding to the voltage at PHY-side node of inductor L3 (see Fig. 12).

Voltage overshoot and ringing is visible at the waveform shown in Fig. 13. For small signal levels, the PHY IC terminates the differential pair into 50 Ω to ground. However, if the signal levels are large enough to turn on the ESD protection of the PHY IC, the signal is reflected by the low dynamic resistance of the ESD protection (about 0.4 Ω). The ringing is caused by this reflection and the traces and inductances between the IC and the transformer.

V. DISCUSSION

A. Transformer Saturation

The first aspect to discuss is the effect of saturation of the transformer core and the common mode chokes. The chokes will not be saturated by differential signals, but long pulses or high current levels will saturate the transformer. This effectively reduces the IC current, protecting the IC. The transformer investigated began to saturate at 3 kV if a 5.6 m cable was used. Using a 25 m cable, saturation was observed above 1 kV (see Fig. 14). The saturation onset occurs at rather high currents which are caused by the low dynamic impedance of the ESD protection circuit (0.4 Ω). The large current in the secondary winding partially cancels the flux caused by the primary winding and in this way, preventing core saturation. As the saturation is reducing the current in the ESD protection, it is important to model saturation for predicting the CDE robustness of the system.

B. Comparing CDE to IEC 61000-4-2 Contact Mode Discharge

As CDE test equipment [32] is presently not widely available, it is common practice to test the robustness of equipment against CDE by using an IEC 61000-4-2 generator in contact mode. The IEC 61000-4-2 ESD generator is discharged to individual pins of the connector while the other pins are left unconnected. Simulations using the proposed model help to clarify the differences and similarities between a dedicated CDE tester and an ESD simulator.

As shown in Fig. 15, the ESD generator directly discharges to a LAN connector pin. The current flows via the common mode choke, and one half of the transformer to the 75 Ω – 1 nF termination circuit. This current, and the resulting voltages at the Ethernet PHY IC are compared to a discharge from a LAN cable in differential mode, i.e., to the case in which the second pin which contacts belongs to the same pair.

Here, an ESD generator charge voltage of 4 kV is assumed. For the discharge of the LAN cable, 1 kV differential voltage is used for the simulation. The ESD generator circuit model is taken from [22].

Comparing the CDE tester to the ESD generator shows clear differences between the measured current and voltage waveforms (see Fig. 16). The data indicate that a 1 kV CDE differential (second pin) discharge causes a peak current value of approximately 15 A, which is similar to the peak current caused by an ESD generator charged to 4 kV and discharged to the pin in contact mode.

The pulse lengths cannot be directly compared as the CDE pulse depends on the length of the LAN cable length. A 1:4 voltage ratio approximately matches the peak current which can be estimated by simply analyzing the impedance ratios. The CDE differential discharge has a source impedance of about 100 Ω (LAN cable); the approximate source impedance of an IEC 61000-4-2 generator can be estimated from the requirement of having 3.75 A/kV peak current which leads to about 266 Ω. Further, the 75 Ω of the ac termination must be included for the ESD generator discharge leading to an impedance ratio of 100:341. However, the fundamental difference in the return current path should not be overlooked. First, the second pin discharge of a LAN cable drives a differential current, which passes unaffected through the common mode chokes. In contrast, the ESD generator discharge current is not compensated within the common mode choke; thus, the choke will partially suppress the current up to the point of saturation.

An additional difference results from a large variation in circuit implementation of the ac termination circuit which carries the bulk of the return current when an ESD generator is used for testing. In this case, the circuit is implemented by a 1 nF capacitor and 75 Ω resistor connected in series from the transformer center tap to VSS. Because the connection method and component selection for this termination circuit varies strongly between products (e.g., multiple center taps may be connected to one termination, varying RC values, or a simply nonexistent termination), the ESD generator can see significantly different load impedances which are unrealistic during real CDEs. Therefore, it is recommended that IEC 61000-4-2 compliant generators not be used for evaluating the CDE robustness of the Ethernet front-ends.

C. Shielded LAN Cables

Cable discharge of a multiwire cable is a complex situation and the current depends on many parameters, such as the mating sequence, the distance of the cable to ground, the charge voltage and the response of the different linear and nonlinear components inside the product. If the cable is shielded, additional parameters need to be considered. If the cable is charged by applying a voltage to the shield and the shield contacts first, a discharge will occur between shield and the system ground. In this case, the discharge is not likely to cause damage, as the voltage between the shield and the wires would be very low. However, the quality of market sampled cables varies strongly. The best cables use both a foil and a braid and connect them well to the connector shield. However, some “shielded” cables have no shield at all, and some use only a rather resistive foil which does not make reliable contact with the connector. Thus, an analysis of “shielded cables” would have to include a discussion on the quality of the shield implementation-based cables sampled from the market.

VI. CONCLUSION

This paper introduced a system-level modeling method for the electrostatic discharge of LAN cables. An Ethernet-connected system was chosen to illustrate the modeling method. Four main parts are included in the simulation model: charged cable, transformer and common mode choke arrangement, including saturation, traces in the system, and the nonlinear response of the Ethernet transceiver’s ESD protection circuit. The pins of the connector connect in a random sequence. A differential mode discharge will occur if the first and the second pin which contact are from the same twisted pair. This connection sequence may lead to the worst case discharge. This differential mode current can damage the physical layer-integrated circuit. It is further shown that the saturation of the transformer can help to protect the IC, and that testing for CDE robustness by using an IEC 61000-4-2 generator is not a good substitute for a CDE tester as the return current path for the IEC 61000-4-2 testing does not match the current path of the differential discharge. The methodology proposed in this paper provides a step toward a complete SEED simulation of LAN cable discharges.

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TR002 PV Module Diodes TLP Test Report

SEM image of die surface from ESD damaged PV bypass diode sample, melted metal and silicon observed

Download or View in PDF: TR002_PV Module Diodes TLP Test Report

Bypass and blocking diodes inserted across the strings of the solar panel arrays are found to be susceptible to potential electrostatic discharge (ESD) events. The objective is to explain the theory behind the ESD damage and the proper test and analysis methods for ESD failure of PV module diodes. To demonstrate the proposed test methodology, some diode models supplied by a solar panel arrays manufacturer were evaluated.

 

by Wei Huang, Jerry Tichenor, Yingjie Gan, David Pommerenke,

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PB2016.02 ESD Failure Analysis of PV Module Diodes and TLP Test Methods

Download PDF – ESD Failure Analysis of PV Module Diodes and TLP Test Methods

Bypass diodes inserted across the strings of the solar panel arrays are essential to ensure the efficiency of the solar power system. However, those diodes are found to be susceptible to potential electrostatic discharge (ESD) events in the process of solar photovoltaic (PV) panel manufacture, transportation, and on-site installation. Please refer to [1], where an International PV Module Quality Assurance Forum has been set up to investigate PV module reliability, and Task Force 4 has been setting guidelines for testing the ESD robustness of diodes used to enhance PV panel performance.

This article explains the theory behind the ESD damage and the proper test and analysis methods for ESD failure of diodes. To demonstrate the proposed testing methodology that follows, we will be evaluating six different types of diode models as supplied by our customer, who manufactures solar panel arrays.

BACKGROUND

Bypass and Blocking Diodes in Solar Panel Arrays

To help maintain the efficiency and performance of solar panel arrays it is common for bypass diodes to be inserted across individual PV panels, and blocking diodes to be inserted in series with a string of panels that are used in a parallel array (see Figure 1). The bypass diodes provide a current path around a shaded or damaged panel. If these are not installed, the panel will act like a high impedance load when shaded. This effectively reduces the series string output as the current produced by the remaining series connected panels will be forced to go through the shaded panel, thereby reducing the voltage output of the string.

If the bypass diodes are installed, and one of them fails due to ESD, it typically fails to a short circuit. When this happens (see Figure 2), the shorted diode does not allow any power produced by its panel to enter the system, thereby lowering system efficiency. Blocking diodes keep current from the battery pack, or a parallel panel string from entering a damaged string. This is important at night when the panel array cannot provide any power, thus providing a path for the battery to discharge. When installed, the blocking diodes may have leakage current on the order of nano- or micro-amps. However, if they fail due to ESD, they typically fail to a short circuit providing another path for the battery to discharge. This discharge current can be milli-amps or amps. (See Figure 3 for an example of this failure scenario.)

Failure of even one of these diodes in the field is very expensive for companies to replace due to the need for a qualified service technician, as most installations will require code requirements to be met. Continued operation of the panel array with a damaged bypass or blocking diode will, at best, hamper the array’s efficiency and, at worst, cause permanent damage as it consumes power rather than produces power. It has been proposed that the damage to the diodes is caused by ESD stress.

What is ESD and how it damage the solar PV module diodes?

ESD is the sudden flow of electricity between two electrically charged objects caused by contact, an electrical short, or dielectric breakdown. Electrostatic discharge stress can occur in many forms and, depending on the characteristics of the stress, can damage different parts of solar PV module subjected to the stress. In particular, there are several ESD models with industrial standards that describe the pulse shape, source impedance, and determines levels at which the device should survive.

The commonly used ESD models (Table 1) are the Human-Metal Model (HMM) (IEC 61000- 4-2 for system level ESD testing or ANSI/ESD SP5.6-2009 for component level ESD testing), the Human-Body Model (HBM) for component level ESD testing (ANSI/ESDA/JEDEC JS-001-2014), and the Charged-Device Model (CDM) for device level ESD testing (ANSI/ESDA/JEDEC JS-002-2014). There is also the Machine Model (MM), but it has been discontinued due to poor repeatability. Further, a new ESD model that currently has no established industrial standard, but has a different damage effect is the Cable Discharge Event (CDE).

Human Metal Model (HMM)

The human-metal ESD can take place when a charged person holding a pointed metal object, like a screwdriver or a ballpoint pen, rapidly moves the hand against an electronic device. In regard to PV module bypass and blocking diodes, this type of ESD events would most likely occur during junction box assembly with metal tools like tweezers, pliers, or screw drivers, etc. Figure 4 demonstrates a HMM event between a screwdriver and a screw that is part of an electrical installation in the junction box.

Human-Body Model (HBM)

Human-body model simulates the transfer of charge from a human to a component, such as through a fingertip as a device is picked up. This model is one of the most commonly used ESD tests for component qualification. In regard to PV module bypass and blocking diodes, this type of ESD event would also most likely occur during junction box assembly, especially if the operator picks a diode and mounts it by hand into the junction box. Figure 5 demonstrates a personnel picking up a PV module diode with bare fingers.

Charged-Device Model (CDM)

Charged-device model simulates the transfer of charge from a device to ground. A device can collect charge by sliding across a surface and then discharged by contact to a metal surface or ground. In regard to PV module bypass and blocking diodes, this type of ESD event would most likely occur during junction box assembly.

Transmission Line Pulse (TLP)

The TLP technique is based on charging a transmission line to a pre-determined voltage, and discharging it into a device under test (DUT). The cable discharge emulates an ESD event that has better defined RF signal path, controllable rise-time, and pulse width. The test setup allows transient current and voltage waveform to be monitored. Therefore, the change of the DUT impedance can be monitored as a function of time in ps details. The DUT performance degrade or failure check can be automated with RF high voltage switch and help the system with faster ESD performance analysis. Regarding to the PV module diodes, this model is not a real-world event as the transmission line would not be well defined as the TLP model, but the type of waveform is relatively similar to cable discharge events (CDE) during the PV module on-site installation process.

Cable Discharge Event (CDE)

A cable discharge event is a frequent real-world electrostatic discharge event that occurs when a cable is connected onto a device and the cable has existing charge prior to making the connection. This can also happen by connecting a charged cable (open on one end) to a device. It occurs because there is a potential differential between the charge on the cable to be connected and the device. The resulting waveform is highly dependent on the real-world current return path and specifications of the cable.

However, these events usually have a fast rise time of less than 500ps, potential for high current that can reach over 100 Amperes, and a potential long pulse that can be several µs if the discharging cables are long. The fast rise time, high current, and long pulse duration can result in a permanent performance degrade or physical damage of device being subjected. Regarding to solar PV module, the cable connections between the panels can be very long, resulting the ESD current waveform could be very different from all previous cases. Because cable connection is an avoidable on-site installation process, cable discharge event should be treated as a special ESD case with special test setup for the PV module diodes quality assurance.

Although these ESD models describe how an ESD stress event may originate, the underlying physics of these models point to two basic damage causes. Damage may occur as the device cannot withstand the extremely fast voltage transient, or a device is not able to handle the current or the heating caused by the current. Here, the heating occurs within nanoseconds, such that there is no thermal exchange with the surrounding. Further, the current distribution within the conduction area of the device may not be homogeneous, such that local melting (“filament creation”) leads to damage at current levels that the device could handle, if the current would flow with equal current density in the device.

The CDM model is used to qualify a device for the first of these damage types in that a very fast rise time as 100 ps with a short duration pulse. This test can determine if the gate oxide layer of a component is susceptible to a CDM type of event. The HBM model is used to qualify a device for the latter of the damage types in which a long duration (100ns) pulse is applied. The HMM, CDE and TLP models could possibly contain both types of damage. However, the CDE or TLP type of model would result in the worst possible damage in all of the cases discussed above.

An example of damage to the semiconductor components is shown in Figure 7 which illustrates burn track damage on a PV bypass diode caused by ESD.

THE TRANSMISSION LINE PULSE TEST METHODOLOGY

Given the nature of how the bypass and blocking diodes could be exposed to and damaged by ESD events, the worst case that would be the cable discharge event, in which both fast rise-time and high energy pulses occur during the installation process. Therefore, based on the existing industrial ESD testing methods, we propose to use the transmission line pulse test method that does not necessarily replace the IEC 61000-4-2 standard, which may have been be used in the current qualification process. Instead, the TLP test method subject a diode (a low resistance DUT) to a faster rise-time and higher energy pulse up to 180A (pulse reflections being allowed to approach the real-world CDE case). This provides a fully-automated device ESD performance characterization system for transient IV signal and degrade/failure inspection before and after each pulse. Compared to the other types of ESD models, the advantages of using a TLP test are:

Well Defined Consistent Waveform Shape: Both circuit and waveform defined in ESD simulator standards are too flexible (no impedance control for test path, 30% tolerance at only certain time) This causes ESD simulators to provide very different ESD test results between different test sites. A TLP pulse is very clean and consistent.

Highly RepeaTable Test Setup: Fatigue from holding ESD simulator by hand can lead to inconsistent test setups. In TLP testing with jigs for mounting the DUT, a more controlled test is obtained.

Fast Automatic Measurement and Reporting: Typical TLP testing is done with full automatic control of oscilloscope scale adjustment, voltage pulsing, failure criteria checking, and IV curve update.

Important Device Behavior is recorded for ESD analysis and design: Many useful parameters can be extracted from TLP tests for device transient behavior analysis, modeling and system-efficient ESD design (SEED). Traditional ESD tests only generate pulse for pass/fail results.

Test Setup

The TLP test setup is shown in Figure 8. A transmission line pulse (TLP) generator provides a rectangular voltage pulse by charging a 50Ω transmission line to a test voltage, and discharging the pulse to the DUT by a special relay which can withstand the voltage, and can switch to an on “on” status without bouncing. The pulse then travels out of the TLP through a coaxial transmission line where it first reaches a high voltage relay (A621-HVLKR).

This relay is capable of withstanding up to 10kV, and is required for the high current TLP testing used with these high power diodes. The relay provides a means of transferring connection of the DUT between TLP measurement system and the failure detection system. In particular, during TLP pulsing, the relay connects the DUT to the TLP, the measurement probes, and the oscilloscope. After each TLP pulse test waveform has been captured, the system switches the DUT to the SMU to measure the diode reverse leakage current at maximum recurrent peak reverse voltage (VRRM). The A621-LTKSEM leakage test module also helps to facilitate these connection changes on the low voltage side of the measurement probes.

The DUT current is measured indirectly using a resistive tee to voltage measurement. The current is recovered by the overlapping reflection method. This method measures both the current through and the voltage across the DUT, but for lowresistance devices, such as a diode in the “on” state, this method is not well suited for measuring the device voltage. Instead, the DUT voltage is measured directly at the device, providing a highly accurate voltage probing measurement. The current measurement is performed by first measuring the pulse as it passes by the first pickoff resistor that goes to Ch1 of the oscilloscope. A short delay later (as determined by the length of coaxial cable between the pick off resistors), the pulse reflected from the DUT is measured at the same pick off resistor yielding an overlapped waveform. Using transmission line theory and a pre-measurement calibration pulse, the current into the DUT can be determined as:

Where V+, V- , and Zo are the incident pulse, reflected pulse, and characteristic impedance (50Ω) of the transmission line system, respectively.

Test Procedure

The test procedure is demonstrated in the flowchart shown in Figure 9. Upon entering the test loop, the system measures the leakage current of the DUT to obtain the initial degrade measurement. Next the TLP charge voltage is set. For the testing reported in this article, the charge voltage was set to sweep from 500V to 9600V, in 100V increments. For the first test point, the oscilloscope scale and trigger level are set based on the initial charge voltage and a 50Ω DUT. As testing progresses, the scale and trigger level are set based on if the waveforms clip, or is under scaled. If the waveforms do not clip or are not under scaled the settings are kept.

After setting the oscilloscope parameters, the DUT is pulsed and the captured data is compared to the oscilloscope display range for each captured channel to check for clipping and whether the scale is appropriate. If any of the waveforms are clipped, the scale is adjusted and the DUT is pulsed again. If the waveforms are ok, or under scaled, the data is accepted and processed. Any under scaled waveform corrections are made on the next pulse level. Processing is completed by scaling the data by the measurement attenuator and probe values.

Another DUT degrade/failure measurement (measure the PV diode leakage current under reverse working voltage) is made to determine if the DUT has failed or not. If failure occurs, the test is stopped. If. If not, the next pulse point is performed. This repeats until all pulse points are done, or failure occurs.

Dynamic IV Curve Measurement Principles

One of the goals of the measurement system described above is to obtain the dynamic IV curve of the DUT over the voltage range pulsed. Current and voltage waveforms resulting during pulse test are demonstrated in Figure 10. The dashed lines near the end of the pulses represent the start and stop points of the dynamic IV measurement window.

The measurement window is typically 70 to 90% range of the pulse but other ranges can be selected. Over this window, the average value of the time waveform is taken as the current and voltage, respectively. This value is then plotted for each voltage pulse applied.

Degrade/Failure Measurement (Leakage Current Measurement)

The leakage current was measured using the source meter unit (SMU) and, depending on the diode tested, the bias voltage was varied between two and three different voltages with the maximum bias voltage set to the maximum recurrent peak reverse voltage (VRRM) for each diode. The VRRM voltage is listed in each individual diodes datasheet.

Also, for the results reported below, for any diode that failed the leakage current upper limit was set to 2.5mA (a value that is very high and can be treated as failure criteria). This is the compliance limit of the SMU and is not an indicator of diode characteristic after failure, other than they appear to fail to a short.

SOLAR PV MODULE DIODES TESTS

Over the years, ESDEMC Technology has tested several diode models for solar PV module companies. The VRRM (from device datasheet) of the diodes are listed in Table 3. The VRRM values are important because they provide the maximum bias voltage applied to the diode for leakage current measurement. This value is supplied by the device manufacturer, and is typically found in their respective datasheets.

In the following sections, the test results will be presented in terms of the best performer to the worst performer in regard to diode failure during TLP testing.

Sample Set #5

Out of the 80 devices we tested in Sample Set #5, no failure occurred. The dynamic IV and leakage current curves for three samples are shown in Figure 12. The dynamic IV curve is read from the Y-axis to the bottom of the X-axis, and the leakage current from the Y-axis to the top of the X-axis. Note that the top of the X-axis is logarithmic due to the dramatic change in leakage current once a device fails to a short circuit.

Sample Set #3

The next best performers were the devices in Sample Set #3, which had only one diode fail out of one hundred units; failure occurring near the last few test pulse levels. The dynamic IV and leakage current curves are shown in Figure 14. Once the diode failed to a short, the resulting leakage current was at the compliance limit of the SMU, and is not an indicator of the diode condition.

Sample Set #6

Sample Set #6 had eleven failures out of eighty diodes tested. The minimum, maximum, and average pulse current for each of them are listed in Figure 25, and the dynamic IV and leakage current curves, for three of the failed diodes, are shown in Figure 16.

Sample Set #4

Sample Set #4 had 18 devices fail out of 100 tested. The dynamic IV and leakage current curves, for three of the failed diodes, are shown in Figure 18.

Sample Set #2

All of the diodes in Sample Set #2 failed. The minimum, maximum, and average pulse current for each of them are listed in Figure 25, and the dynamic IV and leakage current curves, for three of the failed diodes, are shown in Figure 20.

Sample Set #1

All of the diodes in Sample Set #1 failed. The minimum, maximum, and average pulse current for each of them are listed in Figure 25, and the dynamic IV and leakage current curves, for three of the failed diodes, are shown in Figure 22.

CONCLUSION

Of the diodes tested, only those in Sample Set #5 did not have failure up to 200 Amp or 10 kV of the eighty diodes tested. The next best performer was Sample Set #3, which only had only one failure, and that particular diode failed near the last few test pulses (100 diodes tested). Sample Set #6 had ten diodes fail out of eighty tested, and the Sample Set #4 had eighteen diodes fail out of one hundred tested. The worst performers were those in Sample Sets #1 and #2, where all diodes failed (all diodes tested failed for both models).

The chart shown in Figure 25 depicts the minimum, maximum, and average pulse current at failure for the diodes that failed.

It has been suggested that it is not necessarily the diode design type that determines if the diode is more or less susceptible to ESD stress, but instead a result of quality control of the manufacturing. For example, the process may be as follows: a diode as the 15SQ100 (tested data is now shown herein) is being checked in quality control after manufacturing. Its reverse breakdown voltage is checked. If it does not pass 100V, but passes 50V, it is re-labeled as a 15SQ050 model. This may not guarantee that the 15SQ50 model is a higher quality 050 design, and may instead be a poor quality 100 design relegated to the 050 model line. Here, the problem is that the diode may not hold 100V reverse voltage due to a local defect. The local defect will concentrate the current during ESD into a very small area and cause the diode locally to melt. Thus, the robustness of such a diode is much worse than a diode that passes the 100V reverse voltage, which may indicate that it does have few, and less severe local defects.

According to our customers (solar solution providers), our findings on the diode failure rate, through TLP test methodology, correlates to their field return failure rate. Therefore, we recommend that TLP testing be performed for all solar PV module diodes. In addition, it may be in the best interest of both solar PV module and diode manufacturers to investigate the quality control of the diodes selected, yielding a more reliable design for field use.

Read more: http://incompliancemag.com/article/esd-failure-analysis-of-pv-module-diodes-and-tlp-test-methods/#ixzz45fk4HnPT

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PB2015.12 System-Level Modeling for Transient Electrostatic Discharge Simulation

Download PDF – System-Level Modeling for Transient Electrostatic Discharge Simulation

Abstract—This paper introduces an improved electrostatic discharge (ESD) system-level transient simulation modeling method and discusses its validation using IEC 61000-4-2 ESD pulses on a real-world product. The system model is composed of high current and broadband (up to 3 GHz) models of R, L, C, ferrite beads, diodes, and integrated circuit IO pins. A complex return path model is the key to correctly model the system’s response to the IEC excitation. The model includes energy-limited time-dependent IC damage models. A power–time integral method is introduced to accurately determine if a junction would experience thermal runaway under an arbitrary injection waveform. The proposed method does not require knowledge of the junction’s microscopic geometry, material information, defect location, or melting temperature.

 

Index Terms—Common mode, electromagnetic compatibility (EMC), electrostatic discharge (ESD), human metal model (HMM), IEC 61000-4-2, system efficient ESD design (SEED), transmission line pulser (TLP).

I. INTRODUCTION

Recent studies have shown that system-level electrostatic discharge (ESD) simulation can serve as a powerful tool for analyzing ESD performance [1]. The simulation enables the design of reliable protection on the first attempt and avoids the need for repeated design optimization tests.

The concept of ESD simulation has been promoted as an option in system-level ESD efficient design (SEED) [2]. SEED emphasizes the analysis of the interaction between the quasistatic I–V curve of a vulnerable pin and the pin’s external protection. Gossner et al. applied SEED for analyzing an IO pin’s response to ESD for different on-board protection solutions [3]. Monnereau et al. extended the modeling framework by adding trace and package models, and validated their method with an inverter circuit under a 100 ns transmission line pulser (TLP) excitation [4]. Li et al. previously published a hard error analysis of a cellphone’s keyboard illumination circuit based on a 35 ns TLP source [5]. Orr et. al used similar method to characterize IC pins [6].

Although the SEED simulation offers greatly improved system-level ESD design, some issues remain unresolved. A TLP-excited system simulation may not substitute IEC/HMM [7] excited analysis in certain cases. TLP-based simulation results may be valid when the damage is caused by the IEC’s second peak (residue portion), which has a long duration and can be mimicked by a TLP pulse. It does not reflect the consequences of the first few nanoseconds of an IEC excitation. In addition, as an IEC waveform passes through a complicated system, the resulting injection on a vulnerable part could be in an arbitrary shape and, thereby, break a fixed empirical HMM-IEC relation [8]. A TLP source is not suitable for modeling soft error, near-field coupling or signal integrity (SI) problems caused by an ESD injection. Due to the above reasons, many researches have moved forward to perform ESD transient simulation under IEC/HMM excitations [9]–[13].

It is difficult to convert a TLP-based simulation into an IEC setup directly by substituting the TLP model with an ESD gun model, based on a real product system. Compared to a TLPbased model, an IEC source-based setup requires more sophisticated modeling on the current return path in order to achieve an accurate circuit response under ESD tests. Furthermore, intensive use of flex-printed circuits (FPCs) for connecting multiple PCBs creates complex return paths. Among the recent publications that researched system-level IEC simulation, some showed less accurate results compared to measurement, especially at the very first nanosecond, e.g., [11]. Some demonstrated excellent modeling results, but the investigated problems were only at the PCB level rather than the real product level due to the lack of complex return path structures, e.g., [12] [13].

In addition to modeling the PCB-based and IC internal ESD protection structures, a failure criterion is needed. Using only a TLP-derived constant failure, current threshold [13] may be insufficient if this threshold is only surpassed for a few nanoseconds. This will be the case if the initial peak of the ESD current surpasses the threshold but the second peak remains below it. As Notermans et al. concluded in [8], “For a real system, dynamic failure must be taken into account as well.” Particularly, it will be shown later in this paper that a complex network could introduce an oscillatory current waveform inside the system, thereby making a constant current threshold inapplicable. The dynamic failure according to junction overheat was investigated by Wunsch and Bell [14], who characterized the failure model with the tested pulse–power relationships. Later, several researchers such as Yiquan Cao, applied the thermal failure model in ESD scenarios [15].

In the study presented in this paper, we modeled a cell phone circuit in realistic IEC testing scenarios. The state of the art of this paper includes the following four parts. First, typical components (R, L, C, ferrite beads, and semiconductor devices) under high-current and high-frequency excitations are modeled. Second, a detailed model of the complex return path inside the phone is presented. Finally, a time-dependent destruction model and power–time integral method is introduced to accurately determine if a junction would suffer thermal damage under an arbitrary injection waveform. The checking algorithm is an extension to Taska’s work [16].

The remainder of this paper is organized as follows. Section II describes the product under investigation. The test systems and methods for creating the model are introduced in Section III. The component models are shown in Section IV. Section IV presents the semiconductor’s failure model and discusses the development of the thermal runaway criterion of a junction under an arbitrary waveform. Section VI mainly discusses the ESD gun model and common-mode path modeling. Section VII shows the validation of the system-level model and the model’s application for hard error analysis.

II. SYSTEM UNDER INVESTIGATION

A vulnerable keypad backlight LED circuit in a smart phone, as shown in Fig. 1, was investigated. The driver IC controlled the LED’s brightness by varying the IO pin’s state. All component information will be kept confidential because of intellectual property constraints. ESD tests indicated that the LED was a sensitive zapping point. During product-level tests, airmode discharge sometimes struck through the aperture between the plastic buttons that covered the LED and coupled into the illumination circuits.

At first glance, the circuit’s behavior under ESD appeared somewhat complex for the following reasons: 1) L–Cpairs could cause resonance; 2) ferrite beads and capacitors may saturate or show nonlinear behavior under high-current injection; and 3) the keyboard PCB was connected to the main PCB through an FPC, which introduced a complex return path for the ESD current.

III. MODELING METHODOLOGY

A component model was created based on an RF model and a device model obtained under high current, as shown in Fig. 2. This combination ensures sufficient accuracy under IEC 61000- 4-2 or HMM excitations. Based on the 0.7–1 ns rise time and the response of nonlinear elements, a modeling bandwidth of 3 GHz was selected. Z-parameters were used to obtain the RF model.

The high-current I–V curves were extracted using a 1540 ns adjustable TLP pulse (see Fig. 3), which is long enough to extract a stabilized result yet avoid damaging the DUT. To control the parasitics of the test setup, inductances were minimized, e.g., a circular arrangement of five 10-Ω resistors was used to create a broadband 2-Ω current measurement shunt.

IV. COMPONENT MODELS

A. Semiconductor Devices

Similar measurements were used to determine the VI behavior of LEDs, Zener diodes, and IC pins. The only difference was that the IC was powered to ensure the same operating conditions as those encountered during system-level testing.

The Zener diode’s transient I–V curve appears in Fig. 4, as does a behavioral model developed by fitting this curve. Diode 11 defined the I–V characteristics of the Zener diode under negative pulses applied to its cathode; diode 10 and the switch (actually, a voltage controlled resistor) determined the positive I–V characteristics. Diode 9 was used as a unidirectional switch to separate the positive and negative pulse injections.

The capacitance of the Zener diode was measured using a vector-network analyzer (VNA). Due to its large value of 25 pF, it was determined that the diode would carry most of the current during the first nanoseconds of the ESD pulse.

The LED model (see Fig. 5) is based on a similar concept. It has two parts: the factory-provided SPICE model for nominal current conditions, and two voltage-controlled resistances to mimic the high-current I–V behavior. The factory model already included the capacitance, so no external RF model is needed here.

The IO pin on the driver IC was modeled as a three-terminal device. First, a TLP was used to obtain the power clamp of the Vcc network (Diode 3 in Fig. 6). Then, the high-side (DIODE1) and low-side (DIODE2) protection diodes of the IO pin were measured by applying positive and negative pulses to the IO pin, respectively. Finally, using a VNA, the values of the linear components (C, R, and C33) were derived. The 300-pF-power rail capacitor is a combination of junction, gate, and metallization capacitance. The system contains a large 2-μF on-board capacitor placed in parallel.

B. Capacitors, Ferrite Beads, and Inductors

The voltage across a capacitor may lead to sparking, capacitor breakdown, and a recoverable change in the capacitance value [18], [19]. Fig. 7 shows the voltage and current of a 10-V-rated 10-nF X7R capacitor that was excited with a 15 ns 3 kV TLP. Although the charge current was constant, a nonlinear voltage increase occurred. This indicates that the capacitance decreased as the voltage increased. The capacitance variation over time, or C(t), can be calculated from the measured voltage and charging current waveform

The C–V behavior was approximated by an arc–tangent function (2) to account for this C–V behavior, although other researchers have shown that quartic functions can work equally well [20]

where A–D tune the model, as shown in Fig. 8. For this specific capacitor, the best match was achieved at A = 18, B = 2.2, C = 2.8, and D = 7.

Using the arc–tangent function, together with equivalentseries-resistance and equivalent-series-inductance obtained from measured Z-parameters, a complete capacitor model can be created in Agilent’s Advanced Design System [21].

Not all capacitors behave nonlinearly under ESD. The low dielectric constant of NP0 ceramic will show little or no nonlinearity; however, the low capacitance values achievable with small-package NP0 capacitors may spark over.

Similar to capacitors, ferrites may exhibit saturation or other nonlinear behavior under high-current conditions. The nonlinear inductance can be approximated using the following:

In certain cases, the additional high-frequency noise on the measured I(t) may cause dI/dt to change significantly, thereby interfering with the calculated L(t). To calculate the L(t), one could either perform low-pass filtering on the tested raw data, or use


 V (t)dt I (t) to calculate.

The inductance–current relationship can be modeled by a nonlinear arc–tangent function, as used in capacitor modeling. Here, we used an alternative method, a quartic equation, for modeling

where I stands for the current flow through the nonlinear inductor; L0 is the initial/nominal inductance; and Lsat represents the saturated inductance. A = 2 and B = 1 for the specific ferrite we tested. Fig. 9 shows the modeled curve of a ferrite with an equivalent 60-nH inductance that can be saturated to 20 nH.

The complete model of the ferrite appears in Fig. 10. Besides the nonlinear inductance model (SDD1P), other linear models can express the effect of the capacitance and loss following Yu’s topology [22]. These linear parts usually can be found in a device’s datasheet and can be checked by measuring the S-parameters. This model does not take hysteresis into account because the ferrite bead uses soft magnetic materials that exhibit no relevant hysteresis [23].

V. DYNAMIC DESTRUCTION THRESHOLD MODELING

A. Failure Power Models

To determine if a specific ESD will damage a device, its robustness threshold must be known. As discussed previously, a simple current threshold may not be sufficient; a dynamic threshold will better predict complex waveforms, such as an HMM discharge. Using a TLP with a varying pulse width, the damage threshold function (see Fig. 11) was created. The TLP current decreased as the pulse length increased, indicating that the device was energy limited.

Semiconductor devices under electrical over stress (EOS) have many microscopic failure mechanisms, e.g., surface breakdown around a junction and internal body breakdown through a junction. However, as Wunsch noted in [14], most failure mechanisms are linked primarily to the junction temperature. The widely used junction thermal model was developed by Wunsch and Bell [14], and later, Taska [16]. Their thermal analysis yielded the failure power (P) per unit junction area (A) as a function of the rectangular pulse width (tp ):

where K1 , K2 , and K are design-specific parameters that relate to the junction material and conductivities. The resulting curve of (5) appears in Fig. 12.

The parameters K1 , K2 , and K may not always be derived explicitly from junction design because in many applications, the material information and junction geometries are not known. They can be determined, however, by fitting the measured curves, as shown in Figs. 13 and 14.

B. Failure Criteria

To determine device failure under time-varying waveform P(τ ) based on the knowledge of the TLP tested failure power/time relationship P0 (t), one can identify whether or not any portion in P(τ ) injected the same amount of energy as a certain destructive rectangular pulse.

This idea can be derived from heat transfer equation [25]

where T is the junction temperature, ρ is the density, Cp is the specific heat capacity, D is the thermal diffusivity, and q(t) is the heating rate per unit volume. The Green’s function, or the solution to this function, is

The Green’s function is known as the impulse response in both the time and spatial domains. As an injection source P(r


 ,τ ) heating a defect volume Δ, the temperature at an observation location r (the vulnerable point) at time t can be written as [26]

where T0 is the initial ambient temperature.

A rectangular pulse with an amplitude of P0 and a duration of tf can damage a semiconductor junction because the failure point temperature reaches the failure temperature Tc

If an arbitrary injection profile that starts at an arbitrary time τ0 can also generate the same amount of heat within a duration of tf

This arbitrary waveform can be considered destructive. Therefore, the heat contribution of this arbitrary waveform to its equivalent rectangular pulse can be related as

The rectangular pulse failure power P0 is a function of duration tf (the failure power–time model in Section V-A), so the failure criterion is written as

Note that the power–time integral must be performed in an assumed failure time span tf ; otherwise, the integral of heat transfer function G cannot be eliminated. This is intuitive; if the injected arbitrary wave’s energy reaches P0 (tf ) tf over a longer span than tf , the junction temperature may still be lower than Tc because more heat has dissipated.

an Tc because more heat has dissipated. Equation (12) allows a devices’ thermal failure to be evaluated without knowing its material, geometry, failure location, or melting temperature. Only its tested failure model P0 (tf ) and simulated time-varying power profile P(τ ) are needed. Equation (12) can be implemented with the following algorithm:

Equation (12) can be simplified further if τ0 = 0, or, if the highest power portion always occurs at the beginning of an injection (usually the case for an ESD event). The criterion, therefore, is simplified as

The interception point of the left and right sides of (13) stands for the failure time and destructive injection energy (but not the energy that heats the defect region).

Section VII contains examples of applying the failure criterion.

VI. SYSTEM-LEVEL SETUP, ESD GUN MODEL, AND COMMON-MODE MODELING

A. System-Level Test Setup and Modeling

A contact-mode discharge on the DUT setup is shown in Fig. 15. A cellphone’s battery charging cord, filtered with a ferrite, was connected to the cell phone’s USB port as part of the return path. The cord’s shielding at the other end was shorted to a large metal plane.

In such a test setup, the ESD current return path (commonmode path) and the ESD generator should be modeled in order to correctly calculate the ESD current within the circuitry under investigation.

B. System-Level Grounding Model

For the system test setup shown in Fig. 15, the connection between the cell phone’s ground (metal frame) and the main ground plate can be modeled as shown in Fig. 16. The transmission lines TL1 and TL2 modeled the IO and Vcc nets on the double-sided flex circuit, respectively. The characteristic impedance was measured as 45Ω with a TDR. This impedance can also be calculated from the flex’s 2-D cross-sectional geometry. TL1 and TL2 were not referenced to the same metal; instead, their left sides were connected to the keyboard PCB’s local ground, and their right sides were shorted to the main PCB’s reference plane.

The transmission line TL3 modeled the flex’s ground metal relative to the cellphone’s body frame metal. The characteristic impedance of this common-mode path was measured as 120Ω.

C. ESD Gun Model

An ESD generator, TESEQ NSG 438 [27], was used in this project. Its equivalent circuit model appears in Fig. 17, which was developed based on Wang’s topology [28].

VII. SYSTEM-LEVEL SIMULATION RESULTS

A. System Model Validation

The system model was constructed by inserting all of the circuit models developed as described in Section IV, as well as the ESD gun model, into the system scheme shown in Fig. 16.

Fig. 18 shows one of our most challenging validation setups used for checking the model’s credibility and the robustness of the modeling methods. A Tektronix CT-6 probe was inserted in front of the IO pin to measure the ESD current flowing into the IC. To allow the current probe to be placed, an 8-mm-long wire was soldered in-series to the IO pin. This wire introduced an additional 4-nH inductance. The simulated current conformed to measurements reasonably well (see Fig. 19). The difference between simulated and measured results can be quantitatively described with the feature selective validation technique [29]– [31].

B. Application of the System Model for ESD Hard-Error Analysis

1) Transient Current Flows Into the LED: One objective was to determine the conditions under which the LED would suffer damage. Calculating the destruction criteria (12) on the simulated power profile and the LED’s failure model, respectively, showed that under +14 kV, the LED would be damaged (see Fig. 20), which agreed with our tested result. The checking algorithm also showed that under 15-kV injection, the damage would occur within the first 5 ns; under 14 kV, the damage occurred at 32 ns. Fig. 21 shows the result of the simplified checking algorithm (13).

2) Thermal Failure of the Driver IC: Another objective was to analyze the conditions under which the driver IC could survive without any external protection (same setup as shown in Fig. 18, but with a 10-nF nonlinear capacitor in parallel to the LED to avoid LED destruction).

By applying (12), we were able to predict that the driver IC could survive under 15 kV but would not withstand a 16-kV injection (see Fig. 22). This prediction also agreed with our tested results.

VIII. CONCLUSION

The transient response of a real cell phone product under IEC 61000-4-2 excitation was modeled. The proposed method features both high voltage/current and high speed (up to 3 GHz) modeling of typical components, including R, L, C, ferrite, diodes, and IC pins, as well as a complex return path model. The simulation result resembled the tested waveform at both the first and second peaks of the IEC excitation.

The time-dependent destruction threshold of a semiconductor device can be obtained from the tested Wunsch–Bell model with rectangular waveforms. This model accounts for thermal-related junction failures, which have been proven to be the primary cause of a semiconductor junction’s failure mode under EOS.

To determine the device failure under an arbitrary waveform based on the knowledge of the TLP tested failure power/time relationship, one can identify whether or not any portion in the arbitrary waveform P(τ ) injected the same amount of energy as a certain destructive rectangular pulse. Our proposed checking algorithm (12) and its simplified version (13) can be applied for IEC excitation scenarios. For other injection profiles in which the power peak does not occur at the very beginning of the whole waveform, (13) cannot be applied. It must be noted that the checking algorithm is based on a thermal failure model. In rare cases when a component is vulnerable to voltage breakdown, one needs to compare the simulated voltage profile to the TLP The proposed model is very suitable for both pre- and postdesign analysis due to its high computational efficiency. An engineer can quickly understand the holes in a design as long as off-the-shelf circuit models and failure threshold models can be provided readily by the device vendor. Besides using an extracted equivalent circuit model, one may model the return path more precisely with its geometry at the cost of computing time, as what have been done in [32]. A component can always be characterized with automated TLP and VNA measurements. characterized voltage threshold to predict if the device would damage. However, when a component is not available, one could model it from its geometry and material [33]. In addition to failure analysis, the system model also can be used to analyze ESD-induced interference in SI problems, with an additional coupling path model.

 

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TS002 Cable Discharge Event (CDE) Automated Evaluation System Based on TLP Method

Download Cable Discharge Event (CDE) Automated Test System Based on TLP Test Method (PDF)

What is CDE Event ? A Cable Discharge Event (CDE) is electrostatic discharge(s) between metal of a cable connector and the mating cable connector or plug. It is very common in daily life.

When CDE happens, transient high current and high voltage pulses are generated into the connector pins and cause potential damage to the system with connector. The pulse characteristic is determined by the cable type, cable length, physical arrangement of the cable and system with connector, and system with connector side circuitry.

As a pioneer and expert of Cable Electrostatic Discharge (ESD) solution provider, ESDEMC has been releasing several new Cable Discharge Event (CDE)  Automated Systems in the past 3 years. Lately, we would like to introduce our latest generic CDE system based on out latest TLP-MUX development.

MUX stands for Multiplexer, it allows many devices to be automatically tested with our ES62X series TLP system (our first TLP-MUX design works up to 32 devices). This allows the ESD reliability of different cable interconnection designs, such as the ESD reliability of USB, HDMI, VGA, DVI etc…, to be evaluated with detailed data analysis.

 

ESDEMC_GenericCDE_TLPbased_V2
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PB2015.11 Multi-physics Simulations for Triboelectric Charging of Display Panels During the Roller Transfer Process

Download PDF – Multi-physics Simulations for Triboelectric Charging of Display Panels During the Roller Transfer Process

50 Words Abstract – A multi-physics simulation methodology for triboelectric charging during the roller transfer process of display panels is proposed. Electrical and mechanical models for triboelectric charging are developed. Comparisons between the measured and the simulated results are conducted for the transient triboelectric charges of the display panels.

I. Introduction

There are several contact and separation steps during the display manufacturing process which increase productivity and automate manufacturing processes, such as the roller transfer of display panels and lift-up of display panels from vacuum stages. However, the glass for display panels is an insulating material in contrast to the dissipative silicon substrates; therefore, it is hard to bleed off the accumulated trioboelectric charges that accumulate.

Triboelectric charging is a physical phenomenon that has been known for thousands of years. Principles of triboelectric charging are applied in laser printing toners, electrophotography, energy harvesting devices, material separations, textile processing, pharmaceuticals, and granular flow processing. However, mechanisms of triboelectric charging are not completely understood [1]. Theoretical modeling and experimental work was conducted to address triboelectric charging of display panels [2, 3]. However, based on the authors’ survey there are few simulation approaches for the analysis of triboelectric charging of display panels.

In this work, a multi-physics simulation methodology for triboelectric charging of display panels during the roller transfer process is proposed. The electrical and mechanical modeling of the roller transfer process is included, and simulation results for the transient triboelectric charges and the E-field distributions on the display panel are shown.

II. Simulation Framework for Triboelectric Charging of Display Panels During Roller Transfer

Triboelectric charging of display panels during the roller transfer process is a multi-physics problem, i.e., the accumulated charges on display glass are dependent not only on the electrical properties of materials such as (effective) work functions, surface states and contact capacitances, but also on the mechanical properties such as friction, contact pressure and area between the glass and the rollers. In addition, the problem is not a static, but a timedependent event. Typical properties of triboelectric charging of display panels during the roller transfer process and related physics and simulation parameters are summarized in Table 1 based on previously published experimental works [1-4].

Although several simulation tools for multi-physics problems are commercially available such as COMSOL, there are few well-defined simulation models for triboelectric charging of display panels and the physical mechanisms are not clearly defined yet. It would be good to verify the proposed simulation methodology first and then implement it into the commercial multi-physics software by adopting the analytical modeling approaches.

Fig. 1 shows the flow chart of the proposed simulation methodology for triboelectric charging of display panels during the roller transfer process. First, the electrical and the mechanical properties of the glass and the rollers such as (effective) work functions, empirical parameters for triboelectric charging, dimensions and velocities of the roller transfer system, Young’s moduli and passion ratios, and so on are required to calculate the number of contacts, the contact area between the glass and the rollers, and the triboelectric charges at a given time. The triboelectric charges consist of contact and separation and frictional charges which are explained in this section. The variations of the roller diameters due to manufacturing tolerances and wear out are not considered in this work. The electrical and mechanical calculations are repeated until the charge calculation time is equal to the given E-field calculation time. After finishing the calculation of the charge distribution on the bottom of the display panel, the Efield distribution is calculated using a 3D electrostatic field simulator.

A. Modeling for Triboelectric Charging of Display panels

1. Modeling of Electrical Properties

Although the phenomenon of triboelectric charging has been described even in ancient times, there are few well-defined physical models for triboelectric charging between insulating materials. Triboelectric charging between metals or metal-to-insulator materials are well explained using the concept of work functions or effective work functions; however, many different charging mechanisms have been proposed such as electron transfer, ion transfer, and material transfer in order to physically explain triboelectric charging between insulating materials [1].

In this work, empirical modeling approaches [1, 4] are adopted to model the triboelectric charging: the empirical model consists of the charge transfer and the discharge terms, and requires experimental data to fit its coefficients. The driving force for the charge transfer is the difference in surface voltage between two materials and charges on the materials. The equation for net charge transfer is derived as [1]

where n is the number of contacts; qc and ql are the generated and the leakage charges of the triboelectric charging process, respectively; Cc is the contact capacitance between two materials; Vc is the (effective) work function difference; f is the frequency of the triboelectric charging process; and kc, ki, and kl are proportional constants for the generated, the leakage, and the image charges, respectively. Solving (1) with the initial condition q=q0 when n=0, gives the following equation,

which is used to calculate the triboelectric charges between the glass and the rollers, where n0 is the characteristic number of the triboelectric charging, q0 is the initial charges on the glass, and q∞ is the saturated charges on the glass. Both the characteristic number of triboelectric charging and the saturated charges are functions of the capacitance between two materials, the contact area, the frequency of the triboelectric charging process, and the (effective) work function differences as shown in (3) and (4)

It is important to note that the proportional constants kc, ki, and kl are empirical parameters and the contact area between two materials should be known in order to calculate the capacitance between them.

Equations (1)–(4) were originally developed to describe the electrification by impact of a sphere on a plane, and Fig. 2 shows the conceptual analogy between the electrification by the impact of the sphere and by the roller transfer process. The (n-1)th, n th, and (n+1)th rollers simultaneously contact the display panel and shift left with the frequency of vtrans/d, where d is the spacing between the shafts, and vtran is the transfer velocity of the glass. The contact frequency of a specific location on the glass from the n th to (n+1)th rollers is equal to vtrans/d.

The E-field distribution on the display panel is calculated by numerically solving the 3D Poisson’s equation with the boundary conditions of the charge distribution on the bottom of the display panel and the grounding conditions of the shafts. A commercially available 3D solver, CST EM Studio, was used in this work. It was assumed that the charges do not move on the surface via surface discharges.

2. Modeling of Mechanical Properties

The transmission of the glass on the roller transfer system is based on the rolling contact between the rollers and the glass. In the rolling contact, the contact area is divided into two domains: a sticking domain with the length of 2a′ and a slipping/skidding domain with the length (2a-2a′). In the sticking domain, the relative velocity at the contact vtran-Rω is zero, which means the pure rolling condition (static friction). In the slipping/skidding domain, the relative velocity is a nonzero value, which means the slipping condition (dynamic friction). In other words,

where 2a is the contact length of two cylinders with parallel axes from the Hertzian equation, τ(x,t) is the tangential stress distribution, p(x,t) is the Hertzian pressure distribution, μ is the friction coefficient according to the friction law of Coulomb, ω is the angular velocity, and R is the radius of the rollers [5, 6].

The ratio of each domain in the contact area depends on the relative velocity at the contact, and the areas of each domain are calculated using (7) and (8)

where Fn is the applied load, R′ is the combined radius, E′ is the combined elasticity modulus, and wroller is the width of the rollers [5, 6]. The number of rollers beneath the glass is calculated every time, and then the force due to gravity is divided by the number of rollers to calculate Fn. Under pure rolling, i.e., the rolling without slipping condition (vtran=Rω), the area of the sticking domain is equal to the Hertzian contact area, while the area of the slipping/skidding domain grows with increasing the relative velocity at the contact until it encompasses the entire contact area.

Because the skidding/slipping may stain the surface of the glass and cause display failures, the translational (transfer) and circumferential velocity should be under control in order to minimize the skidding/slipping during the display manufacturing process. However, the relative velocity at the contact inevitably increases/decreases during either acceleration (vtranRω) of the transfer velocity at both the beginning and the end of the roller transfer system, or during transfer velocity changes between two manufacturing units. Fig. 3 shows the conceptual diagram for the relative velocity at the contact and the corresponding contact areas of the sticking and the slipping/skidding domains during the roller transfer process of the display panels.

Triboelectric charges tend to increase as the acceleration/deceleration time of the transfer velocity decreases, or when there is a transfer velocity difference between manufacturing units as shown in Table 1 [2, 3]. There are still arguments on the physical causes of the increased charges, and potential reasons are increased contact area for charge transfer, localized frictional heating, material transfer, and so on [7–9]. In [9], the authors experimentally showed the effects of the contact area and the relative velocity at the contact on the triboelectric charges by changing the normal contact force and the rubbing velocity between two materials, respectively. In addition, the heat produced through friction is proportional to the contact area and the relative velocity at contact as shown in (9) [10]

Based on the previously mentioned works, (2) is modified in order to consider the different triboelectric charging characteristics of the sticking and the slipping/skidding domains of the contact area as shown in (10)

where qsticking is the triboelectric charges between the glass and the rollers under the pure sticking condition, and qslipping/skidding is the triboelectric charges between the glass and the rollers under the pure slipping/skidding condition. Pure contact and separation electrification for the sticking domain, and pure frictional electrification for the slipping/skidding domain are assumed. The triboelectric charges for the partial sticking and partial slipping/skidding conditions are calculated by summing the multiplications of the triboelectric charges of the pure sticking and the pure slipping/skidding conditions by the areas of each domain, as shown in (10).

3. Modeling of Triboelectric Charging Characteristics Between Glass and Roller

In order to simulate triboelectric charging using (10), six constants n0, q0, and q∞ values for the pure sticking and the pure slipping/skidding conditions should be experimentally determined by fitting with the measured triboelectric charges because they are functions of not only the known physical constants (such as the (effective) work functions, the contact capacitance, the effective contact area and frequency), but also the empirical fitting parameters (kc, ki, and kl for the charging and the discharging efficiencies, humidity, surface roughness, manufacturing tolerance, and so on), as shown in (3)–(4).

An apparatus for determining the triboelectric charging between the glass and the rollers was developed in our research group. Material characterizations for the triboelectric simulations and correlation results between the measured and the simulated results are shown in section III. In this section, the triboelectric charging characteristics are fitted based on data in the published paper for insulating and dissipative materials [11].

Fig. 4 shows the modeled triboelectric charging characteristics between the glass and a single roller as the function of the number of the contacts for the purpose of simulation tool development. For the sample selected it was observed that the accumulated charges with the dissipative material were larger than those with the insulating material, and the charging time was also faster with the dissipative material [11]. The authors experimentally show that static dissipative surfaces can charge up insulating surfaces more efficiently than actual insulating surfaces in the case of friction between grounded static dissipative and insulating surfaces, and emphasize that triboelectric charging is highly related to the test arrangement and insulators must be evaluated case by case.

We analyzed the triboelectric charging behavior of the display panels during roller transfer processing by using the aforementioned electrical and mechanical models and the modeled triboelectric charging characteristics. In order to obtain the best possible prediction of the quantity of the triboelectric charges, fitting of the empirical parameters should be conducted with the same materials of the roller transfer system, which is discussed in section III in detail.

B. Simulated Triboelectric Charging of Display Panels

1. Charge Distribution Beneath Display Panel

Fig. 5 shows the schematic diagram of the roller transfer system of the display panels, where sshaft and sroller are the spacing between the shafts and the rollers, respectively, and ldisplay and wdisplay are the length and the width of the display panel, respectively. The values of wroller, ldisplay, and wdisplay are 10, 2200, and 1870, all in mm, respectively. Two different combinations for the values of droller and sshaft are used; 60 and 150 (case 1), and 180 and 450 (case 2), all in mm, respectively. The transferred distance, dtransfer, is determined by the transfer velocity and the E-field calculation time.

Fig. 6 (a) shows the transient triboelectric charges on the bottom of the display panel at 5 and 15 sec with a 100 mm/sec transfer velocity, and rollers are assumed to be made of dissipative material. Fig. 6 (b) shows the transient triboelectric charges on the bottom of the display panel with the same condition, but now assuming insulating rollers. In both of cases, the diameter of the rollers and the spacing between the shafts is 60 mm and 150 mm, respectively. The maximum values of the triboelectric charge density with the dissipative and the insulating rollers at 15 sec are 10.5 nC/mm2 and 3.8 nC/mm2 , respectively. The triboelectric charges with the dissipative rollers reach the saturation value of triboelectric charging faster than those with the insulating rollers.

2. E-field Distribution on Display Panel

Fig. 7 (a) and (b) show potential distributions on bare glass at 15 sec using a transfer velocity of 100 mm/sec. The insulating materials for the combination of case 1 and 2 are used. Three lines of rollers are considered.

The peak potential of case 2 is 1.7 times higher than that of case 1 because the increased distance from the ground which is linearly proportional to the diameter of the rollers. Both of the cases are simulated under rolling condition without considering slipping.

III. Material Characterizations and Correlation between Measured and Simulated Results

A. Descriptions of Characterizations and Measurements Setup

Fig. 8 shows the fabricated apparatus for the characterizations of the roller and the glass materials and the measurements of the triboelectric charges of the roller transfer process, where the width and the transfer length of the apparatus are 61 cm and 188 cm, respectively. The stepper motors are used to control the rotational speed of the rollers and to control the height of the lift pins. The glass travels back and forth on the rollers by changing the rotational direction of the rollers, and the acceleration/deceleration time of the transfer velocity is also controllable. The lift pins are used to investigate the effect of the height of the glass from the ground on the electrostatic voltages on the glass and for charge creation during lift off from a metallic platform.

Several design parameters such as the diameter of the rollers, the spacing between the rollers, and the spacing between the shafts are mechanically adjustable. Insulating UHMW (ultra-high-molecularweight) polyethylene was used to fabricate the rollers. Alkaline earth boro-aluminosilicate glasses are used for the characterizations of the materials and the measurements of the triboelectric charging.

The triboelectric charges were measured using a Faraday cup and the ES103 solid state electrometer from ESDEMC Technology LLC. The TREK model 347 electrostatic voltmeter was used to measure a voltage that leads to a field cancellation on the glass and the rollers [12]. In order to control the ambient humidity and temperature all of the characterizations and the measurements were conducted in the climate chamber with 30% humidity and 22° C ambient temperature [13]. In this work the 30% R.H. was selected, which is the lowest reliable level of humidity at 22° C which can be achieved in the climate chamber in summer months. Follow up experiments in the winter will allow lower humidity. The rollers and the glasses are cleaned using 91% isopropyl alcohol and preconditioned in the climate chamber for a minimum of twelve hours.

Firstly, the material characterizations were conducted by changing the number of the contacts, and based on the characterization results the required simulation parameters were extracted. As the next step, the multiphysics simulation of the triboelectric charging was conducted with different operating conditions and compared to measurements.

B. Characterization of Materials

In this work, the triboelectric charging characteristics under rolling without the slipping condition were studied. Because the triboelectric charges are dependent on the relative velocity at the contact and there are velocity changes due to the acceleration and the deceleration periods at both ends of the roller transfer system, two-step measurements were conducted in order to extract the triboelectric charges of the sticking domain only. The proposed method can also be applied to the triboelectric charging characterizations for the rolling with slipping condition, which is a future work.

First, the glass on the roller transfer system travelled back and forth with only the acceleration and the deceleration periods as shown in Fig. 9 (a), and the triboelectric charges on the glass were measured using the Faraday cup and the solid state electrometer. The triboelectric charges were measured again within the constant velocity period, as well as during the acceleration and the deceleration periods as shown in Fig. 9 (b). Using these two measured triboelectric charges, the triboelectric charges under the rolling without slipping condition were de-embedded.

The de-embedding was conducted by subtracting the triboelectric charges during the acceleration and deceleration periods from those having completed full periods. The driving conditions of the roller transfer system are summarized in Table 2.

Fig. 10 shows the measured triboelectric charge densities on the glass as the function of the number of contacts: the solid blue circles show the charge density with the driving conditions of the acceleration and the deceleration periods only, and the solid black triangles show the charge density with the driving conditions of the acceleration, the constant velocity, and the deceleration periods. The solid red squares show the de-embedded triboelectric charge density based only on the steady-state transfer velocity period. With less than 2400 number of contacts the measured triboelectric charges due to the acceleration and the deceleration periods are higher than those due to the steady-state transfer velocity period, however, the triboelectric charges due to the acceleration and the deceleration periods reached the saturated values of the triboelectric charging faster than the triboelectric charges due to the steady-state transfer velocity period.

The empirical parameters are extracted using the measured triboelectric charges. The purple line shows the simulated triboelectric charge density due to the steady-state transfer velocity period, and they show good agreements with the measured the triboelectric charge density due to the steady-state transfer velocity period.

C. Comparisons Between Measured and Simulated Results

Triboelectric charges due to the steady-state transfer velocity period were simulated with the extracted simulation parameters by changing the transferred distance. Fig. 11 shows the measured and the simulated total charges on the glass, where the solid red squares show the measured total charges and the purple line shows the simulated total charges, which show good agreement with the measured charges.

IV. Conclusions and Future Works

A simulation methodology for triboelectric charging of the roller transfer process is proposed. First, the methodology was verified based on previously published triboelectric characteristics of materials. The apparatus for the triboelectric charging characterizations of the glass and roller materials was developed, and material characterizations were conducted. Based on the material characterization results, the empirical parameters in the triboelectric charging equations were extracted and comparisons between the measured and the simulated triboelectric charges were conducted.

The developed simulation methodology is based on empirical equations. Systematic characterizations for triboelectric charging of glass on the roller transfer system using the developed apparatus would greatly helpful to optimize the empirical parameters extraction process and the equations themselves. In addition, the verification of the proposed triboelectric charging equations for the slipping/skidding domain is another future work.

Acknowledgements

The authors would like to acknowledge Samsung Display Co., Ltd., for supporting this project. The authors also would like to thank Jeffrey Birt for the design and fabrication of the roller transfer system and thank ESDEMC Technology LLC for providing the solid state electrometer.

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TR001 VF-TLP Performance of PIN-Limiter Diodes

3D Diode TransientResistance-Time-Voltage Surface Plot

Download or View in pdf: TR001_VF-TLP Performance of PIN-Limiter Diodes

The objective is to test the Pin-limiter diodes for their ESD performance. The end application for these diodes will be decided by diode parameters like the turn on voltage, dynamic resistance, diode capacitance and survival current. Based on these parameters the diodes can be chosen for ESD protection application suitable for the lab instruments.

The pin-limiter diodes were bought from different manufacturers like Cobham, Skyworks, Microsemi and Avago. These diodes were soldered in reverse bias orientation from the trace to ground on the evaluation PCB’s. They were first tested for their frequency response and then they were tested for the ESD performance using the VF-TLP setup. The results of these diodes measurements are shown in the subsequent sections of this report.

 

 

by Shubhankar Marathe, Jerry Tichenor, David Pommrenke, Wei Huang

 

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PB2015.09 Spark-less Electrostatic Discharge ESD on Display Screens

Download PDF – Spark-less Electrostatic Discharge ESD on Display Screens

Abstract—An electrostatic discharge (ESD) to a display screen may lead to sparking into the phone’s structure, e.g., via the glue that connects the different glass layers of the touching panel/LCD, or it may just cause surface charging. The latter is the most likely case for a well-designed display, as the insulation design usually prevents any sparking to the electronics. Even if no spark is visible, strong surface charging occurs. These charges couple via displacement current and via their magnetic field into the display electronics. Most phone and tablet manufacturers currently suffer from damages or upsets caused by this type of spark-less ESD. As far as we know, no data has been published showing the magnitude, rise time and total charge parameters of these surface discharges for displays. In this paper, discharges to different displays have been measured at ±4, ±8, ±10 and ±14 kV. The discharge currents are measured using an F65 current clamp. Five different types of display screens have been tested and the results of transient current discharges are compared in this paper. During the experiments, repeatability of results is investigated. Moreover, the effects of touch position as well as dirty screens (i.e., presence of finger prints, etc) are investigated.

Keywords— Electrostatic discharge (ESD), portable device, display screen, rise time;

I. INTRODUCTION

Electrostatic discharge (ESD) is a severe source of interference in electronic products and can produce damage or upset failures. In different areas, ESD has been studied. In [1], decay times of ESD events caused by garment removal and sitting/standing motions from a chair are presented. In [1]-[6]. ESD in data centers caused by various types of human activities—walking, sitting/standing from a chair, and garment removal—have been studied at different dew points (various temperature-relative humidity). Presently, many manufacturers of portable electronic devices which utilize display screens including mobile cell phones, smart phones, multimedia players, etc., are facing severe ESD related problems which demands ESD protection, [7]-[10]. In most of these products, LCD, LED, or electronic ink screens are utilized. Generally, ESD on electronic products might occur when the device itself becomes charged by triboelectrification and approaches another conducting object. Other types of ESD occur when a human, charged by triboelectrification, touches the electronic product. Thus, it can be said that the ESD can either produce a spark (e.g., to the body of the cell phone), or it can be a sparkless corona charging the glass display screen. Therefore, there is high interest in the understanding of ESD events on the display screens of portable electronic products.

This paper presents measurements of spark-less discharges to displays. The ultimate goal of this work is to understand the mechanisms that allow the spark-less discharges to upset or destroy display or touch screen circuits. A prerequisite to this is to understand the current magnitudes, rise times, and total charges associated with an ESD event and their dependence to parameters like polarity, voltage, and different display types. Further, quantifying the current densities through display glass and the current density distribution is important. This paper reports on measurement and analysis of the governing parameters for spark-less surface discharges to displays. The distribution of the deposited charges can be further illustrated using the Lichtenberg dust figure method [11]-[14], which is known that related to the discharge voltage level, polarity, etc.

II. MEASUREMENT SET-UP

Fig. 1(a) shows the measurement set-up. An ESD gun or generator connected to voltage source is used to create the desired discharges to the device under test. A current clamp, F65 (Fischer Custom Communications), having a transfer impedance of 1 ohm, is used to measure the discharge current. Five different displays are compared, including displays released in 2014. In the real application the displays are connected to the main PCB of the device by flex cables. These nets have ESD protection, so it is reasonable to assume that these nets act as if they are connected to the system ground. For the displays which are tested without being integrated into a functional system, the flex cable connectors are grounded. Furthermore, the displays usually back against a metallic frame of a cell phone, tablet, etc. These frames are connected to a large ground plane. Electrically, the consequence is that part of the displacement current that flows through the glass can flow via the touch and LCD flex cable to ground, and part will reach the back metal structure. As of now, the ratio of currents is not known, but the touch circuit’s ITO layers have a high resistance, such that the current fraction through these layers maybe small. The ESD generator is grounded to the metal plane, which is also connected to the oscilloscope shield. A current clamp, shown in Fig. 1(b) is placed around the air discharge ESD generator tip. A coaxial cable via a bulk-head SMA connector is connected to the current clamp to divert any common mode current away from the oscilloscope. As further protection, a 20dB attenuator is used. The experiment is conducted by approaching the display with the ESD generator (in air discharge mode). As seen in Fig. 1(c), five display screens are utilized for experiments, and are labeled as screen #1 to #5. To perform the experiments, charge voltages of ±4, ±8, ±10, and ±14 kV were used. The surface of the screens can be clean or dirty. The touch location and approach speed were varied. Three approximate approach speeds were used, and are referred to as “slow”, “medium”, and “fast”. The slow approach speed was in the range 1cm/sec, and the fast approach was close to the speed which may break the glass. Thus, the medium approaching speed was used in most experiments. As shown in Fig. 2 for voltage of +8 kV, the influence is strong and the slow approach has the lowest discharge current and the fast approach has the highest current. While achieving constant speed was difficult, each experiment was repeated several times for each experiment. Further, a phenomenon observed from discharge current is a double peak, shown in Fig. 3 for screen #1 to #3, at +8 kV. It shows that the 1 st rise time is faster than the 2nd .

III. MEASUREMENT RESULTS AND DISCUSSIONS

A. Repeatability

To understand the natural and experimentally induced variations of these discharges, repeatability testing was performed. Each discharge measurement was repeated at least 3 times using medium approach speed to the center of the screen. Tests were repeated over three days. The results are presented in Fig. 4. From the results, variation of the peak current are seen which might be due to variation of approaching speed (i.e., faster approaching often gives higher current, and faster rise time), humidity and temperature [1], fine layer of moisture, spark initiation, etc. Comparing all the screens together shows that screen #1 experiences the highest peak currents and screen #2 has the lowest peak currents. Generally, these currents show a fast rise (< 2 nSec) and a slower decay. The decay to 50% of its amplitude is about 20- 30 nSec. The amplitudes are highly voltage dependent but reach a few amperes for +10 kV, which explains their potential to disrupt or damage displays. This is true for human metal discharges (IEC 61000-4-2 or also called HMM). A discharge from the skin (Human Body Model–HBM) shows much lower currents. Thus, this paper provides data related to ESD tests in which a metal part is used to touch the screen. The current rise times and peak values determine the current derivative which quantifies the magnetic fields which may induce voltages in the screen electronics. Thus, two mechanisms may lead to disturbances: the current derivative induced voltages, and the displacement currents. The total charge, peak current, and 1st and 2nd rise time parameters are presented for +4kV in Table I. The numbers show the average of results for different days. Both mean value (m) and standard deviation (s) are presented to illustrate the repeatability. For reasons presently unknown, but suspected to be related to the glass thickness and grounding of the touch and LCD structure, it is observed that screen #1 has the largest average peak current (0.7 Amp, +4 kV) and screen #2 has the lowest average peak current (0.31 Amp). This again indicates that the design of screen #1 may contain features that will create more difficulties in passing IEC 61000- 4-2 tests. The average peak current from all the screens is around 0.45 Amp. Also, screen #2 showed the lowest peak current but the largest transferred charge (7.67 nC) on its surface. As there is no conduction current flowing through the glass, these charges are deposited on the glass surface. Also, the lowest transferred charge (3.6 nC) was measured on screen #4. The average charge transfer at +4 kV was around 6.3 nC. The first peak showed an average rise time of 0.49 nSec. This value may already be influenced by the 1 GHz bandwidth of the current probe. The second peak current rose in 1.35 nSec (screen #4). The slowest rise of 0.48 nSec was observed on screen #2. The average rise time for the second peak was 2.49 nSec.

B. Dirty vs. Clean Screen

The presence of fingerprints (i.e., a more realistic case than a clean screen) causes a thin layer of oil, dust, etc. which can lead to changes in the amount of current or transferred charge on the screen. Thus, it is interesting to analyze the discharge behavior for the case of dirty screens and compare them with clean ones. To do this, three screens were selected: screen #1, #4, and #5. The ESD source voltage level was set on +4 kV. The discharge measurements were repeated three times at medium speed at the center point of the screens. As seen in Fig. 5, the presence of fingerprints or dust on the display screen has little effect on the discharge behavior. A double rise is observed again for all cases. The results are combined together in Table II. As seen, the mean values of the peak current amplitude for a clean (0.97 Amp) and a dirty (1.04 Amp) screen for screen #1 are similar. However, around 0.1 Amp difference is observed for screen #4 and #5. Moreover, dirty screens showed a higher transferred charge (about 1nC higher). The first and second rise times remain about the same.

C. Position

If a large portion of the current would flow via the ITO layers of the touch-screen or the LCD structures, then a discharge position towards the interfaces would have a lower resistance path, and would lead to a higher current. As seen in Fig. 6, three different positions including top, center, and bottom were tested at different times. No large variation was observed when testing three screens (screen #2, #4 and #5) at +4 kV using a medium approach speed and clean surface. This indicates that a large portion of the current might flow as displacement current through the display to the metallic backing structure.

D. Polarity and voltage level

The dielectric response of the glass, and the conductivity of metal structures is linear with respect to voltage and polarity. While ESD protection structures usually are not symmetrical, it is unlikely that this asymmetry can be seen in the current of the spark-less discharge, as all ESD protection of the touch and LCD probably turn on, resulting into a virtual short. However, it is known that surface discharges may strongly depend on the polarity due to the large difference in the velocity of electrons, relative to ions. This motivated us to compare the currents for both polarities. Strong difference may indicate a higher likelihood of failures in one polarity.

Here, a medium approach speed and a discharge location in the center of a clean screen were selected. Each experiment was repeated 3 times for all the voltages. Fig. 7 presents the current waveforms for positive charge voltages (A to D), and for negative charge voltages (E to H). The peak current dependency as well as charge for positive/negative voltages is shown in Fig. 8 (H to J).

There are strong differences between negative and positive charge voltages. While the rise times are similar, the peak current for negative charge voltages is more than 10 times smaller than positive charge voltages (compare Fig. 7: A to E, B to F, C to G, D to H).

In addition, the peak current increased, reaching 4 Amp for voltages up to +10kV for the positive case (Fig. 8, I), however, within the limited range of our present observations from -4 to -14kV, the largest peak current was measured at -4kV, while -8 to -14kV showed the same peak currents (Fig. 8, K).

Moreover, the distributed charges are much larger for the positive case. The charges increased to about 70 nC (+10 kV, Fig. 8, J). The negative voltages led to charges up to -6 nC (Fig. 8, L).

In all but the very slow approach speed case, positive charge voltages let to a double peak in the rising edge, this was rarely observed for the negative voltage.

Beside, screen #1 showed the highest peak currents (Fig. 7, A to D). The design details of the screen are not known, however it indicates that this design maybe more ESD susceptible due to the higher currents.

Multiple possible consequences can be supported from the results. If the failure mechanism is polarity independent and related to rise time, no polarity dependence would be expected. However if the total transferred charge is relevant (e.g., melting of a trace), or the peak current is critical, then the robustness will be less for positive polarity discharges. To analyze these results with respect to the current density of the displacement current that leads to currents on the ITO layers and in the LCD, an additional fact needs to be considered. It is known that the charge distributes over a much smaller area for negatively charged electrodes. Although the peak current is less for the negative charge voltage, it might be stronger concentrated in one area. On the other hand, if the peak current correlates to the failure mechanism, then positive polarity is worse than negative polarity for failure level. Also if the total transferred charge matters (e.g., a trace burns out), then positive polarity should be worse than negative polarity.

IV. CONCLUSION

In this paper, measurement results from spark-less electrostatic discharge on five display screens are presented. Using an ESD generator in air discharge mode, the currents are measured at ±4, ±8, ±10 and ±14 kV using a current clamp. The surface discharge waveform shows a fast double peak rise +14kV, a charge transfer of about 60 nC and a peak current of 5 Amp was measured. These currents are sufficient to damage or disrupt the display. These peak currents depend non-linearly on the voltage and may not even increase with increased voltage. This research will be continued by modeling the current distribution in the display between the touch and LCD connections relative to the displacement current that flows through display to the metallic body of the grounded system.

ACKNOWLEDGMENT

This material is based upon work supported partially by the National Science Foundation under Grant No. IIP-1440110 and the work is supported in part by the scholarship from China Scholarship Council (CSC).

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TS001 Introduction of Transmission Line Pulse (TLP) Testing for ESD Analysis -Device Level

This slides introduce the basic about Electrostatic Discharge (ESD), How ESD tests have been done, What is TLP testing, and FAQs.

ESDEMC_TS001_Introduction of TLP for ESD Analysis – Device Level

ESDEMC_TS001_Introduction of TLP for ESD Analysis – Device Level_CN

By Wei Huang, Jerry Tichenor, David Pommerenke

Introduction of Transmission Line Pulse (TLP) Testing for ESD Analysis – Device Level from Wei Huang

用于ESD分析的传输线脉冲测试 (Transmission Line Pulse – TLP Measurement) 元件级 from Wei Huang
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PB2014.08 An Ethernet Cable Discharge Event (CDE) Test and Measurement System

Download PDF –  An Ethernet Cable Discharge Event (CDE) Test and Measurement System

Abstract — A Cable Discharge Event (CDE) is an electrostatic discharge between a cable and a connector. CDEs occur on unshielded Ethernet based communication interfaces and inject currents into the pins directly [1-3]. The charging processes are in general understood; however, the discharge processes are complicated due to the number of pins involved and their connections to a system. Based on an understanding of the factors which determine the severity of a CDE, this article describes how to setup a variety of repeatable CDE tests and how to analyze the measurement results.

Keywords — Cable Discharge Event (CDE) Test; Cable ESD;

 I. INTRODUCTION

 

Both occurrence rate and severity of a CDE needs to be considered when determining the importance of dedicated CDE tests to ensure a reliable system. The occurrence rate of a CDE depends on the type of connector used and the environment the system is used. While a USB connector on a laptop will receive many more ESD events than a LAN connector, the LAN connector still poses a larger risk to the system as it is usually not shielded and often used in applications that require high reliability such as back bone internet routers. In contrast to a USB connector, a LAN connector can have a spark from the connector to a pin during a CDE. In the case of USB connectors the connector shells will mate first. Provided that the shells are connected to the shield and to the system ground, most of the discharge current will flow on the connector shells.

For the LAN CDE case a good understanding of the dominating processes provides a mean for developing and validating models. These models will allow computer simulation, and laboratory test setup formulation for reproducing real CDEs. This is crucial for IC and system level engineers to study and optimize the immunity of Ethernet based communications interface designs.

It is well known that triboelectric charging is the culprit that generates the charge on a cable [1],[2]. This fact is especially important in Ethernet communication systems due to the long lengths of UPT cable that must be pulled through conduit, which may result into large charges. A model for describing the interaction of one twisted pair in a UTP (Unshielded Twisted Pair) cable is presented in [2] using a three body model analyzed from an electrostatic point of view. In [3] a system for discharging a cable using a relay on a test bed is presented, and experimental results are shown. In regards to the measurement analysis side of Ethernet CDE, there are few publications discussing the phenomena. Some ESD test setup have been developed to repeat ESD current transfer through Ethernet magnetic effects in [4] and [5].

The focus of this article is to present a CDE testing system that will allow for real world test conditions to be reproduced in the laboratory, thereby providing design engineers a quick and reliable method for testing new hardware designs. The test system will allow for different types of copper based Ethernet cables, and twisted pair termination strategies. Further, full control of the charge and discharge sequence of each cable line allows for all possible cases to be explored.

II. IMPORTANT PARAMETERS IN ETHERNET CDE

Prior to discussing the CDE test system, a few important parameters of copper based Ethernet cable CDE, especially UTP must be reviewed.

A. Parameters of the charged Ethernet cable affecting CDE

Several important parameters must be considered in UTP cables. The first parameter is the charging processes in UTP cables. In particular, the wires can be charged due to charges on the outside of the jacket, due to migration of charges through the jacket and insulation to the wires, or due to direct contact of the wires with a charged object. The voltage magnitude can be as high as 2 kV. In most cases all wires will be charged to the same voltage. If the spatial arrangement of the cables is changed, the capacitance between the charged wires and ground will also change, which can further increase the charge voltage.

Another important parameter to consider is that there are shielded and unshielded cables for Ethernet. These cable types are illustrated in Fig. 1. They all maintain 100 Ohm differential impedance for each twisted pair, but the unshielded cable will have relatively large common mode impedance (100-300 Ohm) versus the shielded cables because their current path is physically far from the ground as compared to the shielded wires. This common mode impedance plays a critical role in the magnitude and to a lesser extend in the shape of the CDE discharge current waveform.

B. The termination of the Ethernet device

Load terminations also play an important role in the characterization of a CDE. Many different types of termination schemes exist, however, the most commonly used is the Bob Smith Termination [5]. This termination uses a 75 W resistor for a common mode impedance match at each signal pair, and they all connect via a high voltage capacitor to chassis ground as shown in Fig 2. The isolation between the Ethernet connector/chassis and internal PHY circuit is established through a transformer and some designs incorporate common mode chokes to further reduce common mode current motivated EMI concerns. Further variations of the Bob Smith circuit can be found in power over Ethernet applications, and strongly cost reduced designs.

One pin will make the first contact and any other pin will contact next. The initial contact leads to a charge redistribution, a partial discharge of the total charge on the cable, and it can charge the capacitor used in the Bob Smith circuit. Depending on the contact sequence, various common mode and differential mode termination plus the PHY IC circuit determine the load of the discharge current path and therefore are the important factors that determine the CDE current waveform.

C. The ESD events during CDE

The Ethernet cable connection includes several metal to metal contacts, which can lead to multiple ESD events during connection. For the case of plugging a shielded Ethernet cable into a shielded Ethernet connector, the first ESD event is the discharge between the shielding of the cable to the shielding of Ethernet connector as this is the first contact point. Normally this ESD is not likely to cause any failures if the DUT is shielded. For the case of an unshielded cable or an unshielded Ethernet connector the current must flow in the wires of the UTP.

When an Ethernet cable is plugged into a connector, many possible contact sequences can occur. Theoretically there could be eight separate ESD events, one for each pin. However, each contact will minimize the voltage between the other pins and the connector. This is caused by the large mutual capacitance between the wires, and by charging the Bob Smith Termination.

To illustrate the charging of the capacitor in the Bob Smith circuit, a 100 m long shielded cable was charged to 100 V between the shield and its wires and inserted into an Ethernet device. A result from this experiment is shown in Fig 3. Because the capacitance between the wires and the shield is much larger than the 1000 pF capacitor, the voltage reaches over 90 V immediately after first contact, thereby lowering the voltage difference between other connecting pins. For the next seven contact events the voltage difference across the contacts is drastically reduced.

The voltage waveform shown in Fig 3 gradually diminishes due to the 100 MW resistive voltage probe used in the measurement. Without this drain path the voltage on the cable will remain high for a very long time after the connection is made. If the other end of this cable is plugged into an Ethernet device another cable discharge event may occur.

Because the differential pairs of the cable have a welldefined 100 W discharge impedance, after the first wire has made contact and the high voltage capacitor has a low impedance path to ground, such that the second wire also experiences the discharge as it is making contact, resulting in a differential ESD event. This differential ESD current can easily transfer through the magnetics to the isolated PHY circuit, which is hazardous for the PHY chip.

III. THE ETHERNET CDE TEST SYSTEM CONCEPT

A good Ethernet CDE test setup should be able to control as many of the parameters related to the cable discharge event as possible, and provide a repeatable test. To do this the setup must have these three main components; a Controller, a Charge Module, and a Failure Test Monitor.

The Controller must have the capability to control cable charge voltage and polarity, charge and discharge different types of Ethernet cable arrangements, and separately control the charging, floating, grounding, or discharge of each wire. In addition, the test system should maintain the electrical characteristic of the entire discharge current path as close to real world CDE cases as possible. In particular, it should control common and differential mode impedance of each pair, and the contact sequence delay time between each discharge to the same order of magnitude of a real cable as it is plugged into a device.

The Charge Module represents the Ethernet cable used as the discharge source for the CDE event. This consists of different lengths of various CAT5 cable types. For research purposes, different types of cables and how they are arranged must be studied. For industry testing purposes, a good charge module will provide a worst case, real world CDE source.

ill provide a worst case, real world CDE source. The Failure Test Monitor provides a means for verifying the Ethernet performance. It will check if a failure has occurred, or simply if a degradation in communication speed has occurred. It is important this is automated due to the vast array of tests that can be performed to check all discharge sequences. A general block diagram of the CDE test system is shown in Fig 4.

A. CDE Test Controller

The main CDE test controller consists of high voltage supplies (dual polarity), relays to separately control the connection of each Ethernet cable wire, including whether it is charging, floating, or grounded. The relays are bounce free and provide a clean discharge for each wire. The transmission lines on the board maintain the controlled 100 W differential pair structure of the Ethernet cable, and current probes are embedded into each wire to monitor CDE discharge current. The system also has remote control capability integrated into the upper level system as a part of the automatic test equipment (ATE). A simplified diagram of the main CDE controller is shown in Fig 5.

A common test procedure may consist of the following four steps, as illustrated by the block diagram in Fig 6.

1. Charge cable status control

The controller separately controls the voltage (level and polarity) for each wire in the cable bundle. This includes the status of each wire indicating if it is charged, floating, grounded, or a through path.

2. Pre-discharge preparation

The controller will disconnect the charging path from each wire in the Ethernet cable bundle and disconnect the DUT discharge path between the DUT connector and ground. This will leave all wires floating before the discharge step.

3. Control wire discharge while monitoring ESD Current

The controller will close the relays allowing the wires coming from the charge line to discharge into the DUT or termination load. The sequence of the relay closure and the delay between relay closures can be set by the user.

4. Preparation after a discharge and check DUT status

The controller will open all cable discharge relays such that the cable can be charged again. To charge the wires the high voltage charging relays are closed. In additional all remaining charges on the DUT need to be removed. This is achieved by closing the DUT discharge relays.

The controller will open all cable discharge relays, then close all high voltage charging relays and DUT connector discharge relays to prepare for next CDE test.

B. Charge Module

In real world Ethernet cable installations there are many different possibilities in regard to cable type and arrangements, leading to unlimited test scenarios. Some common real world arrangements are:

A. Cable hanging on the celling (relatively far from ground)

B. Cable on the floor (very close to the ground)

C. A spool of new cable

D. Cable pulled through conduit (very close to the ground)

C. Failure Test Module

Besides the setup for CDE test control, it is also important to test for normal Ethernet performance and functionality. It is important to understand the effects of applied CDE on the DUT, and as in the block diagram of Fig 4, an Ethernet traffic test system should not only monitor the status of DUT during CDE test, but also check the performance of the CDE applied ported after each test level.

D. Calibration of the Ethernet CDE Test System

A CDE Tester (Model ES631-LAN) with two different types of Ethernet Charge Modules (shielded and unshielded) was built. The analysis of real discharge waveforms is difficult. For that reason a proper calibration method with well-defined test loads is important to verify the functionality, to understand the current paths and the output parameters of the CDE test setup. A set of calibration loads including short, open, and 100 W differential load were built using 10 cm CAT5E UTP cables, and are shown in Fig 8.

The EIA 568B cable standard was used for all Ethernet wiring, Fig 9.

In the measurement setup the oscilloscope was set to capture the waveforms: Channel 1-voltage on line 5, Channel 2-current on line 5, Channel 3-voltage on line 4, and Channel 4-current on line 4. The voltage probes were 1010:1 (5 kW/50 W resistor bridge = 101:1, plus 20 dB attenuator). And the current probes were 20:1 (5 V/A plus 40 dB attenuator). The CDE Controller in all tests was set to 500 V, and depending on the test configuration the Charge Module and DUT may have been grounded.

Setup 1 consisted of a short connected to CDE Controller output, one differential pair with one side grounded and preconnected to the load, and a 100 meter Charge Module using S/UTP cable with the chassis not grounded. The setup and measurement waveforms are shown in Fig 10. From the simplified circuit, after the relay is closed in line 5, we expect a large current flowing from line 5 to line 4 over the differential 100 W transmission line structure and the peak current should be 5 A (500 V/100 W). From the waveforms it can be confirmed that the current waveform starts with 5 A peak. Then the waveform shows significant cable loss as the waveforms rapidly decay. After the current reaches the cable ends, reflections occur due to mismatches and several reflections happen until the total signal approaches zero. The voltage is a RC discharge waveform through the voltage measurement path.

Setup 2 is similar to setup 1 except the charge module chassis is connected to ground. The setup and measurement waveforms are shown in Fig 11. As can be seen, the current waveforms are the same as the first setup, but the voltage waveform RC time constant is much larger due to the grounding of the Charge Module chassis.

Setup 3 consisted of an open load connected to the CDE Controller output, one differential pair with one side grounded and pre-connected to the load, and a 100 meter Charge Module using S/UTP cable and chassis grounded. The setup and measurement waveforms are shown in Fig 12. There is little displacement current as the load is an open, and the voltage on line 5 is 494 V peak, which is very close to the charge voltage.

Setup 4 consisted of a 100 W load (with center tap between two 50 W resistors grounded) connected to the CDE Controller output, one differential pair with one side grounded and preconnected to the load, and a 100 meter Charge Module using S/UTP cable and chassis grounded. The setup and measurement waveforms are shown in Fig 13. With the 100 W load in place the current waveform magnitude drops to half of that measured with the short as in setups 1 and 2, and there are no reflections.

Except for the shape and magnitude of the measured calibration waveforms, the time delay of the measurement is also important to understand, in particular, which part of the waveform is due to the 100 W transmission line extension, and which part is due to the DUT. The waveforms shown in Fig 14 are with the CDE Controller connected to a CAT5E UTP cable only. The current waveform shows the 100 W transmission line extension first, then the open end. The real measurement of the DUT starts at the time where the open is shown.

E. Test of the CDE System on Ethernet Systems

Two 10/100Mbps Ethernet DUTs were tested with the CDE test system as shown in Fig 15. The test parameters are: CDE source voltage of 1 kV, a 100 meter Charge Module using S/UTP cable, and oscilloscope channels are scaled to 1 A/div. The first pin discharge waveform is captured and compared between unit A and unit B. Unit B has a much smaller current peak and higher current duration. This is mainly because the common mode impedance of unit B is much smaller than unit A.

Most systems using the Bob Smith Termination are almost fully charged after the initial discharge, so the current magnitude of the 2 nd – 8 th discharges are too small compared to the first one. This is not discussed here.

A Power over Ethernet (POE) system, having more complex termination was also tested. The measurement waveforms are shown in Fig 16. When the first pin contact DUT, first discharge current is generated in common mode through this pin. Then when the other wire in the same twisted pair contacts DUT, another discharge current is generated in differential mode through this pair. Both discharge signals could be transferred from termination to PHY circuit leading to damage in the Ethernet system.

IV.CONCLUSION

In this article, several important physics for CDEs have been discussed, a general CDE test and measurement solution developed, and some test results with well-defined structures and a few real world Ethernet systems are presented and discussed.

The next steps for CDE related test and measurement would be modeling the overall test system with different terminations, and running more tests with Ethernet systems to understand the design principle for CDE.

ACKNOWLEDGMENT

We would like to thank the EMC Laboratory, Missouri University of Science and Technology for the partnership of CDE related study and research and Cisco for the partnership in CDE related tests and measurements.

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TN006 Advanced Frequency Compensation Method for VF-TLP Measurement (up to 10 GHz)

TN006_P09 ESDEMC Frequency Compensation of VF-TLP Voltage Measurement Flow Diagram

 TN006 Advanced Frequency Compensation Method for VF-TLP Measurement (PDF)

1. Objective

The objective of this article is to demonstrate a frequency compensation technique for measuring the current and voltage of a device under test in a Very Fast Transmission Line Pulser (VF-TLP) test environment. The current measurement utilizes Non-Overlapping Time Domain Reflectometry, which is useful for On-Wafer testing because the measurement can be made with low profile small pitch probes, such as the Picoprobe Model 10. Further, to increase the bandwidth of the current measurement over common techniques, such as current transformers with 1GHz bandwidth, the method utilizes a resistive Pick-Off. The Pick-Off can be finely tuned to have as little insertion loss as possible, thereby enhancing the bandwidth. Although this method can also yield a DUT voltage measurement, the result suffers from numerical errors for low ohmic devices. A separate, direct measurement is presented that will demonstrate an extremely accurate voltage measurement that also utilizes frequency compensation.

 

2. Measurement Setup

Very Fast Transmission Line Pulse or VF-TLP testing is a difficult measurement to perform well. This is a high bandwidth measurement and all connections must be completed as well as possible to maintain the characteristic impedance of the system (typically 50 ). This translates into ensuring that any probe connections are well matched, and any connectors/adaptors are of the highest possible quality. Further, due to how Non-Overlapping TDR measurements are implemented, there are great benefits from using low loss cables, which are very expensive.

The overall measurement setup is depicted in Figure 1, where it can be seen to the far right hand of the figure that the system can accommodate a variety of DUT connection methods. In particular, the pulse is applied to the DUT by the Pulse In connection, and a direct voltage measurement is taken at the Vm connection. A true Kelvin measurement can be done using two probes, providing a good On-Wafer measurement solution. Also seen in the figure are an ES 621 Transmission Line Pulser, a Pick-Off tee, a leakage control module (A621-LTKSEM), a Source Meter Unit (SMU), and an Oscilloscope. Encircled numbers denote where frequency domain measurement points are located for the Non-Overlapping TDR current measurement. Under normal pulsing conditions, the leakage control module connections are in the Normally Closed (NC) positions. And during leakage current measurement conditions, the module is in the Normally Open (NO) positions. The NO position connects the DUT to the SMU, and disconnects the voltage measurement resistor Rv. A photograph of the setup is shown in Figure 2.

Figure 1 ESDEMC ES62X Series VF-TLP Measurement Setup
Figure 1 ESDEMC VF-TLP Measurement Setup

 

Figure 2 ESDEMC ES62X Series VF-TLP Delay Line Cable Arrangement
Figure 2 ESDEMC VF-TLP Delay Line Cable Arrangement

2.1 Current Measurement

A simplified figure highlighting the Non-Overlapping TDR connections of the measurement is shown in Figure 3. From the left, a TLP connects to Port 1 of the cabling layout. The V+ indicates the positive outgoing wave from the TLP. Next in line is the resistive Pick-Off, where the incident or (V+M) measurement is taken as V+ propagates toward the DUT. After reaching the DUT, a reflected wave (V-L) propagates back toward the Pick Off to be measured as V-M. The cable between the Pick-Off and the DUT is labeled the Delay Line. This is because the length of this cable must be long enough to delay the reflected wave from reaching the Pick-Off before the incident wave has fully passed. This can be guaranteed if the Delay Line is at least two times longer than the pulse width. The Delay Line length and the need for low loss cables typically results in pulse widths no longer than 10 ns for this measurement method.

ESDEMC ES62X Series Non-Overlapping TDR connections
Figure 3 ESDEMC VF-TLP Non-Overlapping TDR connections

The encircled numbers (○1, ○2, and ○3) in Figure 3 represent where the frequency compensation measurements must be made. In particular, S21, S31, and S32 must be measured and saved for future use for each measurement setup. If any cables or attenuators, or the Pick-Off are changed, then the S-parameters must be re-measured. The leakage control module must be included in the measurement, and put in the normally closed state. The magnitude of the three S-parameters for a typical setup are shown in Figure 4. It would be desirable for the insertion loss of the cabling and Pick-Off to be 0 dB across all frequencies, allowing the full TLP output pulse to be applied to the DUT. However, real low loss cables can have a few dB of attenuation at 10’s of GHz. For the measured setup the increased loss is most likely from the Pick-Off, and the SMA connectors between the ports for connecting the leakage relay and the DUT. Another item to note is that the S21 measurement is relatively flat.

Magnitude of S-parameter measurements for the Non-Overlapping TDR setup
Figure 4 Magnitude of S-parameter measurements for the Non-Overlapping TDR setup

The other two S-parameter measurements are very similar, and this is to be expected because other than S32 having the longer Delay Line in the path, the connections are identical. The ripple in the magnitude measurements are due to reflections in the connections. The ripple is approximately 1 dB to 1 GHz. How these measured S-parameters are used will be presented in Section 3.

2.2 Voltage Measurement

As stated earlier, the Non-Overlapping TDR measurement does yield a DUT voltage measurement. However, the measurement suffers from numerical errors for low ohmic devices. This is due to the Transmission Line theory math used in the processing of the captured data, and will be explained in greater detail in Section 3. A good measurement of the DUT voltage can be achieved by a separate, direct measurement, and a simplified connection diagram for this is shown in Figure 5.
This measurement is typically very accurate with just using the probe ratio and attenuator value to calculate the DUT voltage. However, with VF-TLP type measurements having higher bandwidth restrictions, a more accurate measurement can be achieved by using frequency compensation. Like Non-Overlapping TDR, the cable loss, attenuator value and connection quality can all be represented and compensated for by capturing the S21 of the measurement system. The magnitude of the S21 measurement taken for the system is shown in Figure 6.
VF-TLP Direct Voltage Measurement Setup

Figure 5. VF-TLP Direct Voltage Measurement Setup

 

Magnitude of S-parameter measurements for the Voltage Measurement
Figure 6 Magnitude of S-parameter measurements for the Voltage Measurement

For reasons that will be explained in the next section, the probe connection for the measurement in Figure 6 is the PCB, or upper right hand sub-figure, in Figure 1. The measurement is relatively flat to 1 GHz.

 

3. Frequency Compensation

Processing of the captured data requires loading of the S-parameter data into the TLP measurement control code. This is easily accomplished using the Touchstone file format that all network analyzers support. The core of the processing in this method is done in the frequency domain, which means that the measured time waveforms must be transformed to the frequency domain. Since it is nearly impossible to ensure that the time record length is identical to the measured S-parameters, interpolation must be done to obtain equal length data sets.

A flow diagram for the Non-Overlapping TDR measurement for IDUT is shown in Figure 7. At the upper left hand of the figure is shown a captured Non-Overlapping TDR waveform plot. In the plot, the left hand pulse is the Pick-Off measured incident pulse (V+M), and the right hand pulse is the Pick-Off measured reflected pulse (V-M). The next step in processing gets the data prepared for transforming to the frequency domain. In this step the incident and reflected pulses are separated, Windowed, Filtered, and Interpolated. In particular, the pulses are separated at the Cut Point, which is arbitrary, and merely needs to be in between the two pulses. If the Delay Line is altered or the pulse width changed, the Cut Point should be verified to be in an adequate position. Windowing is required to force to zero the beginning and ending of the time record to ensure that the captured data appear periodic in regard to the FFT. If this is not done, the FFT result will suffer from spectral leakage. Next, if desired, the data can be filtered. In the results presented herein there was no filtering of the data. Finally, the time and frequency domain data are interpolated.

The next step in the flow diagram is to transform the time data by Fast Fourier Transform (FFT). There is other mathematical manipulation not shown herein, but the math is illustrated in the next step of the flow diagram. This manipulation translates the two Pick-Off measurements (V+M and V-M) to the Load/DUT. In particular, the measured incident wave (V+M) must be translated back to the TLP (divide by S31), and then translated to the Load (multiplication by S21), yielding V+L. Since the measured reflected wave (V-M) only traverses between the Load and the measurement port, it only requires translation back to the load by dividing by S32, yielding V-L.

ESDEMC VF-TLP Non-Overlapping TDR Processing Flow Diagram
Figure 7. ESDEMC VF-TLP Non-Overlapping TDR Processing Flow Diagram

Time domain representations of the incident and reflected waves at the Load are then obtained by Inverse-FFT (IFFT). The two waveforms are shown in the plot to the left of the IFFT flow diagram step, and a zoomed in version is shown in Figure 8. Notice that there is a time difference between these two pulses. The S-parameter measurements should have taken care of this time difference, and given the exact same connections they would have. However, since SMA adaptors must be used to connect to the various different ports, all the measurements could not be placed at the calibration plane. Fortunately, the difference is short (typically pico-seconds) which can be accounted for by subtracting the time from the reflected pulse.

V+L and V-L waveforms (Zoom).
Figure 8. V+L and V-L Waveforms (Zoom).

Finally, the Load current or IDUT can then be calculated as shown in the last step of the flow diagram. Notice for low ohmic devices the resulting pulses are comparable in magnitude and in opposite directions. This combination is good for determining the current as the result is the addition of two numbers of comparable size. This is then divided by the characteristic impedance to obtain the current. As stated previously, this is not a good scenario for measuring the DUT voltage. Considering the same pulses, of comparable magnitude and opposite directions, the result for the voltage is the subtraction of two similar numbers, and potential for greater error. This method works great for voltage measurements of high ohmic devices, but for similar reasons the current measurement would suffer.

Processing for the direct voltage measurement is very similar to the current measurement, and the flow diagram is shown in Figure 9. The data is Windowed, Filtered (if desired), and Interpolated before being transformed by FFT. The frequency domain manipulation merely translates the measurement recorded at the oscilloscope back to the Load by dividing by S21 of the measurement path. Shown in the upper left, and bottom left hand of Figure 9 are the raw and resulting voltage at the DUT waveforms, respectively. Notice how the compensation removed the excessive ringing on the voltage measurement introduced by the probe.

ESDEMC VF-TLP Voltage Measurement Flow Diagram
Figure 9. ESDEMC VF-TLP Voltage Measurement Flow Diagram

4. Measurement

The goal of the method described above is to obtain the best possible, high bandwidth measurement possible, and the method utilizes Frequency compensation to try and achieve this goal. To demonstrate the ability of the technique a comparison of two different voltage measurements, recorded simultaneously, was performed. To do this a 1  resistor was mounted onto a PCB along with a measuring resistor (Rv), as demonstrated in the upper right hand of Figure 1. There is one exception to the connections of Figure 1 in that the addition of a Thru port that can be fed directly to the oscilloscope has been added. A schematic and photograph of the PCB are shown in Figure 10. The DUT is connected from Pulse In to ground, making the effective DUT a parallel combination of the 1  resistor with the oscilloscope input impedance (1 Ohm||50 Ohm). The Thru side measurement is directly connected to the oscilloscope channel 3 with a 30 dB / 18 GHz attenuator. The Thru measurement is compensated for by value of the attenuator only.

Photo of VF-TLP DUT test PCB
Figure 10. Photo of VF-TLP DUT test PCB

To truly test and understand the ability of the system, a brief introduction into the pulse shape characteristics that will be used to pulse the DUT are presented. First, the ES 621 TLP can produce a very clean and fast rising pulse, as depicted in Figure 11. The measurement was performed with a Tektronix MSO 72304DX (23 GHz/100 GSa/s) oscilloscope, a short 18 GHz cable and attenuator. As can be seen in the lower left hand of the figure, the average rise time measurement is approximately 60 ps, and the average pulse width measurement is approximately 1.04 ns. Further, the overshoot is small and settles quickly.

ES 621 Vf-TLP output, 60 ps rise time, 1ns pulse, with 23 GHz Oscilloscope
Figure 11. ES 621 Vf-TLP output, 60 ps rise time, 1ns pulse, with 23 GHz Oscilloscope, Measured in ESDEMC Headquarter Rolla, MO, USA 2014/08/28

 

Shown in Figure 12 are results for a current measurement. The Black trace is the raw result. By raw, it is meant that the final measured current value is determined by aligning the incident and reflected waveforms in time, scaling them by the Pick-Off probe value and attenuator in the measurement path, and then using the equation at the bottom of the flow diagram in Figure 7. The Red trace is the same measurement, but it is the result after the frequency compensation method described above. As can be seen the two measurements are in good agreement in regard to general shape and amplitude. But, the frequency compensated measurement removes artifacts introduced by the measurement probe, such as the high frequency ripple at the beginning of the current pulse.

ESDEMC VF-TLP Raw and Frequency Compensated Current Measurement
Figure 12 ESDEMC VF-TLP Raw and Frequency Compensated Current Measurement

Shown in Figure 13 are results for a voltage measurement. The Black trace is the raw direct voltage measurement, scaled by the probe factor and attenuator value only. The Red trace is the same measurement, but it is the result after the frequency compensation method described above. The Blue trace is VThru and is the result of the direct voltage measurement and a 30 dB / 18 GHz attenuator as the only compensation. As can be seen, the Red and Blue traces match very well, supporting the frequency compensation technique does an extremely good job in obtaining the voltage measurement.

Raw, Frequency Compensated, and Thru Voltage Measurement
Figure 13. Raw, Frequency Compensated, and Thru Voltage Measurement

5. Conclusions

The objective of this article was to demonstrate a frequency compensation technique for measuring the current and voltage of a device under test in a Very Fast Transmission Line Pulser (VF-TLP) test environment. It was shown that by incorporating the S-parameter measurements of the test setup into the processing routine that an extremely good voltage measurement could be obtained. In particular, a high bandwidth direct voltage measurement was used to verify the VF-TLP voltage measurement. Similarly, the compensation method was used to obtain the device current from the Non-Overlapping TDR measurement.

ESDEMC 60ps rise-time 1ns Pulse VF-TLP Measurement
ESDEMC VF-TLP Measurement of 60ps rise-time 1ns VF-TLP Pulse

Appendix: Measurement Equipments

Tektronix MSO 72304DX, 23 GHz/100 GSa/s, Oscilloscope
ESDEMC ES621 Transmission Line Pulser System
ESDEMC A621-LTKSEM Leakage Control Module
ESDEMC FS312 VF-TLP Pick-Off
Suhner Sucoflex 100 high performance microwave cable
Micro-Coax UTiFlex Ultra low loss microwave cable
Mini-Circuits SMSM Cable
Gore-Tex UltraLow Loss Coax Cable

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PB2013.08 Effect of Cooling on the Probe System Sensitivity for Low Signal Strength RFI Problems

Download PDF – Effect of Cooling on the Probe System Sensitivity for Low Signal Strength RFI Problems

Abstract—Only highly sensitive probe systems can detect the weak field strengths that cause radio-frequency-interference (RFI) problems typically found within cell phones. The sensitivity of the probe systems depends on the probe factor and on the noise floor. The effect of cooling by liquid nitrogen on the received signal strength and the noise floor of three resonant probe systems has been investigated. They operate at the GSM, GPS, and WiFi frequency bands. Cooling increases the Q-factor of these resonant probes, increases the received signal, and lowers the noise floor. The sensitivity of the system, defined as the signal strength at which the Signal-to-Noise Ratio is equal to 0 dB improves by 3-6 dB.
Keywords— Quality factor, radio-frequency interference (RFI), resonant magnetic field probe, signal-to-noise ratio.

I. INTRODUCTION

High-frequency harmonics generated from the digital ICs and switched power supplies may couple into the antennas which are integrated into mobile systems such as cell phones. The noise of the harmonics is added to the natural noise floor of the receiver and overwhelms weak signals which should be received by the receiver [1], [2]. Near-field probes [3], [4] and scanning technique are effective tools to investigate noise field distribution of circuits at high frequency and to locate the source of the EMI problems at circuit and chip level [5], [6].

Broadband probes are useful tools for initially locating strong noise sources. Magnetic near-field probes for high frequency band up to tens of GHz have been designed by suppressing the inherent resonances of a circular loop [7], and by minimizing the cross-sensitivity of electric near-field [8]. However, when the interfering electromagnetic fields are weak, it is difficult for broadband probes to measure signals of low signal-to-noise ratio (SNR). Probes with larger loop size can improve the SNR but degrade the spatial resolution. Since the noise source of interest is usually in the narrow bands, narrowband resonant probes can detect lower SNR signals than their broadband counterparts because of their higher sensitivity [9], [10]. In the applications of nuclear magnetic resonance (NMR), the SNR is further improved by lowering the coil temperature with liquid helium, since the noise is dominated by the thermal noise of the receiver coil in a welldesigned NMR spectrometer [11], [12].

In the following paper, three resonant magnetic field probes are cooled with liquid nitrogen to investigate the effect of cooling on the probe system sensitivity, where only the probes are cooled. The probes operate at the GSM, GPS, and WiFi frequency bands. The sensitivity is defined as the signal at which the SNR reaches 0 dB within a bandwidth of 1 Hz. The experiment and results are described in detail in the following sections.

II. PROBE UNDER INVESTIGATION

The probe for investigating the effect of cooling is based on a differential-loop resonator shown in Fig. 1 and a Marchand balun based impedance transformer shown in Fig. 2. The theory, design and the dimension of the probe have been introduced in detail in [10]. The probe uses a four-layer FR4 printed circuit board. The initial design selected FR4 as substrate due to its low cost. The top and bottom layers in Fig. 1 are signal return planes and shielding planes minimizing unwanted field coupling. The LC resonator consists of a parallel-plate capacitor in parallel with an inductor formed by the probe loops. The resonant frequency of the probe is set by the geometry of the loops and the capacitors. The resonator is terminated with a Marchand balun based impedance transformer. The impedance transformer converts a high impedance Zl of 1800 Ω to a low impedance Z0 of 50 Ω. The high impedance is loading the resonator but allowing for a high Q-factor. The low impedance matches to the input impedance of measurement instruments such as the spectrum analyzer for maximal energy transfer. The transformer also converts differential signals to a single-ended signal, where the differential signals originate from the mirror-symmetrical design of the resonators on the second and third layers. Drawing of the fabricated resonant magnetic field probe at GPS frequency band are shown in Fig. 3. The assembled probe is about 6.5 cm long from the SMA connectors to the probe tip.

III. MEASUREMENT SETUP

Fig. 4 shows the measurement setup for investigating the effect of cooling probes by liquid nitrogen. The tracking generator of the spectrum analyzer outputs a sweeping sinusoidal signal to drive the 50 Ω microstrip trace terminated by a matched load. The probes are placed 2 mm (H = 2 mm, in Fig. 4) above the trace. This height is in the same order of the height commonly used in the near field scanning. The signal is amplified by a three-stage amplifier and then received by the spectrum analyzer. The amplifiers are connected to the probe output port directly.

The first stage amplifier, Amp1, is a narrow band low noise amplifier (LNA). The second and third stage amplifiers, Amp2 and Amp3, are broadband. The noise figures and gains are listed in Table I at the frequency bands of interest. The system noise figure attributed to the noise contribution of each stage amplifier in the cascade follow the Friis equation:

where NF is the system noise figure, NFi (i=1, 2, 3) is the noise figures of three amplifiers, and Gi (i=1, 2, 3) is the gain of three amplifiers. All the probes are matched to 50 Ω at their center frequencies. Therefore, the noise figure of amplifiers measured in a 50 Ω system is a reasonable estimate for calculation in Eqn. 1. All the values in Eqn. 1 are linear scale, not in decibels. The system noise figures are 0.6 dB, 0.9 dB, and 1.1 dB for GSM, GPS, and WiFi frequency bands, respectively. The system noise figure is mainly influenced by the LNA, which has a low noise figure and relatively high gain.

IV.COOLING EFFECT ON THE PROBE Q-FACTOR

The probe’s Q-factor was measured at room temperature and after cooling the probe in the liquid nitrogen. Although liquid nitrogen is not readily available in a real-word EMC laboratory at present, it is easy to buy a tank of liquid nitrogen. One might pour the liquid nitrogen onto the probe using a pipe during the real-world measurement. In the initial test, however, the probe is immersed in nitrogen. During the cooling, only the PCB of the probe has been placed into the liquid nitrogen for three minutes. The probe can stay cold for approximately two minutes after it is taken out from the liquid nitrogen. Then the probe was placed 2 mm (H = 2 mm) above the trace to measure signals, as shown in Fig. 4.

Cooling the probe increases the resonance frequencies (see Fig. 5). Take the GPS probe as an example. The resonance frequency increases by 46 MHz. The 3 dB bandwidth decreases by 29 MHz. The probe’s Q-factor, Q, is calculated by

where fc is the center frequency of the resonance, BW3dB is the 3 dB bandwidth. The Q-factor when the probe is at room temperature is 11.3. After the cooling, the Q-factor is 14.7. The Q-factor increases by 3.4. Similar results for GSM and WiFi probes are listed in Table II. Both a small increase in the resonance frequency, and lower losses result in an increase of the Q-factor.

From the power point of view, the power received by the spectrum analyzer increases by 1-3 dB at the center frequency. At the same time, the loss in the probe reduces. The thermal noise in the conductors for the signal traces and the ground planes decreases with decreasing temperature. The dissipated power becomes smaller, leading to the higher Q-factor.

V. EQUIVALENT MAGNETIC FIELD STRENGTH OF NOISE FLOOR

The minimal detectable signal can be defined as the signal at which the SNR reaches 0 dB within a bandwidth of 1 Hz, when the noise power is equal to the noise power density. Real bandwidths are much larger. However, it is easy to denormalize to any requested bandwidth from 1 Hz. To calculate the noise equivalent signal, the system probe factor, SPF, and the noise power density, Pn,r, at the output of the probe system is needed. The noise power density is read directly from spectrum analyzer R&S FSV. The system probe factor is obtained from calibration.

During the calibration, the matched microstrip trace is driven by a source with a power level of Pd at the resonance frequency fc . The input impedance looking into the microstrip trace at the driving port is Rin = 50 Ω. The voltage at the driving port is

The microstrip trace generates a magnetic field, which is measured by the probes. The probes output a power, Pr , to the spectrum ananlyzer. Since the input impedance of the spectrum analyzer is RSA = 50 Ω, the receiving voltage measured by the spectrum analzyer is

Therefore, the voltage transfer coefficient TV from the driving voltage Vd to the receiving voltage Vr is

We simulated the same matched microstrip trace driven by one Volt, and the magnetic field above the trace normalized to one Volt is Href in unit of (A/m)/V. In the measurement, the trace is driven by a voltage of Vd. The magnetic field strength, Hm, measured by the probe would be

The system probe factor, SPF, is defined as:

Once the system probe factor SPF is known, the magnetic field strength Hm can be calculated if the receiving voltage Vr is given. When the SNR of the signal probe measures is 0 dB, the probe outputs a noise power of Pn,r within a bandwidth of 1 Hz. The voltage measured by the spectrum analyzer then is

The equivalent magnetic field strength of the noise is

The measured equivalent magnetic field strength is listed in Table III, comparing the cooled and the room temperature cases. The cooling has changed the property of probe materials slightly. This change is reversible.

The driving power Pd is not the same when the probe is cooled and at room temperature. This is caused by a small frequency dependence of the cables losses, as the resonance frequencies shift slightly. It is also caused by a small variation of the tracking generator’s output power at different frequencies. However, the small difference of driving power has no effect on the system probe factor, since the system probe factor is normalized with respect to the driving power, normalizing to 1 volt driving voltage at a 50Ω resistor.

If we take the GPS probe as an example, the received signal increases by 0.8 dB when the probe is cooled. At the same time, the noise power density decreases by 3.89 dB/Hz. The higher sensitivity and the lower noise power density result in an increased sensitivity of 4.69 dB. When this value is converted to the equivalent field strength, the minimal detectable equivalent field strength is 4.8 nA m /)/( Hz lower when the probe is cooled. Similar improvements are seen for the other probes when cooled.

VI.CONCLUSION

The change of the system sensitivity by cooling near field probes for the GSM, GPS and WiFi bands using liquid nitrogen has been investigated. We observed increasing Qfactor, higher sensitivity, larger output power, and lower noise power density of the probe system at lowered temperature. The sensitivity of the system, defined as the signal strength at which the SNR is equal to 0 dB improved by 3-6 dB. The cooled probe system is helpful for detecting low electromagnetic fields coupled to RF antennas.

ACKNOWLEDGMENT

This material is based upon work supported by the National Science Foundation under Grant No. 0855878.

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PB2012.09 An application of utilizing the system-efficient-ESD-design (SEED) concept to analyze an LED protection circuit of a cell phone

Download PDF – An application of utilizing the system-efficient-ESD-design (SEED) concept to analyze an LED protection circuit of a cell phone

An application of utilizing the system-efficient-ESD-design (SEED) concept to analyze an LED protection circuit of a cell phone
Tianqi Li #1, Junji Maeshima *2, Hideki Shumiya*3, David J. Pommerenke#4, Takashi Yamada*5, Kenji Araki*6

# EMC laboratory, Missouri University of Science and Technology, 4000 Enterprise Dr., Rolla, MO, 65401, USA, tlx6f; 4 davidjp@mst.edu
* Sony Corporation, Sony City, 1-7-1 Kounan Minato-ku, Tokyo, 108-0075, Japan
2 Junji.Maeshima; 3 Hideki.Shumiya; 5 TakashiB.Yamada; 6Kenji.Araki@jp.sony.com

 

Abstract—An LED circuit of a cell phone is analyzed using the System-Efficient-ESD-Design (SEED) methodology [1]. The method allows simulation of the ESD current path, and the interaction mechanisms between the clamp and the on-chip ESD protection circuit. The I-V curve and the non-linear behavior under high current pulses of every component including R, L, C, and ferrite beads are measured and modeled. By combining all of the component models, a complete circuit model is built for predicting the circuit behavior and damaging threshold at a given setting-voltage of a Transmission Line Pulser (TLP).

I. INTRODUCTION

To build lower cost systems with better ESDresistant design at the system level it is important to understand the ESD current path, and how an IC’s on-chip protection circuit interacts with outside clamp circuits [2]. For example, if the on-chip ESD circuit of an IO pin could provide enough protection, then any external protection components could be omitted to reduce cost. A more complex case would be if the on-chip ESD circuit could not meet the protection requirements and the off-chip protection circuit has a relatively large resistance, more ESD current would still flow through the IO pin’s internal ESD circuit and finally damage the IO circuit itself. In this case, the external protection circuit should be replaced with a different clamp with smaller resistance in order to protect the IO pin.

For this reason, the interaction between components, especially between different protection circuits inside a system needs to be thoroughly analyzed, to achieve a more efficient protection scheme at the system level [1]. This is the purpose of the SEED approach. Circuit modelling and simulation is a convenient approach for such SEED analysis. However, typical SPICE models of components cannot be used in these simulations because they usually only contain information for normal operating conditions, without responses to several kV pulses such as those seen in ESD strikes. In this project a TLP is used to measure transient IV characteristics of each component, and highvoltage-SPICE models are built based on the tested data [3].

In this paper, an LED circuit in a cell phone is chosen to demonstrate the SEED analysis approach. The schematic of the LED circuit is shown in Fig.1. Under typical working conditions the VCC pin outputs DC current that flows through the LED and is sunk by the IO pin. The driver IC controls LED turn-on and turn-off by changing the status of the output MOSFET. All other components such as capacitors and Zener diodes are used for ESD protection and other filtering purposes. A potential discharge point is at the LED, which is located near the cell phone’s keyboard.

A. Modeling the LED

The I-V curve of the LED has been measured using a TLP resulting in the SPICE model shown in Fig. 2. The model includes two parts: the normalcondition SPICE model which is provided by the device manufacturer, as well as switches for matching the transient I-V curve. The factory model is OK for emulating the device I-V curve in the positive voltage region, but does not conform to the I-V curve in the negative-voltage region. For this reason, two switches are used to correct the simulated I-V curve.

During the measurements, it was also found that the LED will be damaged if the current reaches +15A or -10A.

B. Modeling the Zener Diode

The Zener diode was modeled in a similar way. In the model which is shown in Fig. 4, diode 11 defines the I-V characteristics of the Zener under a negative pulse. Diode 10 and the switch determine the positive I-V characteristics. Diode 9 is used as a unidirectional switch.

A linear capacitance of 25 pF is also included. Its value is taken from the datasheet and verified through measurements.

The simulation results of this model (Fig. 5) show good agreement to measurements as well.

C. Modeling the IO Pin of the LED Driver IC

A reflection-based TLP system is used for insystem measurement of the transient I-V curve of the IO pin, which is modeled without knowledge of its internal circuit. Similarly, the model is a combination of linear and non-linear components. The non-linear behavior was measured by the reflection-based TLP system, and its linear part can be obtained by tuning the model parameters to conform to the measured S11. In this way, a complete model of the IO pin could be developed, as shown in the Fig. 6. R20 and C2 are these linear components which were obtained from the Sparameter measurement.

Similar to the Zener diode model, diode 7 defines the non-linear behavior of the device when a negative pulse is applied at the IO pin. Diodes 6 and 8 define the non-linear behavior when a positive pulse is applied to the IO pin.

A damage threshold of 22A was determined using a 13.5 ns pulse from the TLP to the IO pin. The transient I-V curve of the model is shown in Fig. 7.

D. Modeling the Ferrite Beads

Because ferrites are non-linear components, their equivalent inductances drop as through currents increasing, due to saturation effect. A non-linear model of the ferrite bead, as shown in Fig. 8, was obtained by defining its equivalent inductance as a function of current.

In this model, the linear parts include R1, C2 and R9, which are extracted from the impedance plot provided by the datasheet. The non-linear part of the ferrite model, the inductance as a function of current, was measured by a TLP, and modeled with following equation:

Where I stands for the current through the nonlinear inductor, L0 is the inductance value for I=0. Thus, for FB1 L0 equals to 60nH. Lsat stands for the saturated inductance which, for FB1, equals 20nH. The plot of the equation is shown in Fig. 9.

The model is validated by comparing simulation and measurement results, as shown in Fig. 10.

E. Modeling the Inductors

The inductors used in the circuit are assumed to be linear components, and the transient simulation result, as shown in Fig. 11, validates this assumption.

F. Modeling the Capacitors

The capacitors used in this circuit have anNP0 type dielectric, therefore it was expected that the capacitance would not change as a function of the voltage across the capacitor. Such expectation was validated by measuring capacitance variation with respect to voltage by using a TLP. These TLP measurements confirm that the NP0-dielectric capacitor can be modeled as a simple linear capacitor.

III. SYSTEM MODEL AND SEED ANALYSIS

A. The System Model

A system model was built by combining each of the experimentally obtained component models, as well as a TLP model as the source. The system model is validated through S-parameter measurements, as well as transient pulse measurements. The simulation result is compared to the measurement in Fig. 12. This comparison clearly shows that the injected 500 V TLP pulse is clamped to 9V by the protection circuit.

B. SEED Analysis

From Fig. 12, although it is known that the injected pulse is clamped to a low voltage, it is not known which one of the clamp circuit components is the primary clamping element. Additionally, it is not easy to predict what level of the injection pulse will damage the circuit, due to the fact that only a limited number of DUTs were available for real testing.

With the SEED method, the previous questions can easily be answered because it is possible to observe currents as they flow through various components in a simulation environment. In Fig. 13, it is clearly shown that more pulse current flows though the Zener diode during the first 10ns of an applied pulse before the protection diode inside the IO pin starts to conduct.

If the Zener diode is a more effective form of ESD protection we can ask if it is possible to remove FB1 before the IO pin to reduce cost. The simulation result in Fig. 14 shows that without the ferrite bead more current would flow through the IO pin, but not the Zener diode. Therefore, the ferrite bead has significant effect on the current that flows through the IO pin, and thus should not be removed.

SEED analysis may also tell us what the vulnerable parts in this circuit are, and how much margin left till the circuit would fail under a given injecting level, if the damage threshold of each component is known. For example, the simulation result in Fig. 15, shows that the current which flows though the LED is much larger than the current that flows through the IO pin. Therefore, for this circuit, the LED is more prone to damage than the driver IC, especially considering that LED device is usually placed at a location that has a greater chance to experience air discharge. It can be predicted that the LED will be damaged under 2000V TLP pulse because under this condition the LED’s through current reaches to 15A, which is its damaging threshold measured with 13.5ns TLP pulses.

IV.CONCLUSION

In this study, the SEED strategy is applied to analyze the ESD performance of a cell phone’s LED circuit. High current SPICE behavioral models of each component in the circuit were developed and validated against measurements. By combining these models with a TLP source model, major pulse-current paths, protection mechanisms, system transient response, and weak points of the protection circuit are revealed. These parameters can then easily be analyzed through simulation, instead of performing a large number of destructive measurements.

For next step, the TLP model can be replaced with an ESD gun SPICE model, so that we can predict the circuit’s response under real ESD gun contact discharge measurements. This may help circuit designers predict the ESD performance of a circuit before it is put in to production. This SEED strategy also facilities PCB level ESD protection design during initial product development, rather than traditional trial-and-error process.

ACKNOWLEDGMENT

This material is based upon work supported by the National Science Foundation under Grant No. 0855878, and supported by Sony Corporation of Japan.

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TN005 TEM Cell Measurement of 2.4GHz Device Radiation

Overlaid spectra in GHz TEM Cell Measurment

Download TN005 TEM Cell Measurement of 2.4GHz Device Radiation (PDF)

 

1. Objective

The objective of this article is to demonstrate how the EM601 TEM Cell can be used for measuring the spectrum of 2.4 GHz devices such as Bluetooth and WiFi.

EM601-5.5 DC-5.5 GHz IC Stripline TEM Cell
EM601-5.5 DC-5.5 GHz IC Stripline TEM Cell

2. Measurement Setup

With the large field injection area of 50 x 50 mm, the EM601 series of TEM Cells is readily suitable for measuring the spectrum USB Bluetooth and WiFi devices such as those shown in Figure 1. The only additional equipment required is a computer, for powering and activating the device, and a spectrum analyzer. For the measurements presented herein, an Agilent E4448A spectrum analyzer was used.

USB Bluetooth and WiFi devices
Figure 1. USB Bluetooth and WiFi devices

In order to fit the Bluetooth device into the cell, it was removed from its plastic enclosure and a cable soldered to its connector terminals. The modified device is shown in Figure 2. A copper clad PCB was used as the TEM cell cover, and an aperture the size of a USB connector was milled for mounting USB devices, or exiting a cable. Figure 3 depicts the Bluetooth device inside the cell, and its’ USB cable exiting.

Modified Bluetooth device TEM Cell Measurement
Figure 2. Modified Bluetooth device for TEM Cell Measurement
Bluetooth device mounted inside TEM cell
Figure 3. Bluetooth device mounted inside TEM cell

Measuring the WiFi device was simpler in that it readily fit into the cell, and only required a USB cable to be connected externally as shown in Figure 4.

 

WiFi Device mounted inside TEM cell
Figure 4. WiFi Device mounted inside TEM cell

 

3. Measurements

The measurements were taken with an Agilent E4448A 3 Hz – 50 GHz spectrum analyzer with the settings: 3 MHz RBW, 50 MHz VBW, 10.375 ms sweep time, 10 dB attenuation, 3 Hz start frequency, and 6 GHz stop frequency. Port 1 of the TEM cell was connected to the spectrum analyzer, and Port 2 was terminated in 50 . The first measurement taken was of the TEM cell fully covered and no device inside. The empty cell spectrum measurement is shown in Figure 5.

Empty TEM Cell measurement (Dynamic Range Check)
Figure 5. Empty TEM Cell measurement (Dynamic Range Check)

 

The measured spectra of the Bluetooth, and WiFi devices are shown in Figure 6 and Figure 7. For each device measurement they were connected to a computer and fully functional. The Bluetooth device was put into search for a new device mode.

Spectra of Bluetooth device
Figure 6. Spectra of Bluetooth device

 

Spectra of Wifi device
Figure 7. Spectra of Wifi device

A graph with all plots overlaid is shown in Figure 8. As can be seen, the devices both operate in the 2.4 GHz band, and there is potential for interference when both devices are present and operating.

Overlaid spectra in GHz TEM Cell Measurment
Figure 7. Overlaid spectra in GHz TEM Cell Measurement

4. Conclusions:

The EM601-5.5 TEM Cell is well suited for measuring GHz device spectra. Further, the TEM cell cover can be customized to suit any device that can fit into the large 50 x 50 mm cell of the EM601.

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PB2012.06 Nonlinear Capacitors for ESD Protection

Download PDF – Nonlinear Capacitors for ESD Protection

Hongyu Li, Victor Khilkevich, Tianqi Li, David Pommerenke, Missouri University of Science and Technology, USA;
Seongtae Kwon, Wesley Hackenberger, TRS Technologies, Inc., USA

Abstract – In order to protect electronic products from Electrostatic Discharge (ESD) damage, multi-layer ceramic capacitors (MLCC) are often used to bypass the transient ESD energy. Most
dielectric materials used in MLCC are nonlinear, since the dielectric constant decreases with increasing voltage, reducing the capacitance value, thus degrading the ESD protection effect. Using a large initial capacitance value will ensure sufficient ESD protection; however, the shunt capacitors also limit the signal bandwidth of the ESD-protected data channel, thus setting a maximal capacitance value at data voltage levels. This paper investigates the nonlinearity of capacitors and suggests improved tradeoff between ESD protection and data bandwidth by using the Antiferroelectric (AFE) capacitors as ESD protection. The dielectric constant of AFE material increases with increasing voltage. The voltage dependence of X7R and AFE capacitors are measured
using static and nanosecond transient measurements. The ESD protection effectiveness with different material capacitors are compared by simulation. Due to very limited availability of suitable
AFE material samples only hand-made capacitors have tested without investigating the long term stability of the material.

Index Terms— ESD protection, AFE material, nonlinear capacitor

I. Introduction

ESD is one of the most important reliability problems in an electronic product. In order to provide ESD protection to electronic products, decoupling capacitors and series resistors can be used as shown in Fig. 1. The capacitors absorb the injected charge, and limit the maxi

I. Introduction

ESD is one of the most important reliability problems in an electronic product. In order to provide ESD protection to electronic products, decoupling capacitors and series resistors can be used as shown in Fig. 1. The capacitors absorb the injected charge, and limit the maximal

showed no noticeable voltage dependence. The measurement fixture is shown in Fig. 4. The two cylindrical devices are the PIO capacitors.

B. Static Measurement Results for X7R Capacitors

Static measurement results for X7R capacitors are shown in Fig. 5. All four capacitors (4.7nF, 50V) showed similar behaviour. The capacitance decreases from 4.7nF to about 1nF at 400V DC bias. We observed no damage to the capacitors at 400V.

C. Static Measurement Results for AFE Capacitor

The measurement result for an AFE capacitor is shown in Fig. 6. The capacitance is about 3nF without any DC bias, and increases with increasing DC bias voltage before the transformation from the AFE phase to the FE phase. For this AFE sample, the transformation occurs at about 325V, causing a peak in its capacitance value of about 8.5nF at 325V. In the FE phase the capacitor acts as normal capacitor, and the capacitance decreases with increasing DC bias voltage. The capacitance drops back to 3.5nF at 500V.

IV. Transient Measurement

The nonlinearity of the capacitors can be seen clearly from the static measurement results. However, ESD is a transient process of nanosecond time scale. ESD currents typically have rise time of less than 1ns. However, the voltage and current rise times at the capacitor is limited by the capacitance value and the source impedance (about 300 Ohm for an IEC 61000-4-2 ESD generator at lower frequencies and around 100 Ohm at higher frequencies). The voltage and current rise time at a capacitor with hundreds pF or a few nF is generally between a few and tens of nanoseconds. Transient measurements investigate if the capacitance can react with sufficient speed to provide ESD protection.

A. Transient Measurement Method

In the measurement setup illustrated in Fig. 7, C represents the capacitor under test. A pulse with duration of 70ns and a rise time of 150ps generated by the Transmission Line Pulser (TLP) is injected into the capacitor under test through a microstrip transmission line. A loop formed by a trace and vias is embedded underneath the transmission line. The mutual inductance between the transmission line and loop is used to measure the derivative of the current flowing on the transmission line. The current is obtained by integrating the measured derivative of the current. The voltage across the capacitor is measured with an oscilloscope.

The measurements capture the current derivative and the voltage across the capacitor. The post processing obtains the current and the voltage derivative. Low pass filtering is used for noise suppression and de-trending is used to remove the effect of scope’s imperfect DC-offset on the integration of the current derivative.

B. Transient Measurement Results for X7R Capacitors

If the TLP is set to 1200V charge voltage it takes about 60ns to charge the capacitor to 450V, as shown in Fig. 8. The stress was repeated many times to assure the phenomena are stable. Results from three repeats are plotted in Fig. 8. The change of the capacitance versus time for X7R capacitors is shown in Fig. 9. The results show that the X7R capacitors react fast enough to the transient signal

Fig. 10 compares transient and static measurement results for X7R capacitors and the trend of the nonlinearity matches well.

C. Transient Measurement Results for AFE Capacitor

If the TLP is charged to 2500V, it takes about 60ns to charge the AFE capacitor to 400V, as shown in Fig. 11. Results from three pulses are plotted in Fig. 11. Those indicate good repeatability. The peak and the dip at the beginning and the end of the pulse are due the parasitic inductance in the measurement setup and the large rate of current change at the beginning and end of the TLP pulse. The measurements indicate an inductance of about 5.5nH for the AFE capacitor test setup. Only 1.3nH had been measured for the X7R capacitor (fig. 8). Its 0603 package allowed a lower inductance placement within the test setup. The change of the capacitance versus time for AFE capacitor is shown in Fig. 12. The result shows that the AFE capacitor reacts fast enough to the transient signal, allowing this beneficial property being used for ESD protection. Fig. 13compares the transient and static measurement results for the AFE capacitor and the trend of the nonlinearity matches well. The deviation above 300V may be caused by the limitation of the transient measurement method. Due to its large capacitance it was barely possible to reach 400V at the highest TLP charge line setting of 2500V as shown in Fig. 11, causing uncertainties in the capacitance estimation as the capacitance values are derived just at the beginning of the falling voltage edge.

V. Comparision of the Capacitors for ESD Protection

The effectiveness of the capacitors for ESD protection can be compared by simulation. The nonlinear capacitor models are based on the static and transient measurements.

A. SPICE Model for Nonlinear Capacitor

The Analog Behavioral Model is used to model the nonlinear capacitor, as shown in Fig. 14. The capacitor is modeled by a controlled current source, GVALUE in PSpice, whose current is defined by equation (2). The time derivative of the voltage is modeled by using the discrete derivative of time (DDT) function in PSpice. A voltage dependent capacitance is specified by using a look-up table based on the measurement. This table contains voltage-capacitance pairs picked from points on the measured curve. The voltage input is nonlinearly mapped from the voltage values in the table to the capacitance values. Linear interpolation is used between table values [9].

B. ESD Current Source Model

ESD generator is modeled using the equivalent circuit as shown in Fig. 15. This circuit models the current and the impedance of the ESD generator. Initially, the capacitors are charged until the switch initiates the breakdown. C4, L2, R4 and R5 set the initial rise time, R1 and C2 represent the interaction between the body of the ESD generator and ground. The main discharge constant (330 Ohm, 150pF) is formed by R3+R4+R5 and by C1+C2+C4. R6 represents the ESD target and the current flowing through it is shown in Fig. 16. In this example, the ESD generator is charged to 2000V initially.

C. Capacitors to Compare

Sample1 from the X7R capacitors is selected to compare to the AFE capacitor. Fig. 17 shows the capacitance normalized to their value at 0V. In the simulation both X7R and AFE capacitors are de-normalized to 1nF at 0V; therefore, both protection circuits have the same frequency response, but different protection behavior.

D. ESD Protection Effectiveness Comparison

The simulation circuit is explained in Fig. 18. The device under protection is assumed as an IC. Diode ESD protection is commonly used in IC design. Here only these diodes are modeled and the IC’s internal structure is omitted. The destruction threshold of the commonly used human body model (HBM) test level is 2000V. The IC level HBM test and the IEC 61000-4-2 testing are both based on discharges from a human body, thus their total charge and pulse length are similar. The source impedance for the HBM testing is 1500Ω. Passing the HBM test ensures a robustness of the IC input for currents up to about 1.3A which we assume as the failure threshold of the simulation. Another consideration leads to the usage of a series resistor. Without such a resistor the internal ESD protection of the IC would compete with the PCB based protection, possibly leading to the IC protecting an external ESD protection. A series resistor allows for a sufficient voltage drop separating both protection methods electrically. A resistance of 200Ω is selected in this simulation. ESR and ESL represent the effective series resistance and inductance of the capacitor respectively, whose values are set to 100mΩ and 1nH. The circuit is excited by the ESD generator shown in Fig. 15. The ESD generator is charged to 2000V initially.

The critical current flowing into the IC is shown in Fig. 19. Using the X7R capacitor, it reaches 1.6A which is above the destruction threshold ensured by 2000V HBM testing of 1.3A. In contrast the increasing capacitance of the AFE capacitor limits the peak current below 0.9A.

In designing a protection circuit, the 0V capacitance is determined by the required signal bandwidth. The protection effect is determined by the capacitance ratio between the capacitance at the highest voltage reached during ESD and its 0V capacitance. The larger the ratio is, the better the ESD protection will be. For the X7R capacitor this ratio is usually about 0.3, while it reaches about 3 for the AFE capacitor investigated in this research. This larger ratio allows an improved trade-off between ESD protection and bandwidth.

VI. Conclusion

X7R capacitors are often used as ESD protection. In this application the voltage across the capacitor will surpass the rated voltage, often reaching 400V on a 50V capacitor. The voltage dependence of capacitors with two different dielectric materials, X7R and AFE, are measured using both static and transient measurement methods. Similar capacitance changes have been observed for static voltages and transient voltage changes. The X7R capacitors lose most of their capacitance while the AFE capacitors increase their capacitance values as the voltage increases up to a certain point as shown in Fig. 13, for example. This increasing nonlinearity of AFE capacitor improves ESD protection at a given signal bandwidth. The improvement of the ESD protection has been quantified with simulation. The temperature dependence of the AFE’s capacitance and the long term reliability of AFE capacitors have not been investigated.

Acknowledgement

This material is based upon work supported by the National Science Foundation under Grant No. 0855878. EMC

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TN003 ESD Simulator Calibration Method for IEC61000-4-2 & ISO10605

TN003_P01 ESD Simulator Calibration setup

Download ESDEMC_TN003 ESD Simulator Calibration Method for IEC61000-4-2 & ISO10605 (PDF)

1. Calibration Objective

The objective of this report is to present calibration parameters required for ESD simulators, verify their performance, and compare the results to the requirements of the IEC 61000-4-2 or ISO10605 standard.

2. Requirements and Equipment

2.1 Tip voltage Verification

Both IEC61000-4-2:2008 and ISO10605:2008 specify that the tip voltage or the HV source of an ESD simulator must be verified with a high voltage meter or electrostatic voltmeter.

  IEC61000-4-2:2008 ISO10605:2008
Voltage calibration Up to ± 15 kV Up to ± 25 kV
Tolerance < ± 5% < ± 5%

Table 1 Simulator tip/HV source voltage tolerance.
When using a contact high voltage meter (>100 G Ohm input impedance) for calibration, the HV source will need to continuously charge the tip to maintain the voltage level, otherwise the meter will discharge the tip and the voltage reading will decrease gradually. ES105-100 High-Impedance High-voltage Meter from ESDEMC satisfies the requirements for HV calibration (>100 G Ohm input impedance and measures up to 100 kV with less than 2% tolerance).

Because the ESD simulator tip is sharp and small, the capacitive coupling between the tip and a non-contact electrostatic meter is weak, and therefore <± 5% accuracy may not be achievable. Further, most precision non-contact electrometers do not measure to ±25 kV. This would require a coupling factor for calibration between the discharge tip and the sensor of the non-contact electrometer. ES102 Vibrating Capacitance Electrometer from ESDEMC satisfies the requirements for the HV calibration (non-contact measurement with self-calibration up to 1 kV). With the coupling factor integrated with the externally calibrated HV source a measurement range of 200 V to 200 kV with less than 2% tolerance is obtained.

2.2 Contact discharge mode current verification

Both IEC61000-4-2:2008 and ISO10605:2008 standards specify that the ESD contact mode discharge current waveform meet the requirements listed in Table 2.

 

Standards IEC61000-4-2:2008 ISO10605:2008

 

RC Network 150 pF  330 Ohm

 

150 pF  330 Ohm

330 pF  2000 Ohm

150 pF  330 Ohm

330 pF  2000 Ohm

 

Voltage Range CD 2 kV – 8 kV

AD 2 kV – 15 kV

 

CD 2kV – 15 kV

AD 2kV – 25 kV

First peak

Tr

 

0.6  – 1.0 ns 0.7  – 1.0 ns
First Peak

Tolerance

Ip

3.75 A/kV

< ± 15 %

3.75 A/kV

< ± 10 % for 330 Ohm Res

0 ~+ 30 % for 2000 Ohm Res

 

Current at 40% RC

I1

2 A/kV

< ± 30 %

2 A/kV, < ± 30 %

for 330 Ohm Res

 

0.275 A/kV, < ± 30 %

for 2000 Ohm Res

 

Current at 20% RC

I2

1 A/kV

< ± 30 %

1 A/kV , < ± 30 %

for 330 Ohm Res

 

0.15 A/kV , < ± 50 %

for 2000 Ohm Res

 

Equipment 4 GHz Wideband ESD Current Target – Attenuator – Cable Chain

< ± 0.5 dB   DC – 1 GHz

< ± 1.2 dB   DC – 4 GHz

 

> 1.2 x 1.2  meter reference plane

 

Oscilloscope > 2 GHz analog Band

 

1 GHz Wideband ESD Current Target – Attenuator – Cable Chain

< ± 0.5 dB   DC – 1 GHz

 

 

> 1.2 x 1.2  meter reference plane

 

Oscilloscope > 1 GHz analog Band

 

Tolerance Require ESD waveforms to be tested 5 times at each level and all waveforms should be within the standard specification Require ESD waveforms to be tested 10 times at each level and calculated the average Tr, Ip, I1, I2, then the average parameters should be within the standard specification

Table 2 Contact mode discharge current waveform parameters.
ES613 ESD Simulator from ESDEMC satisfies the requirements for both IEC61000-4-2:2008 and ISO10605:2008 (ES613-20 up to ±20 or ES613-30 up ±30 kV).

A4001 ESD Current Target from ESDEMC satisfies the requirements for both IEC61000-4-2:2008 and ISO10605:2008 (up to ± 30 kV).

A4002 ESD Current Target Adapter Line from ESDEMC satisfies the requirements for both IEC61000-4-2:2008 and ISO10605:2008 to calibrate the frequency response of both ESD target and adapter line.

3. Test Setup:

The ESD current target should be mounted in the center of a 60” x 60” (1.2 m x 1.2 m) or larger vertical calibration plane. The plane can be one wall of a Faraday cage. The target is mounted to a 40 mm diameter hole centered in the plane and fastened by 8 screws and lock-washers. An oscilloscope, attenuators, and cabling are located inside the enclosure, or on the other side of the plane from the ESD simulator. Figure 1 illustrates a possible setup.

TN003_P01 ESD Simulator Calibration setup
TN003_P01 Figure 1.ESD Simulator Calibration setup

Connect the attenuator directly to the ESD target output. If it is expected that the output voltage will exceed the oscilloscope input voltage rating additional attenuation may be used. Please refer to the Attenuation Calculation section below for details on selecting proper attenuation. Connect the ESD ground return cable to the target plane according to the standard. A simplified block diagram is shown in Figure

Typical setup of ESD simulator measurement
Figure 2. Typical setup of ESD simulator measurement

Attenuation Calculation

ESD Target with 20 dB attenuator configuration
Figure 3. ESD Target with 20 dB attenuator configuration

In the diagram above, a 20 dB attenuator is used in the measurement of an ESD discharge event, and an oscilloscope is represented as a 50 Ohm load. Because of the 20 dB attenuator the voltage seen at the input of the oscilloscope is 1/10 of the voltage incident at the target, or
V2= V1/10.
Because the attenuator is terminated in 50 Ohm, the input impedance seen at port 1 is 2.08//50 Ohm = 2.00 Ohm, meaning
V1 = Iesd ×2.00 Ohm
Where, IESD is the current into port 1 during a discharge event. The 2.08 Ohm resistor is the specification for an ESDEMC factory calibrated A4001 Target. This may be different for other manufacture’s targets. The ratio between ESD current and voltage present at the oscilloscope is then
Iesd / V2 = 5:1
This ratio is useful for determining how much attenuation is required for oscilloscope safe measurements because the currents for different high voltage set points are known. For example, during an 8 kV ESD test a discharge current, IESD, is expected to have a 30 A peak, corresponding to a peak voltage at the oscilloscope of 6 V. Additional attenuation should be added at the beginning of any new measurement setup to ensure safety of equipment until confidence in the setup is established.
An ESD Source Voltage versus Recommended Target Attenuator Size table is calculated below for reference. It is based on a 50 Ohm 5 Vrms real time oscilloscope measurement (a measurement range of 8 V with 1 V/div). The green zone is a safe operating area, and the numbers therein are the peak voltages seen at the oscilloscope. The yellow zone is a boarder-line area and should probably be avoided because when considering the ±15% peak current tolerance margin from standard, it might not be enough. A GHz high speed Oscilloscope has max voltage reading of 8V or 10 V at maximum scale:

ESD Source
(kV)
Peak I
(Amp)
(Amp)
First Peak Voltage in Oscilloscope
(Volt)
Attenuation after ESD Target
20 dB 26 dB 30 dB 40 dB
4 15 3.0 V 1.5 V
8 30 6.0 V 3.0 V
15 56.25 11.25 V 5.62 V 3.56 V 1.13 V
25 93.75 18.75 V 9.38 V 5.93 V 1.88 V
30 112.50 22.5 V 11.25 V 7.12 V 2.25 V

Table 3 ESD Source voltage and Recommended Target Attenuation Setups.
Expected Waveform (for IEC standard)

The expected 4kV IEC 61000-4-2 standard waveform is shown in Figure 4.

Figure 4: Ideal IEC 61000-4-2 ESD Simulator Waveform
Figure 4: Ideal IEC 61000-4-2 ESD Simulator Waveform

Measurement 8kV IEC Result

Figure 5 Measured IEC 61000-4-2 ESD Simulator Waveform
Figure 5 Measured IEC 61000-4-2 ESD Simulator Waveform

 

Test Levels Indicated Voltage First Peak (±15%)

Trise = 0.8 ± 0.2 ns

Current @ 30 ns

(±30%)

Current @ 60 ns

(±30%)

Level 1 ±2kV 7.5 A 4 A 2 A
Level 2 ±4kV 15 A 8 A 4 A
Level 3 ±6kV 22.5A 12 A 6 A
Level 4 ±8kV 30 A 16 A 8 A

 

Voltage Rise time (ns) Peak Current  [A] Current  at 30 ns [A] Current  at 60 ns [A] Result
IEC (±20%) Cal Result IEC (±15%) Cal Result IEC (±30%) Cal Result IEC (±30%) Cal Result  
2 kV  

 

0.8

(0.6~1.0)

0.905 7.5 (6.375~8.625) 7.6 4 (2.8~5.2) 3.45 2 (1.4~2.6) 1.75 PASS
4 kV 0.909 15 (12.75~17.25) 15.15 8 (5.6~10.4) 7.6 4 (2.8~5.2) 3.3 PASS
6 kV 0.914 22.5 (19.125~25.875) 22.3 12 (8.4~15.6) 11.3 6 (4.2~7.8) 5 PASS
8 kV 0.925 30 (25.5~34.5) 30.6 16 (11.8~20.8) 15.5 8 (5.6~10.4) 6.5 PASS

Table 4 IEC 61000-4-2 contact discharge current waveform parameters.

 

4. FAQ Section

4.1 How do oscilloscope bandwidth / sampling rate affect calibration?

Some ESD events have been measured with a rise time <100 ps and the actual ESD waveform may be even faster. The bandwidth needed to resolve such a fast rise time is approximately 0.35/rt, or 3.5 GHz for a 100 ps rise time. Without enough bandwidth or sampling rate, the rise time will be down sampled and not adequately captured. A simplified comparison of the same rise time with not enough and enough sampling rate, respectively, is shown below,

Figure 6 Rise-time comparison with and without enough sampling rate
Figure 6 Rise-time comparison with and without enough sampling rate

In addition, the oscilloscope bandwidth / sampling rate could affect the measured first peak value as the first peak contains high frequency components. Even a waveform measured with the same oscilloscope with different sampling rates will show different results. This could lead to an ESD simulator appearing to have passed the standard with a slower sampling rate, but actually failing with a higher sampling rate. An example of this is shown below,

Figure 7 Effect of using different sampling rates with the same oscilloscope
Figure 7 Effect of using different sampling rates with the same oscilloscope

 

4.2 When buying an ESD Target, can I buy only the ESD target and use the cable and attenuators already in house for the calibration?

The standards require the ESD Target-Attenuator-Cable Chain (up to the connection to the oscilloscope) and the oscilloscope to be calibrated before the ESD simulator calibration test. If the ESD target is calibrated without the attenuator and cable, the ESD Target will have to be recalibrated with the new cable and attenuator. Or one should characterize the effects of their own cables and attenuators to compensate for them mathematically.
For cable selection, the standard requires the test cable to be well shielded and low loss. A RG400 cable no more than 1 meter long is preferred by the standard. RG 214 is 1/2 the loss and is commonly available, but may not be available with SMA connectors. Most high speed oscilloscopes use SMA or improved BNC connectors.
For attenuator selection, the frequency response needs to be flat up to 4 GHz to make the overall transfer impedance of Target-Attenuator-Cable Chain flat according to test standard. Also the attenuator needs to be able to handle a relatively large peak power rating.

4.3 How do the other setup parameters affect the waveform?

Parameters Influence
Shielding A 1.2 m x 1.2 m reference plane is required for the shielding against the direct coupling between oscilloscope and the ESD simulator. It is required by the standard.  And the measurements observed by different oscilloscopes can be very different.  Some oscilloscopes will show significant noise coupling (without the ESD target connection), and some will show very little.
Position of ground cable

 

The length and shape of the grounding wire, and thereby the effective inductance of the loop, will affect the secondary RC peak.  This should be positioned correctly, but the effects on waveform are normally small.
Orientation of simulator

 

This typically has some effect on the test waveform but normally small.
Air Discharge

 

The approach speed and environmental factors greatly affect results making repeatability difficult.

Table 5 Parameters and their influence

 

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TN002 ESD Target Calibration Method

Download ESDEMC_TN002 ESD Target Calibration Method (PDF )

1. Calibration Objective

The objective of this report is to calibrate the ESD target and check its performance and compare the results to the requirements of the IEC 61000-4-2 standard.
Requirements from IEC 61000-4-2 standard:

1. Input Impedance of ESD target

The Front Side of ESDEMC A4001 ESD Current Target
Figure 1 The Front Side of ESDEMC A4001 ESD Current Target

The ESD current target used to measure the discharge current from ESD generators should have input impedance between the inner electrode and ground ≤ 2.1 Ohm @ DC.

2. Insertion Loss of the Target-Attenuator-Cable Chain

ESDEMC A4001 ESD Current Target-Attenuator-Cable Chain
Figure 2 ESDEMC A4001 ESD Current Target-Attenuator-Cable Chain

 

Instead of specifying the insertion loss of the ESD current target, the insertion loss of the measurement chain consisting of the target, attenuator and cable is specified. The variation of the insertion loss may not exceed:
+/- 0.5 dB up to 1 GHz
+/- 1.2 dB 1 to 4 GHz.
The nominal value S21 of the insertion loss:
S21 = 20*log [2*Zsys/(Rin + 50 Ω) ] dB
Where Rin is the DC input impedance of the chain when loaded with 50 Ω.

2. Measurement Setup and Results:

Device Manufacture Model Serial Number Calibration Due
Network Analyzer Agilent E8357A US42070561 08/13/2016
VNA Calibration Kit Agilent 85092C MY46180831 08/14/2016
Digital Multi-meter Keithley 2110 1374108 07/15/2016
Digital Power Supply Agilent E3648A MY40004580 07/20/2016
ESD Target Adapter Line ESDEMC A4002 A4002-001 09/02/2016

Table 1. Measurement Equipment used in this report
1. For the DC input impedance
An LCR meter or a 4 wire source-measurement-meter (SMU) should be used to measure the DC input impedance. The electrodes should be connected in parallel to the input of the target. In this calibration report, the target was connected with a 20 dB attenuator plus the RG400 cable and a 50-Ohm termination. A value of around 2.00 Ohm should be measured.
2. For the frequency response
The ESD current target, attenuator and coax cable are attached to the target adapter for determination of the frequency response. The typical setup is shown in figure 3:

Mount ESD Target on to Target Adapter Line and connect to VNA
Figure 3 Mount ESD Target on to Target Adapter Line and connect to VNA

 

The Insertion Loss - S21 of ESDEMC A4001 ESD Target Chain (SN A4001-195)
Figure 4 The Insertion Loss – S21 of ESDEMC A4001 ESD Target Chain (SN A4001-195)

 

 Transfer Impedance of the ESDEMC A4001 ESD Target Chain (SN A4001-195)
Figure 5 Transfer Impedance of the ESDEMC A4001 ESD Target Chain (SN A4001-195)

For measuring insertion loss of the target-attenuator-cable chain, a network analyzer was used to measure the S21. The S21 result of the setup is shown on figure 4. The red dash lines are the limits from the ICE 61000-4-2 standard. So this ESD Target is within the spec per ICE 61000-4-2 standard.

3. Maintaining the Current Target Performance

The performance of the current target shall be verified at least every two years. It is sufficient to verify the DC-characteristics of the target. The rational is that changes in the overall mechanical geometry are very unlikely, as they require a lot of force. The only place damage can occur is at the connector (inspect visually) and at the resistors due to excessive force on the center conductor of the target. If resistors break or get otherwise damage these change will be seen at DC and at high frequencies.
The test can be done by injecting a current of about 1 A into the target while terminating the target with 50-Ohm. The DC transfer impedance, defined as the voltage measured across the 50 Ohm termination divided by the input DC current of about 1A. It shall not deviate from the expected by more than 2%. Care must be taken to inject the current at two points that are different from the points at which the voltage is measured. This is typical for 4-wire resistance measurements. It is suggested to inject the current at the front side of the target and to measure the voltage on the back side of the target. A T-junction connector can be used to attach a DC voltage meter and a 50-Ohm termination at the same time. Often it is advisable to perform the test with two opposing polarities of the DC current and to take the average of the two resistance readings. This cancels effects of thermal voltages that might occur across contacts of different material. A direct use of a 4-wire, 4-contact impedance meter might lead to instable results as long as the target is mounted in a large ground plane, due to noise coupled into the 4-wire, 4- contact connection setup. It is suggested to test the measurement setup on a known, low impedance (e.g., 1 Ohm) resistor at first.

Reference: IEC 61000-4-2 standard ed2.0 – 2008

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TN001 ESD Target Adapter Line Calibration Method

Face-to-face adapter line calibration test setup

Download ESDEMC_TN001 ESD Target Adapter Line Calibration Method (PDF )

 

Model A4002-N ESD Target Adapter Line
Figure 1. Model A4002-N ESD Target Adapter Line

1. Calibration Objective

The objective of this report is to calibrate the ESD target adapter line and check its performance and compare the results to the requirements of the IEC 61000-4-2 standard.
Requirements from IEC 61000-4-2 standard:
The 50 ohm conical adapter line connects the 50 ohm cable to the input of the ESD target. Geometrically, it smoothly expands from the diameter of the 50 ohm coaxial cable to the diameter of ESD target. If the target is made such that the impedance calculated from the diameter ratio d/D not being equal to 50, the target adapter line shall be made such that the outer diameter of its inner conductor equals the diameter of the inner electrode of the current target. The impedance is calculated considering the dielectric constant of the material that fills the conical adapter line (typically air).

The target adapter line shall show an impedance of 50 ohm +/-2% from DC to 4 GHz. The reflection coefficient of two target adapter lines face-to-face mounted shall be better than 30 dB up to 1 GHz and better than 20 dB up to 4 GHz while the insertion loss shall be less than 0.3 dB in the same configuration.

2. Measurement Setup and Results:

In the test, two identical ESD target adapter lines are mounted face to face and connected to a calibrated network analyzer.

Face-to-face adapter line calibration test setup
Figure 2. Face-to-face adapter line calibration test setup

The measure results, S11 and S22 values, show the reflection coefficient of the ESD Target adapter line, which according to the standard the value should be better than 30 dB up to 1 GHz and better than 20 dB up to 4 GHz, the S21 or S12 values show the insertion loss of the shall be less than 0.3 dB. The results below are the examples passed the Requirements from IEC 61000-4-2 standard:

 

Insertion Loss and Reflection Coefficient of 2 Face to Face Mounted ESDEMC A4002 ESD Target Adapter Lines
Figure 3. Insertion Loss and Reflection Coefficient of 2 Face to Face Mounted ESDEMC A4002 ESD Target Adapter Lines

 

 

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PB2010.11 Full-Wave Simulation of an Electrostatic Discharge Generator Discharging in Air-Discharge Mode Into a Product

Download PDF – Full-Wave Simulation of an Electrostatic Discharge Generator Discharging in Air-Discharge Mode Into a Product

Abstract—This paper introduces a methodology to simulate the currents and fields during an air discharge electrostatic discharge (ESD) into a product by combining a linear description of the behavior of the DUT with a nonlinear arc resistance equation. The most commonly used test standard IEC 61000–4-2 requires using contact-mode discharges to metallic surfaces and air-discharge mode to nonconducting surfaces. In the contact mode, an ESD generator is a linear system. In the air-discharge mode, a highly nonlinear arc is a part of the current loop. This paper proposes a method that combines the linear ESD generator full-wave model and the nonlinear arc model to simulate currents and fields in air-discharge mode. Measurements are presented comparing discharge currents and fields for two cases: ESD generator discharges into a ground plane, and ESD generator discharges into a small product.

Index Terms—Air-discharge mode, cosimulation, electrostatic discharge (ESD) generator, full-wave modeling.

I. INTRODUCTION

Simulating electrostatic discharge (ESD) allows predicting the currents and fields seen within a device under test (DUT) during an ESD, thus it helps to predict failure levels [1], [2]. The most commonly used test standard IEC 61000–4-2 [3] requires using contact-mode discharges to metallic surfaces and air-discharge mode to nonconducting surfaces. If an air discharge is attempted to a nonconducting surface, a discharge to a conducting part can occur.

In contact mode, the output waveform is proportional to the charge voltage, thus, the ESD generator can be analyzed as a linear system in both time domain (TD) and frequency domain (FD) [4]. Those models [5]–[8] for contact mode differ in the software used, the upper frequency limits, and if a specific commercial model of an ESD generator is simulated. However, the numerical modeling of an air discharge is more complex due to the highly nonlinear behavior of the arc [9]–[14]. The generator needs to be separated into the linear sections comprising the metallic elements, resistors, capacitors, and the nonlinear arc. It has been shown that the arc can be modeled as a time-varying resistor valid for the first tens of nanoseconds [13]. This model needs to be integrated into the numerical model.

Air-discharge currents badly repeat. Even if the voltage and speed of approach are kept the same, ESD currents will vary strongly from discharge to discharge. The variations are due to different arc lengths and not a direct result of corona or speed of approach [13]. In [12], a method to combine the arc model from Rompe and Weizel with an equivalent circuit of the discharging object is shown. This methodology is expanded in this paper to combine a linear full-wave model of the ESD generator and the DUT with a nonlinear arc model. Currents and fields are obtained.

Section II introduces the methodology. Sections III and IV verify the methodology by comparison to measured data. Section V discusses the application and the limitations of this method.

II. METHODOLOGY

In general, different processes are possible for coupling SPICE to a full-wave solver: Simultaneous solution exchanges voltage and current information with a SPICE-like solver after every time step of the full-wave solution [15], [16]. Sequential solutions first calculate the S-parameters of the linear section of the circuit and then combine them with the nonlinear part of the circuit in SPICE. We use the second method. It allows reusing the S-parameters to save calculation time, if only the arc parameters are changed.

More in detail, a four-step process is used, which simulates linear parts in full wave and nonlinear in SPICE. The arc attaches at two points: at the ESD generator tip and at the DUT. These two points are used to define a port. In the first step, the impedance at this port is calculated. This is the impedance looking into the DUT and a Noiseken ESD generator (ESS2000). The simulation is performed using computer simulation technology (CST) [17]. Both the TD and FD solver can be used. Although the impedance Z11 is calculated in the full-wave model for a given distance (0.7 mm) between the ESD generator and the DUT, different distances will influence the result little as long as the distance is in the arc length range (0.3–3.0 mm). The tip to ground capacitance is small relative to the distributed capacitance of the rod. This impedance is transformed into a form suitable for TD simulation. Here, the commercial software Broadband SPICE [21] was used. An order of 28 was selected to generate the circuit. SPICE then combines the impedance description from step 1 with an arc model based on the law of Rompe and Weizel. This law describes the arc during the first tens of nanoseconds as a resistance and has been validated for ESD applications [18], [19]. The resulting current is reimported into CST as the excitation waveform of the current port, which is placed between the two points that had been previously selected to define the impedance port to calculate Z11 to obtain fields and currents within the ESD generator and the DUT. The process is summarized in Table I.

The detailed combination in SPICE is now shown (see Fig. 2). The Z11 describes the linear part of the system. Once the Z11 has been obtained, it needs to be transformed into a form suitable for TD simulation. Software tools like IDEM [20] or Broadband SPICE [21] have been used successfully in this research. The subcircuit created from Z11 is not unique. Its complexity can be user defined, which depends on the transformation algorithm, the error, and the order of interest.

The arc of an ESD can be modeled by breaking it down into different phases. The first phase is the resistive phase. The arc is best modeled by a time varying resistance. In the second phase, which is usually reached after a few tens of nanoseconds, the impedance of the external circuit is larger than the impedance of the arc. In this case, the arc often acts more as a constant voltage drop of about 25–40 V. The rising edge of the ESD is the main contributor to the radiated and inductive coupling into DUTs. For this reason, we concentrate on the resistive phase and do not model other aspects (e.g., how the arc extinguishes). Multiple models describe the resistive phase or arcs [18], [19], [22]. In [13], it has been shown that the model of Rompe and Weizel is the most suitable for ESD simulation, as it can correctly describe the effect of the arc length on the rise time and peak current. The arc resistance can be calculated as follows [13]:

The structure of the SPICE model is shown in Fig. 2. A step function having a rise time of approximately 30 ps was used as the source. The rise time is selected by two criteria. If it is too long, then it will influence the current rise time. The current rise time should be determined only by the arc resistance law and the linear equivalent circuit. Further, the rise time cannot be too small, if the pulse contains strong frequency components beyond the range, in which the impedance is calculated, it can lead to instabilities in the SPICE simulation. The fast voltage rise starts the arc resistance model. The current rise time is not determined by the rise time of the step function, but by the arc resistance model. The subcircuit represents Z11 . The user provides the voltage and the arc length to calculate the discharge currents. The longest possible arc length in a homogeneous field is given by the Paschen law [13]. Such arc lengths would occur in air discharge for low approach speeds or in humid air conditions. The long arc length leads to slow rise times and lower peak values. Longer arc lengths than the length given by Paschen’s equation are possible in strongly nonhomogeneous fields, e.g., if the discharge is between an ESD generator and a sharp edged metal part, or if the discharge is gliding on a nonconducting surface. Very short arc lengths occur at high approach speeds and in dry air [9], [13], [23], leading to fast rise times and very high peak current values.

In the following, we will first apply this methodology to a discharge to a ground plane, mainly for verification purposes, and then to a discharge to a small MP3 player.

III. CASE 1: ESD GENERATOR DISCHARGE TO A GROUND PLANE

A. Z11 Between the Tip of the ESD Generator and the Ground Plane

The structural and discrete elements of the ESD generator are linear with respect to voltage. We further assume that the DUT acts linearly. For obtaining the current injected by the arc, this does not require that no nonlinear effects take place inside the DUT; it only requires that the current injected into the DUT is proportional to the charge voltage. For example, if an internal ESD protection device would clamp a trace voltage while the ESD current is injected into the ground system of the DUT, then, this clamping would have hardly any effect on the current, thus, the DUT would act as a linear device, as seen by the ESD generator. However, if secondary breakdown occurs, e.g., a spark within an attached two-wire power supply, then this could strongly affect the ESD current, thus, the modeling approach might lead to wrong results.

Both TD and FD solvers can be used to obtain Z11 . We observed the FD simulation giving a more reasonable Z11 result and using less simulation time. The simulated Z11 for the structure of the ESD generator above a ground plane is shown in Fig. 3 as the dotted line. This result is verified by comparison with measurement and an approximate SPICE model of this ESD generator [4]. The model contains sufficient detail for achieving a good match to measured impedance data, and correctly represents the 110-pF capacitor and 330-Ω resistor structure inside the ESD generator at lower frequencies. The calculation takes about 15 h on a PC (CPU 3.20 GHz, 16G RAM).

ESD generators have long ground straps. It increases the simulation time if the full length is included into the simulation domain. As most disturbances are caused by the fast changing parts of the currents and fields, one may not need to include the full ground strap into the model. The ground strap mainly influences the falling part of the waveform. The SPICE model shown in Fig. 4 includes a 3500-nH inductor to model the ground strap. A shorter ground strap will reduce the time between the first and the second peak of the discharge waveform.

The first step obtained the impedance representing an ESD generator discharges to a large ground plane. In the next step, the impedance is transformed into the TD suitable form and combined with a nonlinear arc equation in SPICE.

B. SPICE Simulation for the Discharge Current

Fig. 6 illustrates the effect of the arc length on the current waveform. It shows SPICE-simulated discharge currents for a 5-kV charge voltage. An arc length of 1.1-mm equals the Paschen length, such a discharge current would be expected at high humidity and slow approach speeds. A more typical value at moderate approach speeds is 0.7 mm. At this value, the rise time will be somewhat similar to the rise time of an ESD, as given in the IEC 61000–4-2 standard (about 850 ps). A more extreme case is given by the 0.3-mm arc length simulation. Very dry air and high approach speeds might lead to such a discharge. The simulated current peak value is 26 A and the rise time is 150 ps.

C. Reimport of Currents Into CST

For obtaining the fields, one needs to reimport the discharge current into the full-wave model as the excitation waveform. This is discussed and validated in the second case example.

D. Validation by Measurement Results

The current into the large ground plane was measured using an ESD current sensor, as described in [3]. In Fig. 7, the SPICEsimulated discharge currents are compared to the measured data for different approach speeds. Even if the exact approach speed or arc lengths are not known, it shows that the ranges of arc lengths used in the simulation are representative for discharge currents obtained in the experiment. A more in-depth comparison based on measured arc length values can be found in [13].

IV. CASE 2: ESD GENERATOR DISCHARGE INTO A SMALL PRODUCT

A. Z11 Between the Tip of the ESD Generator and the DUT Surface

This case simulates a discharge into an MP3 player, a small, nongrounded DUT. The whole geometry is shown in Fig. 8. The MP3 player model includes the main blocks of the DUT similar to [24]. In brief, the major blocks of the player (metal frame, battery, display, PCBs) are modeled as metal blocks connected at the locations of connectors and frame connection points.

The DUT is placed on a dielectric sheet above a larger ground plane. This forms a capacitor having a capacitance of about 25 pF, leading to a higher value of Z11 at lower frequencies. The value for Z11 was obtained, as shown in Fig. 9. The comparison between Z11 of the ESD generator and the large ground plane and Z11 of the ESD generator with the MP3 player is shown in Fig. 10. It mainly shows the smaller capacitance at lower frequencies; at higher frequencies the impedance of the 25-pF capacitor formed by the player against the ground plane is lower than the source impedance of the ESD generator, thus, the impedance in case 2 is similar to the impedance seen in case 1, the discharge to a large ground plane.

B. SPICE Simulation for the Discharge Current

The Z11 defined between the discharge tip and the MP3 player was transformed into a subcircuit using Broadband SPICE. The subcircuit combined with the arc model gave the simulated discharge current for different user-defined charging voltage and arc length. The simulated discharge current at the 5-kV charge voltage with different arc lengths is shown in Fig. 11.

The obtained peak values and rise times are tabulated in Table II. The arc length has a very strong effect on the parameters shown, especially, the current derivative.

C. Reimport of Currents Into CST

To obtain transient fields, the current waveform obtained from the SPICE simulation is reimported into CST as the excitation waveform. The current source port is placed between the two points that had been previously selected to define the impedance port to calculate Z11 . One check is worthwhile: If the Z11 representation used in SPICE would perfectly match the Z11 from the FD full-wave simulation, then the port voltage obtained during the full-wave simulation using the reimported current would match the port voltage (= voltage across the arc) in the SPICE simulation.

For case 2, the SPICE-simulated current was imported back to the CST model as the current source. The comparison of the port voltage in the SPICE model and the port voltage in the CST model in Fig. 12 shows a good match.

The simulation using the reimported current allows simulating the fields within and around the MP3 player by placing appropriate monitor probes. If these probes are placed close to the metallic surfaces of the MP3 player, then they represent the surface current densities and the displacement current densities, which can be used to estimate the coupling into bond wires of an IC, traces, and flex cables for predicting ESD upset threshold levels. Before current and field results are shown, the measurement methods are introduced.

D. Validation by Measurement Results

The current was injected into the small product, and the magnetic field was measured. To capture the current injected into the MP3 player, an F-65 (1 MHz–1 GHz) current probe was used, as shown in Fig. 13. The magnetic field was measured using a small shielded loop and a Tektronix 7404 (4 GHz BW, 20 GS/s) oscilloscope.

At 5-kV charge voltage, a NoiseKen ESD generator was discharged into the player. The player was placed above a large GND plane with a dielectric sheet between them. Figs. 13 and 14 illustrate the setup.

The relationship between approach speed, humidity, and arc length is not of deterministic nature, but given by the influence of the humidity on the statistical time lag [13]. Thus, on an average, one will observe shorter arc lengths with increasing approach speeds for a given charge voltage. For achieving short arc length discharges without reducing the humidity, the surface had been cleaned using alcohol and fast approach speeds have been used, longer arc lengths are achieved by slow approach speeds. Shown are examples of the captured waveforms for different approach speeds.

1) Measured Discharge Current: The current clamp’s frequency response falls off above 1-GHz bandwidth, thus, the fastest rise time of a step response signal would be approximately 300 ps. Fig. 15 shows the measured discharge currents for different approach speeds.

The simulation results are compared to the measured results for verification. The fast rise time result is shown in Fig. 16. The simulated discharge current for a 0.3-mm arc length and 5-kV charging voltage gives a discharge current with a rise time of about 200 ps and a peak value of 21 A. The measured discharge current has a rise time of about 300 ps and a peak magnitude of about 22 A. The difference can be explained by the limited bandwidth of the F-65 clamp. Due to the difficulty in measuring arc length, we can only approximately compare measured and simulated results. Nevertheless, the comparison shows that the simulated and measured data are within the same ranges.

In Figs. 17 and 18, the comparison of simulation discharge current for 0.7-mm and 1.1-mm arc lengths is shown. They match well with the measured results.

2) Measured Magnetic Field: This is to confirm the last step of the process: Injecting the SPICE simulated current back into the full-wave simulation for obtaining fields. A shielded loop was placed 5 cm away from the product (see Fig. 14). A deconvolution was performed to obtain the field strength from the captured voltage at the probe output. The deconvolution is mainly an integration process, having two deviations from the ideal integration. At lower frequencies, high-pass filtering is performed to avoid the accumulation of the oscilloscope’s small but relevant dc offset during the integration. Second, at higher frequencies, the self-inductance of the probe in conjunction with the 50-Ω load, leads to a self-integration, thus, no external integration is needed above 3 GHz. The resulting magnetic fields are shown in Fig. 19. The data match well. The measured rise time is about 250 ps. By using the SPICE model, one can estimate the arc length from the rise time. Repeated simulations indicate an arc length of about 0.4 mm. The Paschen length for 5 kV is about 1.1 mm at sea-level air pressure. Thus, the combination of the speed of approach and the statistical time lag reduced the arc length in this measurement to 35% of the Paschen value, leading to a very fast rising ESD current.

Several field probes were placed in the full-wave model to monitor the magnetic field. A probe that is 5 cm away from the discharge point gives the H-field data shown in Fig. 19. The result matches well with the measured data.

V. DISCUSSION

The methodology allows predicting the currents and fields in and around a product. There are three types of limitations in the methodology.

The most obvious one results from the limited ability of simulating details in the product and within the ESD generator. As with every simulation, the number of unknowns and the ratio of the smallest to the largest detail will limit the size of the model. The methodology allows circumventing this at least partially, especially for small products. If the product is small, then the fields inside the product will be dominated by the fields caused from the injected current and not by fields directly coupling from the body of the ESD generator. Those fields would especially be significant in the contact mode, in which the field components that are greater than 1 GHz are often caused by the rapid voltage breakdown in the gas-filled relay that initiates the discharge. As this analysis is for an air discharge, one will find the strongest high-frequency components directly at the arc, as with further distance from the arc high-frequency components will be attenuated by both frequency-dependent loss and radiation. If the fields are dominated by the injected current, then one can use a relatively simple model of the product just to determine the current, but in the last step, in which the current is reinjected into the product, a more complex model of the product can be used, but a very simple model of the ESD generator (and a forced current).

The second limitation results from the need for providing the arc length for the arc resistance calculation. Although possible, arc length measurements are difficult to implement. In a simulation, we suggest the following approach. At first, an arc length should be selected that leads to an air-discharge current that is similar to the contact-mode discharge current, as specified in the IEC 61000–4-2 standard. For 5 kV, this is about 0.8-mm arc length. Values for other voltages can be found in [13]. As a very slow rising current, the Paschen value can be selected, leading to discharges of lower severity and as extremely fast rising current; a value of about 30% of the Paschen length is suggested. This value is based on experimental evidence. In measurements that captured the arc length [13], we found it possible even under very dry air and clean surface conditions to obtain arc lengths of less than 30% of the Paschen value.

The third limitation is related to the stability of the TD SPICE simulation. In this simulation, a very rapid change of resistance is combined with a SPICE impedance model created from fullwave simulation. If instabilities occur, one should inspect the SPICE model for passivity and causality, in addition, one can simulate the discharge using longer arc lengths first, as these show a slower change of the arc resistance.

The main application of this model lies in the simulation of ESD to products. For example, it is known that the arc length tends to be small for fast approach speeds in dry air. The short arc length leads to fast rise times and high peak values. Using this model, one can quantify the fields inside a product for different arc lengths. Further applications are the simulation of grounding conditions of products on the arc, and thus, the current. Further, the model can be extended to the case of secondary breakdown, e.g., an ESD occurs to an ungrounded metal part leading to a second discharge from this ungrounded part to the main part of the DUT.

VI. CONCLUSION

This paper proposes a method for simulating an ESD generator discharging in air-discharge mode into a product. The linear and the nonlinear part of the problem are separated to simulate the linear part in a full-wave solution and the nonlinear arc in SPICE. The SPICE results are reimported into the full-wave problem as the excitation. This allows the fields inside a product during an air discharge to be obtained. The method has been verified by the comparison of simulated current and transient field results with measurements.

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PB2010.11 Effects of TVS Integration on System Level ESD Robustness

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50 Words Abstract – Higher integration of Transient Voltage Suppression (TVS) functionality into ASIC I/O cells implies lower system costs. But as the ESD pulse is directed deeper into the system, migrating the TVS clamping function from the periphery of the system to a central ASIC may actually reduce the system’s ESD robustness. ESD current reconstruction scanning can be used to trace the current path on a PCB, and possibly within an IC. The article compares the current spreading during and ESD for different ESD protection methods.

I. Introduction

The inevitable trend in system design for ESD robustness has tended toward higher integration of Transient Voltage Suppression (TVS) functionality into ASIC I/O cells. In low cost systems where the entire device has been distilled into a single “System on a Chip” (SOC) and perhaps an additional DDR memory device and a power supply and clock generator, the addition of discrete TVS devices near I/O connector ports can add appreciable costs to the parts count and in the case of a system with just a few USB or Ethernet ports, can double the assembly/placement costs for the entire PCB.

By shifting the ESD clamping into the highly integrated SOC these costs can be eliminated, however, this requires that the aggressor ESD pulse must be allowed to travel deep into the system where new susceptibilities to system upset may be triggered. While the cost is reduced, and the system ESD level survivability (resistance to permanent damage and hard failures) may be retained, the relocation of TVS clamping from the periphery of the system PCB to a central ASIC may actually reduce the system’s ESD robustness and resistance to upset and soft errors.

This paper demonstrates an improved methodology for quantitatively analyzing and potentially predicting robustness of different system level ESD protection circuits, topologies and layout permutations on a given product. The methodology uses current reconstruction scanning, a methodology to observe the ESD current spreading in a time resolved fashion [2, 5, 6].

II. Measurement Techniques

The objective of this analysis is to characterize what happens throughout the PCB, at various “nearby” nodes when an ESD pulse enters the system through an I/O port, or other means.

Two different analysis techniques are used:

Susceptibility scanning: This determines the local susceptibility of circuits to field injected noise, e.g. ESD like pulses

Current reconstruction scanning: This determines in a time resolved fashion the spread of current after an ESD strike on the system

What is needed is an analysis technique to quantitatively identify all areas of susceptibility on a board, and then relate that to potential I/O entry vectors. This makes it possible for the designer to correlate and potentially predict how a system level IEC61000-4-2 ESD strike may cause a system upset, and provides a method for objectively comparing improvements to the system design.

For example, a designer with a prototype failing minimum system level ESD testing may need to compare different types of discrete TVS clamp solutions near the I/O connector, versus a costreduced alternative I/O cell integrated into an interior system ASIC.

It is a common practice to place ESD protection as close to the perimeter of the system as possible in order to shunt the energy back to the chassis and out of the system as soon as possible.

However, even in the case of a well protected system, upset in an apparently unrelated subsystem may still occur (i.e. an ESD strike to a USB port upsets a PC’s video memory) making blind debug of the system upset extremely problematic.

By combining ESD susceptibility scanning [5] with a new reciprocal technique for “current spread” scanning [1,3,6], a matrix of potentially related aggressor and victim nodes can be identified and provide a comparative focal point for iterative improvement in design robustness.

A. Susceptibility Scanning Testing

1. Equipment

The scanning setup comprises a robotic 3D scanner with test control computer, Transmission Line Pulser (TLP), and DSO for data capture (See Figure 1).

We used the SmartScan system from Amber Precision Instruments [2]. For this test a 10mm horizontal loop probe was used for field injection (Figure 2). The maximum TLP charge level is set be a non-destructive 1kV, with a modified network to minimize the falling edge rate applied (Figure 2).

The scanning resolution is 5 by 5 mm and can traverse the entire system PCB area. When desirable, the system PCB can be mounted in as much of the system level enclosure as desired for closer relation to system level tests. The primary objective here is to probe the extent of the PCB design, routing and components, given a fixed case and mounting enclosure for the product. Certain systems, especially small handheld devices may dramatically hinder access to stacked PCBs or grounding brackets and consideration should be given to the extents of the scans.

2. Procedure

The iterative scanning process traverses a predetermined area of interest on the PCB, alternately injecting a pulse, and then checking the system under test for continued operation. The initial pulse is 4kV until a system upset is detected and the stepped failure level is then tested at the failure location and recorded. In this particular example, when the router operation was upset (reset) due to pulse injection, the router would stop replying to HTTP requests for the configuration setup page (a typical “recoverable loss of function” criterion as might be used in standard system level ESD testing).

Failure criteria are determined on a system-by-system basis, as they would be with a manual system level ESD testing. In this particular example, the test system repeatedly sends Ethernet requests to the Device Under Test’s (DUT’s) configuration stack. When the upset occurred in this case, the DUT would hang and stop responding to requests. At this point, the DUT would be reset by the system test controller and move on to the next test point on the grid.

B. “Current Reconstruction” Testing

In a corollary to the Susceptibility Scanning, the same TLP waveform is injected into a particular I/O port of interest, and the scanning probe is used to “listen” to the PCB.

At each point on the defined grid, the sensed H-field is recorded and processed at a low, non-destructive level creating a new surface plot of energy flow due to the injected pulse. The sensing methodology must take care to sufficiently shield the probe from E-field pickup, and/or remove this component from the measurement capture. [1,7] This does not actually require the system to be functioning, and it may be performed with and without power depending on the failure mechanism to be analyzed. However, the pulse needs to be large enough to trigger the non-linear ESD protection devices, but not so energetic that it causes permanent damage, or a “hard failure” of the system. This creates a great deal of data which can be postprocessed for myriad perspectives on the design.

By trapping the entire pulse at each position, a time variant surface plot can be reconstructed by windowing an interval of interest at various times during the TLP (or IEC or HMM) pulse applied. By post-processing multiple frames with incremental windowing of the pulse, an animated “movie” of the ESD current spreading can be assembled.

In Figure 6, the obvious entry vector of the residual current from the USB port to the SOC ASIC is seen in the upper left corner at the connector where a TVS clamp shunts much of the pulse.

Additional analysis can contrast the current reconstruction path with and without a discrete TVS clamp installed. Without the clamp installed (Figure7a), the current flowing in the signal traces is much higher than with the clamp (Figure 7b), and can be seen coupling into other unrelated, nearby nodes (blue circles.) This may indicate a link into other subsystems if these coupled nodes are related to other susceptible areas identified in the susceptibility scanning.

This potential problem can then be evaluated or eliminated from consideration by overlaying these plots, and comparing the resulting plots of different selections of TVS devices, layouts or ASIC revisions to determine the ESD robustness of each solution.

For example, the original Susceptibility Scan from Figure 5 is shown here expanded in Figure 8.

This plot is then overlaid with the Current Reconstruction Scanning plot of a particular USB port (Figure 9).

This results in a graphical representation of ESD susceptible areas which can be “reached” externally from that particular USB port (Figure 10).

Repeating this procedure for each I/O port (or other potential system level ESD injection point) yields a new plot (and associated peak susceptibility values and positions on the PCB) for each port or injection point of the system. This does not replace IEC61000- 4-2 testing, for example, but rather aides in the debugging of the design when an unexpected susceptibility is discovered.

In Figure 10, the method correctly identifies that the USB pins of the ASIC are of course susceptible to strikes on the USB port. Here, traditional TVS clamping methods can be expected to improve overall system robustness. However, if the scan overlay indicated that a sensitive DRAM or CLOCK pin was within the area of current spreading from the USB injection port, then the robustness improvement solution might simply require a reoriented layout of the USB and CLOCK/DRAM traces.

Such areas can also unexpectedly be aggravated by migrating the system level ESD protection into the ASIC by driving a larger residual ESD pulse current deeper into the system. The overlaid susceptibility plots for the integrated and external TVS solutions in Figure 7a and 7b can be compared to ensure that the integrated clamping solution does not create other robustness issues elsewhere in the system.

This analysis methodology can be used to help identify, compare and grade the relative improvement of each protection solution to problems at the system level.

Acknowledgements

The authors would like to thank Michael Hopkins of Amber Precision Instruments for his assistance.

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PB2010.06 Probe Characterization and Data Process for Current Reconstruction by Near Field Scanning Method

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Abstract- previously a measurement technique for ESD current spreading on a PCB using near field scanning was developed in order to connect the local ESD sensitivity to system level ESD failures in time and spatial domain. The concept of such scanning methodology is proved and several scanning results were processed. However the validation, precision and weakness of such methodology need to be further investigated before the application of such scanning methodology on complex circuit or system.

This article investigates the current reconstruction by near field scanning technique and methodology. It studies the probe factors including coupling frequency response characterization and deconvolution method, spatial resolution for scanning and orthogonal-scan data combine process.

I. INTRODUCTION

This article is a research continuation of a previous paper “A Measurement Technique for ESD Current Spreading on A PCB using Near Field Scanning”. The ESD injection setup and current return paths are shown in Fig. 1 and Fig.2

II. PROBE CHARACTERISTICS

To successfully recover both the magnitude and direction of injected surface current or coupled trace current from probe’s near field induced voltage signal, the understanding of probe characteristics is of great significance. A probe’s coupling frequency response; loss, spatial resolution and directional response need to be evaluated to estimate how well the injected surface current or coupled trace current can be recovered. Then the reverse process from local induced probe signals to desired surface or trace current vectors can be constructed based on the probes characteristics.

A. Frequency Response and Deconvolution Method

For using a magnetic probe to capture a transient magnetic field or current and recover it numerically, the probe’s magnetic coupling frequency response is one of the most important factors to construct the reverse process, or probe frequency response deconvolution.

The probe should have enough inductive coupling bandwidth to cover the main spectrum of the transient magnetic field or current. Then a compensation function of the coupling frequency response can be calculated to recover the transient magnetic field or current from the induced probe voltage signal. In addition, the experimental measurement including the probe should have enough signal noise ratio and dynamic range of H-field or current coupling to get recoverable measurement results.

A probe’s coupling factor for surface current or trace current can be measured by a terminated TEM cell or trace as Fig. 3 shows:

The coupling mechanism between the probe and the excitation can be modelled as Fig 4.

From the model, the frequency response is inductive coupling dominated and the excitation recovery process can be achieved with a process as Fig 5 shows:

A compensation function of the probe’s frequency coupling response and loss with filters is then created with steps as Fig 6 shows:

Finally the desired field or current data can be rescaled from the recovered excitation_ An example of probe deconvolution is followed_ Fig_ 6 is the measured probe voltage signal from TEM Cell excitation. After the deconvolution process a comparison of transient H-field from processed probe signal and directly measured H-field are shown in Fig 8:

Some of the high frequency and low frequency components are lost due to the filters integrated into the compensation function, but they are important to reject low frequency noise and high frequency resonance. Overall the method works well and the recovery result matches direct measurement.

B. Spatial Resolution

Spatial resolution of a probe reflects how well a magnetic field probe can resolve the field strength