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ESDEMC Project Development Capability

ESDEMC Technology LLC is a high technology company specializing in the development and manufacturing of test and measurement products and services. Our team has extensive experience in the development of challenging systems in the area of high voltage, high frequency, complex systems.


Our current design capability cover the following areas:

1 . High-Speed Analog and Digital Designs on the Module or System Level

2.  Microcontroller/ DSP/ FPGA / Programming

3. High Frequency Circuit and System Development up to 40 GHz

4. High Voltage Circuit and System Design up to 300 KV

5. LABVIEW / MATLAB / Visual C++/ Visual Basic Programming Projects

6. Mechanical Design, CNC Machining, Rapid Prototyping, 3D Printing


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Transmission Line Pulse (TLP) Testing

Transmission Line Pulse testing, or TLP testing, is a method for semiconductor characterization of Electrostatic Discharge (ESD) protection structures. In the Transmission Line Pulse test, high current pulses are applied to the pin under test (PUT) at successively higher levels through a coaxial cable of specified length. The applied pulses are of a current amplitude and duration representative of the Human Body Model (HBM) event (or a Charged Device Model – CDM – event in the case of Very Fast TLP, or VF-TLP). The incident and reflected pulses are evaluated, and a voltage-current (V-I) curve is developed that describes the response of an ESD protection structure to the applied TLP stresses. The Transmission Line Pulse test is unique because the current pulses can be on the order of Amps, and the TLP test results can show the turn-on, snap-back, and hold characteristics of the ESD protection structure.

Transmission Line Pulse testing is useful in two very important ways. First of all, TLP may be used to characterize Input/Output (I/O) pad cells on test chips for new process technologies and Intellectual Property (IP). TLP is very useful in developing simulation parameters, and for making qualitative comparisons of the relative merit of different ESD protection schemes for innovative pad cell designs. Secondly, TLP may be used as an electrical failure analysis tool, often in combination with conventional, standards-based component ESD testing.

TLP testing is done according to the ESDA TLP test method, ESDA SP5.5-2014. TLP is quoted on a case by case basis, based on the scope of the work requested; estimated engineering time to perform the test, and customer requested reporting.

Applicable TLP Specs

  • ESDA SP5.5-2014 (ESD Association)
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General Project Design

General analog and digital circuit design, Radio Frequency design, PCB layout and prototyping, board population and testing. Programming of Micro Controllers, DSPs, and FPGAs. System level programming in LabView, Matlab, Visual C++, and Visual Basic. Mechanical design and machining available, and basic 3D printing.

General analog, digital, and Radio Frequency circuit design (to 40 GHz).

High voltage circuit and system design up to 100 kV.

Prototype PCB’s with board population and system testing for a turn-key solution.