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Coming soon: ES660 ESD and Latch-up Automated Test System


ESDEMC Technology LLC proudly announces the upcoming launch of the ES660 series ESD and LU Test System, a cutting-edge, multi-pin automated testing equipment designed to meet the rigorous demands of modern semiconductor testing. This state-of-the-art system redefines industry standards, offering an unparalleled solution for assessing the reliability and robustness of integrated circuits (ICs) and electronic components.


Advanced Testing Capabilities

The ES660 series is engineered to seamlessly support the Human Body Model (HBM), Machine Model (MM), and Latch-Up testing, providing a comprehensive solution for the critical aspects of semiconductor reliability testing. Its advanced features empower semiconductor manufacturers to push the boundaries of innovation and quality assurance.


Versatile and Efficient

The ES660-P1, the first model going to be released in the series, boasts a remarkable capacity of from 128 pins up to 1024 pins. This pin count capability enables the testing of complex ICs and electronic components with a multitude of connections, ensuring precision and efficiency in the evaluation process. By significantly reducing testing time, the ES660-P1 enhances productivity, allowing manufacturers to streamline their operations and meet market demands with ease.


Future-Ready Innovations

In anticipation of evolving industry needs, ESDEMC Technology LLC is also thrilled to announce the development roadmap for the ES660-P2. This upcoming model will support up to 2048 pins, catering to the demand for higher pin count testing. As technology continues to advance, the ES660 series stands ready to adapt, ensuring that our clients remain at the forefront of semiconductor testing capabilities.


Key Features of ES660 Series:

Seamless support for Human Body Model (HBM), Machine Model (MM), and Latch-Up testing

High pin count capacity: ES660-P1 (up to 1024 pins) for precise evaluation of complex ICs

Future innovation: ES660-P2 (up to 2048 pins) on the development roadmap


ESDEMC Technology LLC is a pioneering technology company committed to delivering cutting-edge ESD and EMC solutions for the industry. With a focus on innovation, quality, and customer satisfaction, ESDEMC Technology LLC continues to explore the possibility of future electronic components testing.



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We’re innovative, curious and collaborative.  We’re obsessed with the future of possibilities. If you are too, talk to us. 


[ Check this ESDEMC Career Opportunity (pdf) for recent job opportunity ]


Please send resumes to

Current Openings (Updated 2021 09):

1. RF Design Engineer


RF Hardware Engineer is responsible for designing, prototyping, evaluating and testing high voltage and high frequency hardware, including RF analog & digital electronic circuits.

ESSENTIAL DUTIES AND RESPONSIBILITIES (include but are not limited to)

  1. Research electronic device usability based on hardware specifications and customer requirements
  2.  Design, simulate, optimize, and prototype radio frequency (RF) circuits, inter and intro system signal integrity, improve analog & digital (A & D) electronic circuits and high voltage (HV) circuits
  3. Make modifications and improvements on the performance of electronic devices of current products using electrical and mechanical tools
  4. Test electronic circuits to ensure compliance with internal design goal, write test scripts and performance analysis codes per customer requirements
  5. Maintain and operate common electronic device instruments (high speed real-time oscilloscope, high frequency digital sampling oscilloscope, wide-band signal generators, network analyzer, impedance analyzer, spectrum analyzer, time domain reflectometer, LCR meter)
  6. Troubleshoot hardware electronic devices and process failure analysis
  7. Provide hardware technical support for internal group and customers
  8. Prepare and update hardware data sheets and assembly notes for the internal group


  • Master’s degree in Electrical Engineering or in a closely related field plus minimum 6 months of experience involving ESD, HV and RF circuits
  • Proficiency in computer-aided (CAD) design tools: FreeCAD, LTSpice, and KiCAD
  • Programming skills in Python, MATLAB/Octave
2. Hardware Engineer
· Working with hardware team on designs from concept, prototype to production.
· Maintain design files and documents, tech supports for products with customers.
· Manage small batch production and inspection of new products with China office team.
· Any other necessary duties assigned by Executive Director. 
· BS or MS degree in Electrical or Computer engineering is preferred.
· Good knowledge and experience with general circuit & high-speed system design
· Know some programing language such as Python, C· Experience with EDA tools such as Altium Designer, Circuit Studio, KiCAD, LTSpice, etc.
· Ability to communicate effectively with other design team members.
· Ability to operate instruments, including oscilloscope, network analyzer, LCR, multi-meter, etc.
· Have good technician skill in hardware prototype, such as SMD soldering, drilling, etc.
· Good at drawing, documentation, and management for multi-tasks.
· Multiple languages (Chinese, Korea, etc.,) is a plus.
3. Application Engineer
. Work with design group from concept to product, maintain design and production documents
. Demo and promote solutions internally and externally
. Tech supports for products with existing customers
. Write patents to protect design and paper for publication
Write datasheets, application note and manual
. Manage relationship with customers and sales representatives. 
· BS or MS degree in Electrical engineering or computer engineering
· Ability to operate instrument equipment is preferred, including power supplies, multi-meter, high speed oscilloscope, network analyzer, TDR, LCR meter, spectrum analyzer, etc.
· Excellent knowledge and experience with several types of programing language is preferred, such as Python, C, C++.
· Knowledge and experience with RF and microwave designs· Experience with popular design tools is preferred
· Ability to communicate effectively with other design team members.· Have good hands-on skill in prototype such as soldering, drilling, etc.
· Good at writing/drawing/documentation skills for datasheets and manual writing, and well-organized management skill for multi-tasks between projects  

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Coming Soon: CDM Solution with Multiple Methods, Better Motion, Larger Area, and Wider Bandwidth

ESDEMC will soon be releasing newly developed robotic Charged Device Model (CDM) solutions with the ES640 series. It supports  multiple popular CDM methods, Including widely used FI-CDM Methods (ANSI/ESDA/JEDEC JS-002-2018, AEC Q100-011D, AEC Q101-005A), several contact first methods designed for low voltage CDM, such as LI-CCDM(ANSI/ESD SP5.3.3-2018), CC-TLP methods(upcoming SP), as well as our patent-pending RP-CCDM method, which is a more repeatable solution of performing FI-CDM in contact first method.

The advanced motion control of model ES640 allows testing of for modular, packaged and possible wafer level CDM  devices with XYZ steps down to 1 µm. The solution also features a large test area (150 x 150 and 300 x 300 mm). Both models offer plenty of space for common devices under test. Customization of the test area is also available for special purpose upon request.

The measurement bandwidth of ES640 is greatly improved with DSP. The frequency compensation of the measurement chain, including the disc resistor, cable, attenuator, and measurement channel adapter, can allow the system measurement bandwidth to be over 18 GHz.

Model ES640 has a precision voltage control range from ±5V to ±2000V/4000V, and up to three cameras can be enabled in the test setup for easier user operation (two cameras viewing the contact tip in X & Y directions and another one straight facing down for vertical alignment).

The software allows for automatic waveform capture, automatic system calibration, frequency compensation for processing waveform data, and test speed optimization while supporting a variety of CDM test methods. Old legacy and special customized CDM methods are available upon request.

Please feel free to contact us at where we could provide more information about our system including comparison of some important features and specifications between our new solution and other popular CDM solutions in the market for potential customers.

ESDEMC ES640 CDM Solution with Multiple Methods, Better Motion, and Higher Bandwidth for Charged Device Model ESD Test
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ESDEMC will attend 2019 EOS/ESD Symposium (Riverside, CA, USA, Sep 15th – 20th)

ESDEMC will attend 2019 EOS/ESD Symposium (Riverside, CA, USA, Sep 15th – 20th)

Exhibit Location:

Riverside Convention Center
3637 5th Street
Riverside, CA 92501

Exhibit Hours:

  • Monday, September 16,  6:00 PM – 9:00 PM
  • Tuesday, September 17,  9:30 AM – 5:30 PM
  • Wednesday, September 18,  8:30 AM – 1:30 PM

Our 2019 New Developments includes:

Higher Current ES620-LVS Low Voltage Surge IV-Curve System

EOS-500 EOS Pulse Generator & IV-Curve System

Please visit us!

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EOS-500 Electrical Overstress Pulse Generator is coming

Electrical overstress, or EOS, is a phenomenon where electrical signals applied to a circuit or a device exceed normal operating parameters. These excessive electrical signals are abnormal by definition and are not a part of normal operation of the devices. [1]

Most stress-related semiconductor failures are electrothermal in nature; locally increased temperatures can lead to immediate failure by melting or vaporizing metallization layers, melting the semiconductor, or by changing the semiconductor features. Diffusion and electromigration tend to be accelerated by high temperatures, shortening the lifetime of the device. Damage to junctions may not lead to immediate failure, but it may manifest as altered current-voltage characteristics of the junctions. Electrical overstress failures can be classified as thermally-induced, electromigration-related and electric field-related failures;[2]

Currently, the device EOS failure has been characterized in DC mode and Pulsed mode. Safe operation area (SOA) [3] has been used as the voltage and current conditions over which a device can be expected to operate without self-damage. However, the existing characterization cf the SOA area is not fully covered by DC and TLP type ns scaled pulse. A high current pulsed source between us – ms is needed to bridge the gap.  In addition, the boundary of the safe operation area was not well studied and modeled in terms of repeated electrical stress. ( pulse repetition, pulse duty cycle, and accumulated performance degradation).

Based on the demand of a longer pulse width SOA characterization system, the EOS-500 Electrical-overstress Pulse Generator was developed by ESDEMC to address the pulsed SOA characterization with pulse widths from below 1 μs to over 1ms

EOS-500 R1 Prototype – less than 10 ns rise-time, the pulse width can be digitally adjustable from 1 μs – 1 ms.

EOS-500+ R1 Prototype – less than 6 ns rise-time, the pulse width can be digitally adjustable from 20 ns – 5 ms.


This pulse generator design has multiple advantages comparing to TLP design. such as it can generate pulses at 10000+ pulses per second rate at very repeatable pulse shape. It can be precisely trigged (synchronized ) externally. The pulse circuit is very reliable, no mechanical wearing. The pulse-width is precise, continuously and programmable adjustable from min to max.


The preliminary data sheet can be downloaded below. Specifications are subject to change.

Datasheet download: EOS-500



If you have interest, please contact us at

[1] Electric Overstress (EOS) and Its Effects on Today’s Manufacturing

[2] Failure of electronic components – wikipedia

[3] Safe Operating Area – wikipedia

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ESDEMC will attend 2016 EOS/ESD Symposium (Anaheim, CA, USA, Sep 12 – 14th)

ESDEMC will attend 2016 EOS/ESD Symposium (Anaheim, CA, USA, Sep 12 – 14th)


Exhibit Location:

Hyatt Regency Orange County
11999 Harbor Blvd.
Garden Grove (Anaheim), California, USA, 92840

Exhibit Hours:

  • Monday, September 12 5:00 PM – 9:00 PM
  • Tuesday, September 13 9:30 AM – 5:30 PM
  • Wednesday, September 14 8:30 AM – 1:30 PM


Our 2016 New Developments includes:

TLP Based CDE Test Solution for USB, HDMI, etc…

100 A Compact TLP Pulse Generator & IV-Curve System

Extension Pulse Module for IV-Curve Characterization, including HBM, LV-Surge, etc…


Please visit us at Booth 404 !

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TR002 PV Module Diodes TLP Test Report

SEM image of die surface from ESD damaged PV bypass diode sample, melted metal and silicon observed

Download or View in PDF: TR002_PV Module Diodes TLP Test Report

Bypass and blocking diodes inserted across the strings of the solar panel arrays are found to be susceptible to potential electrostatic discharge (ESD) events. The objective is to explain the theory behind the ESD damage and the proper test and analysis methods for ESD failure of PV module diodes. To demonstrate the proposed test methodology, some diode models supplied by a solar panel arrays manufacturer were evaluated.


by Wei Huang, Jerry Tichenor, Yingjie Gan, David Pommerenke,

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ESDEMC Project Development Capability

ESDEMC Technology LLC is a high technology company specializing in the development and manufacturing of test and measurement products and services. Our team has extensive experience in the development of challenging systems in the area of high voltage, high frequency, complex systems.


Our current design capability cover the following areas:

1 . High-Speed Analog and Digital Designs on the Module or System Level

2.  Microcontroller/ DSP/ FPGA / Programming

3. High Frequency Circuit and System Development up to 40 GHz

4. High Voltage Circuit and System Design up to 300 KV

5. LABVIEW / MATLAB / Visual C++/ Visual Basic Programming Projects

6. Mechanical Design, CNC Machining, Rapid Prototyping, 3D Printing


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PB2016.02 ESD Failure Analysis of PV Module Diodes and TLP Test Methods

Download PDF – ESD Failure Analysis of PV Module Diodes and TLP Test Methods

Bypass diodes inserted across the strings of the solar panel arrays are essential to ensure the efficiency of the solar power system. However, those diodes are found to be susceptible to potential electrostatic discharge (ESD) events in the process of solar photovoltaic (PV) panel manufacture, transportation, and on-site installation. Please refer to [1], where an International PV Module Quality Assurance Forum has been set up to investigate PV module reliability, and Task Force 4 has been setting guidelines for testing the ESD robustness of diodes used to enhance PV panel performance.

This article explains the theory behind the ESD damage and the proper test and analysis methods for ESD failure of diodes. To demonstrate the proposed testing methodology that follows, we will be evaluating six different types of diode models as supplied by our customer, who manufactures solar panel arrays.


Bypass and Blocking Diodes in Solar Panel Arrays

To help maintain the efficiency and performance of solar panel arrays it is common for bypass diodes to be inserted across individual PV panels, and blocking diodes to be inserted in series with a string of panels that are used in a parallel array (see Figure 1). The bypass diodes provide a current path around a shaded or damaged panel. If these are not installed, the panel will act like a high impedance load when shaded. This effectively reduces the series string output as the current produced by the remaining series connected panels will be forced to go through the shaded panel, thereby reducing the voltage output of the string.

If the bypass diodes are installed, and one of them fails due to ESD, it typically fails to a short circuit. When this happens (see Figure 2), the shorted diode does not allow any power produced by its panel to enter the system, thereby lowering system efficiency. Blocking diodes keep current from the battery pack, or a parallel panel string from entering a damaged string. This is important at night when the panel array cannot provide any power, thus providing a path for the battery to discharge. When installed, the blocking diodes may have leakage current on the order of nano- or micro-amps. However, if they fail due to ESD, they typically fail to a short circuit providing another path for the battery to discharge. This discharge current can be milli-amps or amps. (See Figure 3 for an example of this failure scenario.)

Failure of even one of these diodes in the field is very expensive for companies to replace due to the need for a qualified service technician, as most installations will require code requirements to be met. Continued operation of the panel array with a damaged bypass or blocking diode will, at best, hamper the array’s efficiency and, at worst, cause permanent damage as it consumes power rather than produces power. It has been proposed that the damage to the diodes is caused by ESD stress.

What is ESD and how it damage the solar PV module diodes?

ESD is the sudden flow of electricity between two electrically charged objects caused by contact, an electrical short, or dielectric breakdown. Electrostatic discharge stress can occur in many forms and, depending on the characteristics of the stress, can damage different parts of solar PV module subjected to the stress. In particular, there are several ESD models with industrial standards that describe the pulse shape, source impedance, and determines levels at which the device should survive.

The commonly used ESD models (Table 1) are the Human-Metal Model (HMM) (IEC 61000- 4-2 for system level ESD testing or ANSI/ESD SP5.6-2009 for component level ESD testing), the Human-Body Model (HBM) for component level ESD testing (ANSI/ESDA/JEDEC JS-001-2014), and the Charged-Device Model (CDM) for device level ESD testing (ANSI/ESDA/JEDEC JS-002-2014). There is also the Machine Model (MM), but it has been discontinued due to poor repeatability. Further, a new ESD model that currently has no established industrial standard, but has a different damage effect is the Cable Discharge Event (CDE).

Human Metal Model (HMM)

The human-metal ESD can take place when a charged person holding a pointed metal object, like a screwdriver or a ballpoint pen, rapidly moves the hand against an electronic device. In regard to PV module bypass and blocking diodes, this type of ESD events would most likely occur during junction box assembly with metal tools like tweezers, pliers, or screw drivers, etc. Figure 4 demonstrates a HMM event between a screwdriver and a screw that is part of an electrical installation in the junction box.

Human-Body Model (HBM)

Human-body model simulates the transfer of charge from a human to a component, such as through a fingertip as a device is picked up. This model is one of the most commonly used ESD tests for component qualification. In regard to PV module bypass and blocking diodes, this type of ESD event would also most likely occur during junction box assembly, especially if the operator picks a diode and mounts it by hand into the junction box. Figure 5 demonstrates a personnel picking up a PV module diode with bare fingers.

Charged-Device Model (CDM)

Charged-device model simulates the transfer of charge from a device to ground. A device can collect charge by sliding across a surface and then discharged by contact to a metal surface or ground. In regard to PV module bypass and blocking diodes, this type of ESD event would most likely occur during junction box assembly.

Transmission Line Pulse (TLP)

The TLP technique is based on charging a transmission line to a pre-determined voltage, and discharging it into a device under test (DUT). The cable discharge emulates an ESD event that has better defined RF signal path, controllable rise-time, and pulse width. The test setup allows transient current and voltage waveform to be monitored. Therefore, the change of the DUT impedance can be monitored as a function of time in ps details. The DUT performance degrade or failure check can be automated with RF high voltage switch and help the system with faster ESD performance analysis. Regarding to the PV module diodes, this model is not a real-world event as the transmission line would not be well defined as the TLP model, but the type of waveform is relatively similar to cable discharge events (CDE) during the PV module on-site installation process.

Cable Discharge Event (CDE)

A cable discharge event is a frequent real-world electrostatic discharge event that occurs when a cable is connected onto a device and the cable has existing charge prior to making the connection. This can also happen by connecting a charged cable (open on one end) to a device. It occurs because there is a potential differential between the charge on the cable to be connected and the device. The resulting waveform is highly dependent on the real-world current return path and specifications of the cable.

However, these events usually have a fast rise time of less than 500ps, potential for high current that can reach over 100 Amperes, and a potential long pulse that can be several µs if the discharging cables are long. The fast rise time, high current, and long pulse duration can result in a permanent performance degrade or physical damage of device being subjected. Regarding to solar PV module, the cable connections between the panels can be very long, resulting the ESD current waveform could be very different from all previous cases. Because cable connection is an avoidable on-site installation process, cable discharge event should be treated as a special ESD case with special test setup for the PV module diodes quality assurance.

Although these ESD models describe how an ESD stress event may originate, the underlying physics of these models point to two basic damage causes. Damage may occur as the device cannot withstand the extremely fast voltage transient, or a device is not able to handle the current or the heating caused by the current. Here, the heating occurs within nanoseconds, such that there is no thermal exchange with the surrounding. Further, the current distribution within the conduction area of the device may not be homogeneous, such that local melting (“filament creation”) leads to damage at current levels that the device could handle, if the current would flow with equal current density in the device.

The CDM model is used to qualify a device for the first of these damage types in that a very fast rise time as 100 ps with a short duration pulse. This test can determine if the gate oxide layer of a component is susceptible to a CDM type of event. The HBM model is used to qualify a device for the latter of the damage types in which a long duration (100ns) pulse is applied. The HMM, CDE and TLP models could possibly contain both types of damage. However, the CDE or TLP type of model would result in the worst possible damage in all of the cases discussed above.

An example of damage to the semiconductor components is shown in Figure 7 which illustrates burn track damage on a PV bypass diode caused by ESD.


Given the nature of how the bypass and blocking diodes could be exposed to and damaged by ESD events, the worst case that would be the cable discharge event, in which both fast rise-time and high energy pulses occur during the installation process. Therefore, based on the existing industrial ESD testing methods, we propose to use the transmission line pulse test method that does not necessarily replace the IEC 61000-4-2 standard, which may have been be used in the current qualification process. Instead, the TLP test method subject a diode (a low resistance DUT) to a faster rise-time and higher energy pulse up to 180A (pulse reflections being allowed to approach the real-world CDE case). This provides a fully-automated device ESD performance characterization system for transient IV signal and degrade/failure inspection before and after each pulse. Compared to the other types of ESD models, the advantages of using a TLP test are:

Well Defined Consistent Waveform Shape: Both circuit and waveform defined in ESD simulator standards are too flexible (no impedance control for test path, 30% tolerance at only certain time) This causes ESD simulators to provide very different ESD test results between different test sites. A TLP pulse is very clean and consistent.

Highly RepeaTable Test Setup: Fatigue from holding ESD simulator by hand can lead to inconsistent test setups. In TLP testing with jigs for mounting the DUT, a more controlled test is obtained.

Fast Automatic Measurement and Reporting: Typical TLP testing is done with full automatic control of oscilloscope scale adjustment, voltage pulsing, failure criteria checking, and IV curve update.

Important Device Behavior is recorded for ESD analysis and design: Many useful parameters can be extracted from TLP tests for device transient behavior analysis, modeling and system-efficient ESD design (SEED). Traditional ESD tests only generate pulse for pass/fail results.

Test Setup

The TLP test setup is shown in Figure 8. A transmission line pulse (TLP) generator provides a rectangular voltage pulse by charging a 50Ω transmission line to a test voltage, and discharging the pulse to the DUT by a special relay which can withstand the voltage, and can switch to an on “on” status without bouncing. The pulse then travels out of the TLP through a coaxial transmission line where it first reaches a high voltage relay (A621-HVLKR).

This relay is capable of withstanding up to 10kV, and is required for the high current TLP testing used with these high power diodes. The relay provides a means of transferring connection of the DUT between TLP measurement system and the failure detection system. In particular, during TLP pulsing, the relay connects the DUT to the TLP, the measurement probes, and the oscilloscope. After each TLP pulse test waveform has been captured, the system switches the DUT to the SMU to measure the diode reverse leakage current at maximum recurrent peak reverse voltage (VRRM). The A621-LTKSEM leakage test module also helps to facilitate these connection changes on the low voltage side of the measurement probes.

The DUT current is measured indirectly using a resistive tee to voltage measurement. The current is recovered by the overlapping reflection method. This method measures both the current through and the voltage across the DUT, but for lowresistance devices, such as a diode in the “on” state, this method is not well suited for measuring the device voltage. Instead, the DUT voltage is measured directly at the device, providing a highly accurate voltage probing measurement. The current measurement is performed by first measuring the pulse as it passes by the first pickoff resistor that goes to Ch1 of the oscilloscope. A short delay later (as determined by the length of coaxial cable between the pick off resistors), the pulse reflected from the DUT is measured at the same pick off resistor yielding an overlapped waveform. Using transmission line theory and a pre-measurement calibration pulse, the current into the DUT can be determined as:

Where V+, V- , and Zo are the incident pulse, reflected pulse, and characteristic impedance (50Ω) of the transmission line system, respectively.

Test Procedure

The test procedure is demonstrated in the flowchart shown in Figure 9. Upon entering the test loop, the system measures the leakage current of the DUT to obtain the initial degrade measurement. Next the TLP charge voltage is set. For the testing reported in this article, the charge voltage was set to sweep from 500V to 9600V, in 100V increments. For the first test point, the oscilloscope scale and trigger level are set based on the initial charge voltage and a 50Ω DUT. As testing progresses, the scale and trigger level are set based on if the waveforms clip, or is under scaled. If the waveforms do not clip or are not under scaled the settings are kept.

After setting the oscilloscope parameters, the DUT is pulsed and the captured data is compared to the oscilloscope display range for each captured channel to check for clipping and whether the scale is appropriate. If any of the waveforms are clipped, the scale is adjusted and the DUT is pulsed again. If the waveforms are ok, or under scaled, the data is accepted and processed. Any under scaled waveform corrections are made on the next pulse level. Processing is completed by scaling the data by the measurement attenuator and probe values.

Another DUT degrade/failure measurement (measure the PV diode leakage current under reverse working voltage) is made to determine if the DUT has failed or not. If failure occurs, the test is stopped. If. If not, the next pulse point is performed. This repeats until all pulse points are done, or failure occurs.

Dynamic IV Curve Measurement Principles

One of the goals of the measurement system described above is to obtain the dynamic IV curve of the DUT over the voltage range pulsed. Current and voltage waveforms resulting during pulse test are demonstrated in Figure 10. The dashed lines near the end of the pulses represent the start and stop points of the dynamic IV measurement window.

The measurement window is typically 70 to 90% range of the pulse but other ranges can be selected. Over this window, the average value of the time waveform is taken as the current and voltage, respectively. This value is then plotted for each voltage pulse applied.

Degrade/Failure Measurement (Leakage Current Measurement)

The leakage current was measured using the source meter unit (SMU) and, depending on the diode tested, the bias voltage was varied between two and three different voltages with the maximum bias voltage set to the maximum recurrent peak reverse voltage (VRRM) for each diode. The VRRM voltage is listed in each individual diodes datasheet.

Also, for the results reported below, for any diode that failed the leakage current upper limit was set to 2.5mA (a value that is very high and can be treated as failure criteria). This is the compliance limit of the SMU and is not an indicator of diode characteristic after failure, other than they appear to fail to a short.


Over the years, ESDEMC Technology has tested several diode models for solar PV module companies. The VRRM (from device datasheet) of the diodes are listed in Table 3. The VRRM values are important because they provide the maximum bias voltage applied to the diode for leakage current measurement. This value is supplied by the device manufacturer, and is typically found in their respective datasheets.

In the following sections, the test results will be presented in terms of the best performer to the worst performer in regard to diode failure during TLP testing.

Sample Set #5

Out of the 80 devices we tested in Sample Set #5, no failure occurred. The dynamic IV and leakage current curves for three samples are shown in Figure 12. The dynamic IV curve is read from the Y-axis to the bottom of the X-axis, and the leakage current from the Y-axis to the top of the X-axis. Note that the top of the X-axis is logarithmic due to the dramatic change in leakage current once a device fails to a short circuit.

Sample Set #3

The next best performers were the devices in Sample Set #3, which had only one diode fail out of one hundred units; failure occurring near the last few test pulse levels. The dynamic IV and leakage current curves are shown in Figure 14. Once the diode failed to a short, the resulting leakage current was at the compliance limit of the SMU, and is not an indicator of the diode condition.

Sample Set #6

Sample Set #6 had eleven failures out of eighty diodes tested. The minimum, maximum, and average pulse current for each of them are listed in Figure 25, and the dynamic IV and leakage current curves, for three of the failed diodes, are shown in Figure 16.

Sample Set #4

Sample Set #4 had 18 devices fail out of 100 tested. The dynamic IV and leakage current curves, for three of the failed diodes, are shown in Figure 18.

Sample Set #2

All of the diodes in Sample Set #2 failed. The minimum, maximum, and average pulse current for each of them are listed in Figure 25, and the dynamic IV and leakage current curves, for three of the failed diodes, are shown in Figure 20.

Sample Set #1

All of the diodes in Sample Set #1 failed. The minimum, maximum, and average pulse current for each of them are listed in Figure 25, and the dynamic IV and leakage current curves, for three of the failed diodes, are shown in Figure 22.


Of the diodes tested, only those in Sample Set #5 did not have failure up to 200 Amp or 10 kV of the eighty diodes tested. The next best performer was Sample Set #3, which only had only one failure, and that particular diode failed near the last few test pulses (100 diodes tested). Sample Set #6 had ten diodes fail out of eighty tested, and the Sample Set #4 had eighteen diodes fail out of one hundred tested. The worst performers were those in Sample Sets #1 and #2, where all diodes failed (all diodes tested failed for both models).

The chart shown in Figure 25 depicts the minimum, maximum, and average pulse current at failure for the diodes that failed.

It has been suggested that it is not necessarily the diode design type that determines if the diode is more or less susceptible to ESD stress, but instead a result of quality control of the manufacturing. For example, the process may be as follows: a diode as the 15SQ100 (tested data is now shown herein) is being checked in quality control after manufacturing. Its reverse breakdown voltage is checked. If it does not pass 100V, but passes 50V, it is re-labeled as a 15SQ050 model. This may not guarantee that the 15SQ50 model is a higher quality 050 design, and may instead be a poor quality 100 design relegated to the 050 model line. Here, the problem is that the diode may not hold 100V reverse voltage due to a local defect. The local defect will concentrate the current during ESD into a very small area and cause the diode locally to melt. Thus, the robustness of such a diode is much worse than a diode that passes the 100V reverse voltage, which may indicate that it does have few, and less severe local defects.

According to our customers (solar solution providers), our findings on the diode failure rate, through TLP test methodology, correlates to their field return failure rate. Therefore, we recommend that TLP testing be performed for all solar PV module diodes. In addition, it may be in the best interest of both solar PV module and diode manufacturers to investigate the quality control of the diodes selected, yielding a more reliable design for field use.

Read more:

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PB2015.12 System-Level Modeling for Transient Electrostatic Discharge Simulation

Download PDF – System-Level Modeling for Transient Electrostatic Discharge Simulation

Abstract—This paper introduces an improved electrostatic discharge (ESD) system-level transient simulation modeling method and discusses its validation using IEC 61000-4-2 ESD pulses on a real-world product. The system model is composed of high current and broadband (up to 3 GHz) models of R, L, C, ferrite beads, diodes, and integrated circuit IO pins. A complex return path model is the key to correctly model the system’s response to the IEC excitation. The model includes energy-limited time-dependent IC damage models. A power–time integral method is introduced to accurately determine if a junction would experience thermal runaway under an arbitrary injection waveform. The proposed method does not require knowledge of the junction’s microscopic geometry, material information, defect location, or melting temperature.


Index Terms—Common mode, electromagnetic compatibility (EMC), electrostatic discharge (ESD), human metal model (HMM), IEC 61000-4-2, system efficient ESD design (SEED), transmission line pulser (TLP).


Recent studies have shown that system-level electrostatic discharge (ESD) simulation can serve as a powerful tool for analyzing ESD performance [1]. The simulation enables the design of reliable protection on the first attempt and avoids the need for repeated design optimization tests.

The concept of ESD simulation has been promoted as an option in system-level ESD efficient design (SEED) [2]. SEED emphasizes the analysis of the interaction between the quasistatic I–V curve of a vulnerable pin and the pin’s external protection. Gossner et al. applied SEED for analyzing an IO pin’s response to ESD for different on-board protection solutions [3]. Monnereau et al. extended the modeling framework by adding trace and package models, and validated their method with an inverter circuit under a 100 ns transmission line pulser (TLP) excitation [4]. Li et al. previously published a hard error analysis of a cellphone’s keyboard illumination circuit based on a 35 ns TLP source [5]. Orr et. al used similar method to characterize IC pins [6].

Although the SEED simulation offers greatly improved system-level ESD design, some issues remain unresolved. A TLP-excited system simulation may not substitute IEC/HMM [7] excited analysis in certain cases. TLP-based simulation results may be valid when the damage is caused by the IEC’s second peak (residue portion), which has a long duration and can be mimicked by a TLP pulse. It does not reflect the consequences of the first few nanoseconds of an IEC excitation. In addition, as an IEC waveform passes through a complicated system, the resulting injection on a vulnerable part could be in an arbitrary shape and, thereby, break a fixed empirical HMM-IEC relation [8]. A TLP source is not suitable for modeling soft error, near-field coupling or signal integrity (SI) problems caused by an ESD injection. Due to the above reasons, many researches have moved forward to perform ESD transient simulation under IEC/HMM excitations [9]–[13].

It is difficult to convert a TLP-based simulation into an IEC setup directly by substituting the TLP model with an ESD gun model, based on a real product system. Compared to a TLPbased model, an IEC source-based setup requires more sophisticated modeling on the current return path in order to achieve an accurate circuit response under ESD tests. Furthermore, intensive use of flex-printed circuits (FPCs) for connecting multiple PCBs creates complex return paths. Among the recent publications that researched system-level IEC simulation, some showed less accurate results compared to measurement, especially at the very first nanosecond, e.g., [11]. Some demonstrated excellent modeling results, but the investigated problems were only at the PCB level rather than the real product level due to the lack of complex return path structures, e.g., [12] [13].

In addition to modeling the PCB-based and IC internal ESD protection structures, a failure criterion is needed. Using only a TLP-derived constant failure, current threshold [13] may be insufficient if this threshold is only surpassed for a few nanoseconds. This will be the case if the initial peak of the ESD current surpasses the threshold but the second peak remains below it. As Notermans et al. concluded in [8], “For a real system, dynamic failure must be taken into account as well.” Particularly, it will be shown later in this paper that a complex network could introduce an oscillatory current waveform inside the system, thereby making a constant current threshold inapplicable. The dynamic failure according to junction overheat was investigated by Wunsch and Bell [14], who characterized the failure model with the tested pulse–power relationships. Later, several researchers such as Yiquan Cao, applied the thermal failure model in ESD scenarios [15].

In the study presented in this paper, we modeled a cell phone circuit in realistic IEC testing scenarios. The state of the art of this paper includes the following four parts. First, typical components (R, L, C, ferrite beads, and semiconductor devices) under high-current and high-frequency excitations are modeled. Second, a detailed model of the complex return path inside the phone is presented. Finally, a time-dependent destruction model and power–time integral method is introduced to accurately determine if a junction would suffer thermal damage under an arbitrary injection waveform. The checking algorithm is an extension to Taska’s work [16].

The remainder of this paper is organized as follows. Section II describes the product under investigation. The test systems and methods for creating the model are introduced in Section III. The component models are shown in Section IV. Section IV presents the semiconductor’s failure model and discusses the development of the thermal runaway criterion of a junction under an arbitrary waveform. Section VI mainly discusses the ESD gun model and common-mode path modeling. Section VII shows the validation of the system-level model and the model’s application for hard error analysis.


A vulnerable keypad backlight LED circuit in a smart phone, as shown in Fig. 1, was investigated. The driver IC controlled the LED’s brightness by varying the IO pin’s state. All component information will be kept confidential because of intellectual property constraints. ESD tests indicated that the LED was a sensitive zapping point. During product-level tests, airmode discharge sometimes struck through the aperture between the plastic buttons that covered the LED and coupled into the illumination circuits.

At first glance, the circuit’s behavior under ESD appeared somewhat complex for the following reasons: 1) L–Cpairs could cause resonance; 2) ferrite beads and capacitors may saturate or show nonlinear behavior under high-current injection; and 3) the keyboard PCB was connected to the main PCB through an FPC, which introduced a complex return path for the ESD current.


A component model was created based on an RF model and a device model obtained under high current, as shown in Fig. 2. This combination ensures sufficient accuracy under IEC 61000- 4-2 or HMM excitations. Based on the 0.7–1 ns rise time and the response of nonlinear elements, a modeling bandwidth of 3 GHz was selected. Z-parameters were used to obtain the RF model.

The high-current I–V curves were extracted using a 1540 ns adjustable TLP pulse (see Fig. 3), which is long enough to extract a stabilized result yet avoid damaging the DUT. To control the parasitics of the test setup, inductances were minimized, e.g., a circular arrangement of five 10-Ω resistors was used to create a broadband 2-Ω current measurement shunt.


A. Semiconductor Devices

Similar measurements were used to determine the VI behavior of LEDs, Zener diodes, and IC pins. The only difference was that the IC was powered to ensure the same operating conditions as those encountered during system-level testing.

The Zener diode’s transient I–V curve appears in Fig. 4, as does a behavioral model developed by fitting this curve. Diode 11 defined the I–V characteristics of the Zener diode under negative pulses applied to its cathode; diode 10 and the switch (actually, a voltage controlled resistor) determined the positive I–V characteristics. Diode 9 was used as a unidirectional switch to separate the positive and negative pulse injections.

The capacitance of the Zener diode was measured using a vector-network analyzer (VNA). Due to its large value of 25 pF, it was determined that the diode would carry most of the current during the first nanoseconds of the ESD pulse.

The LED model (see Fig. 5) is based on a similar concept. It has two parts: the factory-provided SPICE model for nominal current conditions, and two voltage-controlled resistances to mimic the high-current I–V behavior. The factory model already included the capacitance, so no external RF model is needed here.

The IO pin on the driver IC was modeled as a three-terminal device. First, a TLP was used to obtain the power clamp of the Vcc network (Diode 3 in Fig. 6). Then, the high-side (DIODE1) and low-side (DIODE2) protection diodes of the IO pin were measured by applying positive and negative pulses to the IO pin, respectively. Finally, using a VNA, the values of the linear components (C, R, and C33) were derived. The 300-pF-power rail capacitor is a combination of junction, gate, and metallization capacitance. The system contains a large 2-μF on-board capacitor placed in parallel.

B. Capacitors, Ferrite Beads, and Inductors

The voltage across a capacitor may lead to sparking, capacitor breakdown, and a recoverable change in the capacitance value [18], [19]. Fig. 7 shows the voltage and current of a 10-V-rated 10-nF X7R capacitor that was excited with a 15 ns 3 kV TLP. Although the charge current was constant, a nonlinear voltage increase occurred. This indicates that the capacitance decreased as the voltage increased. The capacitance variation over time, or C(t), can be calculated from the measured voltage and charging current waveform

The C–V behavior was approximated by an arc–tangent function (2) to account for this C–V behavior, although other researchers have shown that quartic functions can work equally well [20]

where A–D tune the model, as shown in Fig. 8. For this specific capacitor, the best match was achieved at A = 18, B = 2.2, C = 2.8, and D = 7.

Using the arc–tangent function, together with equivalentseries-resistance and equivalent-series-inductance obtained from measured Z-parameters, a complete capacitor model can be created in Agilent’s Advanced Design System [21].

Not all capacitors behave nonlinearly under ESD. The low dielectric constant of NP0 ceramic will show little or no nonlinearity; however, the low capacitance values achievable with small-package NP0 capacitors may spark over.

Similar to capacitors, ferrites may exhibit saturation or other nonlinear behavior under high-current conditions. The nonlinear inductance can be approximated using the following:

In certain cases, the additional high-frequency noise on the measured I(t) may cause dI/dt to change significantly, thereby interfering with the calculated L(t). To calculate the L(t), one could either perform low-pass filtering on the tested raw data, or use

 V (t)dt I (t) to calculate.

The inductance–current relationship can be modeled by a nonlinear arc–tangent function, as used in capacitor modeling. Here, we used an alternative method, a quartic equation, for modeling

where I stands for the current flow through the nonlinear inductor; L0 is the initial/nominal inductance; and Lsat represents the saturated inductance. A = 2 and B = 1 for the specific ferrite we tested. Fig. 9 shows the modeled curve of a ferrite with an equivalent 60-nH inductance that can be saturated to 20 nH.

The complete model of the ferrite appears in Fig. 10. Besides the nonlinear inductance model (SDD1P), other linear models can express the effect of the capacitance and loss following Yu’s topology [22]. These linear parts usually can be found in a device’s datasheet and can be checked by measuring the S-parameters. This model does not take hysteresis into account because the ferrite bead uses soft magnetic materials that exhibit no relevant hysteresis [23].


A. Failure Power Models

To determine if a specific ESD will damage a device, its robustness threshold must be known. As discussed previously, a simple current threshold may not be sufficient; a dynamic threshold will better predict complex waveforms, such as an HMM discharge. Using a TLP with a varying pulse width, the damage threshold function (see Fig. 11) was created. The TLP current decreased as the pulse length increased, indicating that the device was energy limited.

Semiconductor devices under electrical over stress (EOS) have many microscopic failure mechanisms, e.g., surface breakdown around a junction and internal body breakdown through a junction. However, as Wunsch noted in [14], most failure mechanisms are linked primarily to the junction temperature. The widely used junction thermal model was developed by Wunsch and Bell [14], and later, Taska [16]. Their thermal analysis yielded the failure power (P) per unit junction area (A) as a function of the rectangular pulse width (tp ):

where K1 , K2 , and K are design-specific parameters that relate to the junction material and conductivities. The resulting curve of (5) appears in Fig. 12.

The parameters K1 , K2 , and K may not always be derived explicitly from junction design because in many applications, the material information and junction geometries are not known. They can be determined, however, by fitting the measured curves, as shown in Figs. 13 and 14.

B. Failure Criteria

To determine device failure under time-varying waveform P(τ ) based on the knowledge of the TLP tested failure power/time relationship P0 (t), one can identify whether or not any portion in P(τ ) injected the same amount of energy as a certain destructive rectangular pulse.

This idea can be derived from heat transfer equation [25]

where T is the junction temperature, ρ is the density, Cp is the specific heat capacity, D is the thermal diffusivity, and q(t) is the heating rate per unit volume. The Green’s function, or the solution to this function, is

The Green’s function is known as the impulse response in both the time and spatial domains. As an injection source P(r

 ,τ ) heating a defect volume Δ, the temperature at an observation location r (the vulnerable point) at time t can be written as [26]

where T0 is the initial ambient temperature.

A rectangular pulse with an amplitude of P0 and a duration of tf can damage a semiconductor junction because the failure point temperature reaches the failure temperature Tc

If an arbitrary injection profile that starts at an arbitrary time τ0 can also generate the same amount of heat within a duration of tf

This arbitrary waveform can be considered destructive. Therefore, the heat contribution of this arbitrary waveform to its equivalent rectangular pulse can be related as

The rectangular pulse failure power P0 is a function of duration tf (the failure power–time model in Section V-A), so the failure criterion is written as

Note that the power–time integral must be performed in an assumed failure time span tf ; otherwise, the integral of heat transfer function G cannot be eliminated. This is intuitive; if the injected arbitrary wave’s energy reaches P0 (tf ) tf over a longer span than tf , the junction temperature may still be lower than Tc because more heat has dissipated.

an Tc because more heat has dissipated. Equation (12) allows a devices’ thermal failure to be evaluated without knowing its material, geometry, failure location, or melting temperature. Only its tested failure model P0 (tf ) and simulated time-varying power profile P(τ ) are needed. Equation (12) can be implemented with the following algorithm:

Equation (12) can be simplified further if τ0 = 0, or, if the highest power portion always occurs at the beginning of an injection (usually the case for an ESD event). The criterion, therefore, is simplified as

The interception point of the left and right sides of (13) stands for the failure time and destructive injection energy (but not the energy that heats the defect region).

Section VII contains examples of applying the failure criterion.


A. System-Level Test Setup and Modeling

A contact-mode discharge on the DUT setup is shown in Fig. 15. A cellphone’s battery charging cord, filtered with a ferrite, was connected to the cell phone’s USB port as part of the return path. The cord’s shielding at the other end was shorted to a large metal plane.

In such a test setup, the ESD current return path (commonmode path) and the ESD generator should be modeled in order to correctly calculate the ESD current within the circuitry under investigation.

B. System-Level Grounding Model

For the system test setup shown in Fig. 15, the connection between the cell phone’s ground (metal frame) and the main ground plate can be modeled as shown in Fig. 16. The transmission lines TL1 and TL2 modeled the IO and Vcc nets on the double-sided flex circuit, respectively. The characteristic impedance was measured as 45Ω with a TDR. This impedance can also be calculated from the flex’s 2-D cross-sectional geometry. TL1 and TL2 were not referenced to the same metal; instead, their left sides were connected to the keyboard PCB’s local ground, and their right sides were shorted to the main PCB’s reference plane.

The transmission line TL3 modeled the flex’s ground metal relative to the cellphone’s body frame metal. The characteristic impedance of this common-mode path was measured as 120Ω.

C. ESD Gun Model

An ESD generator, TESEQ NSG 438 [27], was used in this project. Its equivalent circuit model appears in Fig. 17, which was developed based on Wang’s topology [28].


A. System Model Validation

The system model was constructed by inserting all of the circuit models developed as described in Section IV, as well as the ESD gun model, into the system scheme shown in Fig. 16.

Fig. 18 shows one of our most challenging validation setups used for checking the model’s credibility and the robustness of the modeling methods. A Tektronix CT-6 probe was inserted in front of the IO pin to measure the ESD current flowing into the IC. To allow the current probe to be placed, an 8-mm-long wire was soldered in-series to the IO pin. This wire introduced an additional 4-nH inductance. The simulated current conformed to measurements reasonably well (see Fig. 19). The difference between simulated and measured results can be quantitatively described with the feature selective validation technique [29]– [31].

B. Application of the System Model for ESD Hard-Error Analysis

1) Transient Current Flows Into the LED: One objective was to determine the conditions under which the LED would suffer damage. Calculating the destruction criteria (12) on the simulated power profile and the LED’s failure model, respectively, showed that under +14 kV, the LED would be damaged (see Fig. 20), which agreed with our tested result. The checking algorithm also showed that under 15-kV injection, the damage would occur within the first 5 ns; under 14 kV, the damage occurred at 32 ns. Fig. 21 shows the result of the simplified checking algorithm (13).

2) Thermal Failure of the Driver IC: Another objective was to analyze the conditions under which the driver IC could survive without any external protection (same setup as shown in Fig. 18, but with a 10-nF nonlinear capacitor in parallel to the LED to avoid LED destruction).

By applying (12), we were able to predict that the driver IC could survive under 15 kV but would not withstand a 16-kV injection (see Fig. 22). This prediction also agreed with our tested results.


The transient response of a real cell phone product under IEC 61000-4-2 excitation was modeled. The proposed method features both high voltage/current and high speed (up to 3 GHz) modeling of typical components, including R, L, C, ferrite, diodes, and IC pins, as well as a complex return path model. The simulation result resembled the tested waveform at both the first and second peaks of the IEC excitation.

The time-dependent destruction threshold of a semiconductor device can be obtained from the tested Wunsch–Bell model with rectangular waveforms. This model accounts for thermal-related junction failures, which have been proven to be the primary cause of a semiconductor junction’s failure mode under EOS.

To determine the device failure under an arbitrary waveform based on the knowledge of the TLP tested failure power/time relationship, one can identify whether or not any portion in the arbitrary waveform P(τ ) injected the same amount of energy as a certain destructive rectangular pulse. Our proposed checking algorithm (12) and its simplified version (13) can be applied for IEC excitation scenarios. For other injection profiles in which the power peak does not occur at the very beginning of the whole waveform, (13) cannot be applied. It must be noted that the checking algorithm is based on a thermal failure model. In rare cases when a component is vulnerable to voltage breakdown, one needs to compare the simulated voltage profile to the TLP The proposed model is very suitable for both pre- and postdesign analysis due to its high computational efficiency. An engineer can quickly understand the holes in a design as long as off-the-shelf circuit models and failure threshold models can be provided readily by the device vendor. Besides using an extracted equivalent circuit model, one may model the return path more precisely with its geometry at the cost of computing time, as what have been done in [32]. A component can always be characterized with automated TLP and VNA measurements. characterized voltage threshold to predict if the device would damage. However, when a component is not available, one could model it from its geometry and material [33]. In addition to failure analysis, the system model also can be used to analyze ESD-induced interference in SI problems, with an additional coupling path model.


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TS002 Cable Discharge Event (CDE) Automated Evaluation System Based on TLP Method

Download Cable Discharge Event (CDE) Automated Test System Based on TLP Test Method (PDF)

What is CDE Event ? A Cable Discharge Event (CDE) is electrostatic discharge(s) between metal of a cable connector and the mating cable connector or plug. It is very common in daily life.

When CDE happens, transient high current and high voltage pulses are generated into the connector pins and cause potential damage to the system with connector. The pulse characteristic is determined by the cable type, cable length, physical arrangement of the cable and system with connector, and system with connector side circuitry.

As a pioneer and expert of Cable Electrostatic Discharge (ESD) solution provider, ESDEMC has been releasing several new Cable Discharge Event (CDE)  Automated Systems in the past 3 years. Lately, we would like to introduce our latest generic CDE system based on out latest TLP-MUX development.

MUX stands for Multiplexer, it allows many devices to be automatically tested with our ES62X series TLP system (our first TLP-MUX design works up to 32 devices). This allows the ESD reliability of different cable interconnection designs, such as the ESD reliability of USB, HDMI, VGA, DVI etc…, to be evaluated with detailed data analysis.


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Wei Huang

Wei Huang
Wei Huang
Wei Huang


Wei Huang received his M.S.E.E. from the Missouri University of Science and Technology in 2010 and B.S.E.E. from Beijing University of Posts and Telecommunications in 2007. He was a research assistant at the MS&T EMCLAB with interests of electromagnetic, electrostatic and RF designs. He is the founder  of ESDEMC Technology LLC and is focusing new ESD and EMC test solution developments.

iNARTE Certified EMC Engineer

Wei Huang has been an iNARTE Certified EMC Engineer from 2009 (The youngest iNARTE EMC Engineer, 23 years old )

Wei Huang has been an iNARTE Certified EMC Engineer since 2009 (The youngest iNARTE EMC Engineer, 23 years old )


Professional Preparation

  • Missouri University of Science and Technology (formerly UMR), USA, M.S.E.E, 2010.
  • Beijing University of Posts and Telecommunications, China, B.S.E.E, 2007.


  • Founder, ESDEMC Technology LLC, R&D Center 2010-Present
  • Hardware Engineer, Portable System EE Group, Apple Inc, 2009 summer.
  • Research Assistant, EMC Laboratory, Missouri University of Science and Technology (formerly UMR), 2007-2010
  • Hardware Design Engineer, Product Design Group, Beijing HJH S&T Co. Ltd., 2005-2007


  1. W Huang , J Dunnihoo , D Pommerenke, “Effects of TVS Integration on System Level ESD Robustness”, 2010 International EOS/ESD Symposium, Reno, NV, USA, Oct. 3 – 8
  1. W Huang, D Liu, J Xiao, D Pommerenke J Min, G Muchaidze, “Probe Characterization and Data Process for Transient Current Reconstruction by Near Field Scanning Method”, 2010 Asia-Pacific Symposium on Electromagnetic Compatibility, Beijing, China, Apr. 12 – 16
  1. Xiao, D. Liu, D. Pommerenke, W Huang, P. Shao, X. Li, J. Ming, G. Muchaidze, “Near Field Probe for Detecting Resonances in EMC Application”, EMC COMPO 2009, 7th International Workshop on Electromagnetic Compatibility of Integrated Circuits, Nov. 17 – 19
  1. W.Huang, D. Pommerenke, J. Xiao, D. Liu, J. Ming, G. Muchaidze, S. Kwon, “A Measurement Technique for ESD Current Spreading on A PCB using Near Field Scanning”, Present on 2009 IEEE International Symposium on EMC, Austin, Texas, Aug. 17 – 21
  1. M. Giorgi, W. Huang, M. Jin, P. Shao, D. James , D. Pommerenke, “Automated Near-Field Scanning to Identify Resonances”, EMC Europe 2008, Hamburg, Germany, Sep. 8-1
  2. W. Huang, M. Jin, P. Shao, D. James , D. Pommerenke, “Automated Near-Field Scanning to Identify Resonances”, EMC Europe 2008, Hamburg, Germany, Sep. 8-1
  3. W. Huang, J Tichenor, D. Pommerenke, V. Pilla, P. Maheshwari, G. Maghlakelidze, “An Ethernet Cable Discharge Event (CDE) test and measurement system”, 2014 IEEE International Symposium on EMC, North Carolina, Raleigh, Aug. 3 – 8

Collaborators and Co-Editors

  1. David Pommerenke, members of the Electromagnetic Compatibility Laboratory at the Missouri University of Science and Technology
  2. Jerry Tichenor, Fredric Stevenson, members of the Product Development Center at the ESDEMC Technology LLC

Graduate Advisors and Postdoctoral Sponsors

  • Masters: Prof. Dr. – David Pommerenke.




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David Pommerenke

David Pommerenke
David Pommerenke
David Pommerenke

Technology Consultant, IEEE Fellow 

Dr. Pommerenke has been our technical consultant from the founding of ESDEMC Technology. His in-depth knowledge of Electrostatic Discharge (ESD) and Electromagnetic Compatibility (EMC) has greatly helped our team in the research and development of many of our products.


Professional Preparation

  • Technical University Berlin, Germany, B.S.E.E, 1989.
  • Technical University Berlin, Germany, Ph.D.E.E, 1995.



  • Professor, Technical University Graz, Austria, 2020-Present
  • Professor, Missouri University of Science and Technology, Department of Electrical & Computer Engineering, 2008-2019
  • Associate Professor, Missouri University of Science and Technology, Department of Electrical & Computer Engineering, 2001-2008.
  • EMC Research and Test Engineer at Hewlett Packard, Roseville, CA 1996-2001
  • Post-Doc at the Technical University Berlin, Germany 1995-1996
  • Research Assistant, Institute for High Voltage and Power Eng. Technical University Berlin, Germany 1990-1995


Five Most Relevant Publications

  1. Ghasr, Mohammad Tayeb, Mohamed A. Abou-Khousa, Sergey Kharkovsky, R. Zoughi, and David Pommerenke. “Portable real-time microwave camera at 24 GHz.” Antennas and Propagation, IEEE Transactions on, 2012, 60, no. 2, pp. 1114-1125.
  2. Fallahpour, M., M. Baumgartner, A. Kothari, M.T. Ghasr, D. Pommerenke and R. Zoughi, “Compact Ka-Band One-Port Vector Reflectometer using a Wideband Electronically-Controlled Phase-Shifter,” IEEE Transactions on Instrumentation and Measurement, October 2012, Vol. 61, no. 10, pp. 2817-2826
  3. Bishop, J. A.; Pommerenke, D. J.; Chen, G., ‘,A Rapid-Acquisition Electrical Time-Domain Reflectometer for Dynamic Structure Analysis ‘, IEEE Trans. Instrumentation and Measurement, 2011, Vol. 60/2 pp. 655-661,
  4. Muchaidze, G., Jayong Koo, Qing Cai, Tun Li, Lijun Han, Martwick, A., Kai Wang, Jin Min, Drewniak, J.L., Pommerenke, D., “Susceptibility Scanning as a Failure Analysis Tool for System-Level Electrostatic Discharge (ESD) Problems”, IEEE Trans. EMC, May 2008, Vol 50, No. 2, pp.268-276
  5. Koo, J., Cai, Q.; Muchaidze, G.,Martwick, A., Wang, K.; Pommerenke, D., “Frequency-Domain Measurement Method for the Analysis of ESD Generators and Coupling”, IEEE Trans. EMC, 49/3, August 2007, pp.504-511


Other Publications

  • Tianqi Li; Maeshima, J.; Shumiya, H.; Pommerenke, D.J.; Yamada, T.; Araki, K, “An application of utilizing the system-efficient-ESD-design (SEED) concept to analyze an LED protection circuit of a cell phone”, Electromagnetic Compatibility (EMC), 2012 IEEE International Symposium on, August 2012, pp. 346-350
  • Khilkevich, V.; Pommerenke, D.; Li Gang; Xu Shuai, “An inductive probe for the measurement of common mode currents on differential traces”, Electromagnetic Compatibility (EMC), 2012 IEEE International Symposium on, 2012, pp. 720-724
  • Jianmin Zhang; Drewniak, J.L.; Pommerenke, D.J.; DuBroff, R.E.; Zhiping Yang; Wheling Cheng; Fisher, J.; Camerlo, S.; “Signal link-path characterization up to 20 GHz based on a stripline structure”, IEEE Int. Symp. on EMC, 2006 14-18 Aug. Vol. 2, pp.356-361
  • Bhargava, A.; Pommerenke, D.; Kam, K.W.; Centola, F.; Cheng Wei Lam; , “DC-DC Buck Converter EMI Reduction Using PCB Layout Modification,” Electromagnetic Compatibility, IEEE Transactions on , Vol.53, no.3, pp.806-813, Aug. 2011
  • Abou-Khousa, M.A.; Ghasr, M.T.; Kharkovsky, S.; Pommerenke, D.; Zoughi, R.; , “Modulated Elliptical Slot Antenna for Electric Field Mapping and Microwave Imaging,” Antennas and Propagation, IEEE Transactions on , Vol.59, no.3, March 2011, pp.733-741


Synergistic Activities

  • US-representative to IEC TC77b
  • Member IEEE EMC Society, TC-9, Computational Electromagnetics
  • Editorial Board, EOS/ESD Symposium on EMC (1996 – 2000)
  • Editorial Board European EMC-2002
  • Member IEEE, Electromagnetic Compatibility and Dielectrics and Electrical Insulation society


Collaborators & Other Affiliations

Collaborators and Co-Editors

  • Daryl Beetner, James L. Drewniak, Richard E. DuBroff, and David Pommerenke, members of the Electromagnetic Compatibility Laboratory at the Missouri University of Science and Technology
  • Bruce Archambeault, Distinguished Engineer, IBM, TRP, NC;
  • Brice Achkir, Distinguished Engineer, Cisco, San Jose, CA;


Graduate Advisors and Postdoctoral Sponsors

  • Masters: Prof. Dr.-Ing Wilfried Kalkner.
  • Doctoral: Prof. Dr.-Ing W. Wilfried Kalkner.
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Transmission Line Pulse (TLP) Testing

Transmission Line Pulse testing, or TLP testing, is a method for semiconductor characterization of Electrostatic Discharge (ESD) protection structures. In the Transmission Line Pulse test, high current pulses are applied to the pin under test (PUT) at successively higher levels through a coaxial cable of specified length. The applied pulses are of a current amplitude and duration representative of the Human Body Model (HBM) event (or a Charged Device Model – CDM – event in the case of Very Fast TLP, or VF-TLP). The incident and reflected pulses are evaluated, and a voltage-current (V-I) curve is developed that describes the response of an ESD protection structure to the applied TLP stresses. The Transmission Line Pulse test is unique because the current pulses can be on the order of Amps, and the TLP test results can show the turn-on, snap-back, and hold characteristics of the ESD protection structure.

Transmission Line Pulse testing is useful in two very important ways. First of all, TLP may be used to characterize Input/Output (I/O) pad cells on test chips for new process technologies and Intellectual Property (IP). TLP is very useful in developing simulation parameters, and for making qualitative comparisons of the relative merit of different ESD protection schemes for innovative pad cell designs. Secondly, TLP may be used as an electrical failure analysis tool, often in combination with conventional, standards-based component ESD testing.

TLP testing is done according to the ESDA TLP test method, ESDA SP5.5-2014. TLP is quoted on a case by case basis, based on the scope of the work requested; estimated engineering time to perform the test, and customer requested reporting.

Applicable TLP Specs

  • ESDA SP5.5-2014 (ESD Association)
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General Project Design

General analog and digital circuit design, Radio Frequency design, PCB layout and prototyping, board population and testing. Programming of Micro Controllers, DSPs, and FPGAs. System level programming in LabView, Matlab, Visual C++, and Visual Basic. Mechanical design and machining available, and basic 3D printing.

General analog, digital, and Radio Frequency circuit design (to 40 GHz).

High voltage circuit and system design up to 100 kV.

Prototype PCB’s with board population and system testing for a turn-key solution.


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TR001 VF-TLP Performance of PIN-Limiter Diodes

3D Diode TransientResistance-Time-Voltage Surface Plot

Download or View in pdf: TR001_VF-TLP Performance of PIN-Limiter Diodes

The objective is to test the Pin-limiter diodes for their ESD performance. The end application for these diodes will be decided by diode parameters like the turn on voltage, dynamic resistance, diode capacitance and survival current. Based on these parameters the diodes can be chosen for ESD protection application suitable for the lab instruments.

The pin-limiter diodes were bought from different manufacturers like Cobham, Skyworks, Microsemi and Avago. These diodes were soldered in reverse bias orientation from the trace to ground on the evaluation PCB’s. They were first tested for their frequency response and then they were tested for the ESD performance using the VF-TLP setup. The results of these diodes measurements are shown in the subsequent sections of this report.



by Shubhankar Marathe, Jerry Tichenor, David Pommrenke, Wei Huang


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The Revolutionary ES620 Compact Pulsed IV-Curve System is Ready ! (TLP, VF-TLP, HMM, HBM, LV-Surge,etc…)

ES620 Compact IV-Curve TLP System

Our Most Revolutionary ES620 Compact Pulsed IV-Curve System !

We redesign and redefine a new TLP system. The improvements of the specification, scalability, and efficiency is so much that the new system deserves to be the beginning of affordable, compact and versatile pulsed IV-curve and failure analysis system (Not just TLP, but expandable for a comprehensive pulse failure analysis system). The code zero of the ES620 means the new beginning.


1. An ultra-compact system that you can pack and flight with our ES620 system for field failure analysis!

2. Even with smaller chassis, it still delivers superior specification (VF-TLP down to 60 ps rise-time or TLP up to 100 A ESD current injection level ! Enough to rival with any competitions in the market)

3. Our system always fits your budget and schedule with an entry-level system (25A model) starts from 60 K USD / 3 weeks lead time.

4. Unlimited possibility with great extension capability (HMM, HBM, EFT, LV-Surge, etc… modules optionally available, programmable pulse width and rise-time available)

5. Great integration compatibility, the system supports hundreds of IVI instruments on-the-fly!

6. Free technical consulting and supports (We help you with your difficulty, suggest the best solution for your application)

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ES614 ESD Air Discharge Workstation is Ready !!

The ES614 ESD Air Discharge Speed Controller


The ES614 Series ESD Air Discharge Work Station is ready as a product now ! Please visit the product page or download the pdf datasheet .


The Objective:

The air discharge ESD test and measurement has been a tough but inconsistent task due to the difficulty of holding the ESD simulator gun and zap at same spot, the inconsistency of the ESD discharge waveforms generated by different ESD guns designs.  The loosely controlled of IEC and ISO standard did not specify the air discharge waveform parameters. The air discharge waveform is a function of many parameters such as the ESD gun physical structure, the gun approaching speed, angle and path, the test environment temperature, humidity. All these parameters vary the arch length and ESD zap location of the device under test.


Our Current Development:

ES614 Series ESD Simulator Air Discharge Approaching Speed Controller is a digital controlled linear guide way system developed to control the ESD simulator approaching speed and travel path for the air discharge tests and calibration. This instrument can greatly improve the air discharge test consistency in terms of the approaching speed and travel path. It also has a temperature and humidity sensor to record the environment parameters.

A short video our Alpha version of the approaching speed controlled ESD air discharge test for touch panel module is shown in the video below.


What is coming along :

We are adding panel display and remote LabVIEW based software so the air discharge test can be fully automated for best consistency.  Because air discharge are influenced by barometric pressure, humidity,  and temperature. Those factors should be documented for best consistency. Those parameters will be monitored and automatically reported in the final system design.



  • ESD Simulator Air Discharge Approaching Speed Control
  • Automated ESD Simulator Air Discharge with Remote Control
  • ESD Simulator Air Discharge Waveform Calibration


Please feel free to contact us!


Wei (Wayne) Huang
CEO and Chief Design Engineer

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TS001 Introduction of Transmission Line Pulse (TLP) Testing for ESD Analysis -Device Level

This slides introduce the basic about Electrostatic Discharge (ESD), How ESD tests have been done, What is TLP testing, and FAQs.

ESDEMC_TS001_Introduction of TLP for ESD Analysis – Device Level

ESDEMC_TS001_Introduction of TLP for ESD Analysis – Device Level_CN

By Wei Huang, Jerry Tichenor, David Pommerenke

Introduction of Transmission Line Pulse (TLP) Testing for ESD Analysis – Device Level from Wei Huang

用于ESD分析的传输线脉冲测试 (Transmission Line Pulse – TLP Measurement) 元件级 from Wei Huang
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PB2014.08 An Ethernet Cable Discharge Event (CDE) Test and Measurement System

Download PDF –  An Ethernet Cable Discharge Event (CDE) Test and Measurement System

Abstract — A Cable Discharge Event (CDE) is an electrostatic discharge between a cable and a connector. CDEs occur on unshielded Ethernet based communication interfaces and inject currents into the pins directly [1-3]. The charging processes are in general understood; however, the discharge processes are complicated due to the number of pins involved and their connections to a system. Based on an understanding of the factors which determine the severity of a CDE, this article describes how to setup a variety of repeatable CDE tests and how to analyze the measurement results.

Keywords — Cable Discharge Event (CDE) Test; Cable ESD;



Both occurrence rate and severity of a CDE needs to be considered when determining the importance of dedicated CDE tests to ensure a reliable system. The occurrence rate of a CDE depends on the type of connector used and the environment the system is used. While a USB connector on a laptop will receive many more ESD events than a LAN connector, the LAN connector still poses a larger risk to the system as it is usually not shielded and often used in applications that require high reliability such as back bone internet routers. In contrast to a USB connector, a LAN connector can have a spark from the connector to a pin during a CDE. In the case of USB connectors the connector shells will mate first. Provided that the shells are connected to the shield and to the system ground, most of the discharge current will flow on the connector shells.

For the LAN CDE case a good understanding of the dominating processes provides a mean for developing and validating models. These models will allow computer simulation, and laboratory test setup formulation for reproducing real CDEs. This is crucial for IC and system level engineers to study and optimize the immunity of Ethernet based communications interface designs.

It is well known that triboelectric charging is the culprit that generates the charge on a cable [1],[2]. This fact is especially important in Ethernet communication systems due to the long lengths of UPT cable that must be pulled through conduit, which may result into large charges. A model for describing the interaction of one twisted pair in a UTP (Unshielded Twisted Pair) cable is presented in [2] using a three body model analyzed from an electrostatic point of view. In [3] a system for discharging a cable using a relay on a test bed is presented, and experimental results are shown. In regards to the measurement analysis side of Ethernet CDE, there are few publications discussing the phenomena. Some ESD test setup have been developed to repeat ESD current transfer through Ethernet magnetic effects in [4] and [5].

The focus of this article is to present a CDE testing system that will allow for real world test conditions to be reproduced in the laboratory, thereby providing design engineers a quick and reliable method for testing new hardware designs. The test system will allow for different types of copper based Ethernet cables, and twisted pair termination strategies. Further, full control of the charge and discharge sequence of each cable line allows for all possible cases to be explored.


Prior to discussing the CDE test system, a few important parameters of copper based Ethernet cable CDE, especially UTP must be reviewed.

A. Parameters of the charged Ethernet cable affecting CDE

Several important parameters must be considered in UTP cables. The first parameter is the charging processes in UTP cables. In particular, the wires can be charged due to charges on the outside of the jacket, due to migration of charges through the jacket and insulation to the wires, or due to direct contact of the wires with a charged object. The voltage magnitude can be as high as 2 kV. In most cases all wires will be charged to the same voltage. If the spatial arrangement of the cables is changed, the capacitance between the charged wires and ground will also change, which can further increase the charge voltage.

Another important parameter to consider is that there are shielded and unshielded cables for Ethernet. These cable types are illustrated in Fig. 1. They all maintain 100 Ohm differential impedance for each twisted pair, but the unshielded cable will have relatively large common mode impedance (100-300 Ohm) versus the shielded cables because their current path is physically far from the ground as compared to the shielded wires. This common mode impedance plays a critical role in the magnitude and to a lesser extend in the shape of the CDE discharge current waveform.

B. The termination of the Ethernet device

Load terminations also play an important role in the characterization of a CDE. Many different types of termination schemes exist, however, the most commonly used is the Bob Smith Termination [5]. This termination uses a 75 W resistor for a common mode impedance match at each signal pair, and they all connect via a high voltage capacitor to chassis ground as shown in Fig 2. The isolation between the Ethernet connector/chassis and internal PHY circuit is established through a transformer and some designs incorporate common mode chokes to further reduce common mode current motivated EMI concerns. Further variations of the Bob Smith circuit can be found in power over Ethernet applications, and strongly cost reduced designs.

One pin will make the first contact and any other pin will contact next. The initial contact leads to a charge redistribution, a partial discharge of the total charge on the cable, and it can charge the capacitor used in the Bob Smith circuit. Depending on the contact sequence, various common mode and differential mode termination plus the PHY IC circuit determine the load of the discharge current path and therefore are the important factors that determine the CDE current waveform.

C. The ESD events during CDE

The Ethernet cable connection includes several metal to metal contacts, which can lead to multiple ESD events during connection. For the case of plugging a shielded Ethernet cable into a shielded Ethernet connector, the first ESD event is the discharge between the shielding of the cable to the shielding of Ethernet connector as this is the first contact point. Normally this ESD is not likely to cause any failures if the DUT is shielded. For the case of an unshielded cable or an unshielded Ethernet connector the current must flow in the wires of the UTP.

When an Ethernet cable is plugged into a connector, many possible contact sequences can occur. Theoretically there could be eight separate ESD events, one for each pin. However, each contact will minimize the voltage between the other pins and the connector. This is caused by the large mutual capacitance between the wires, and by charging the Bob Smith Termination.

To illustrate the charging of the capacitor in the Bob Smith circuit, a 100 m long shielded cable was charged to 100 V between the shield and its wires and inserted into an Ethernet device. A result from this experiment is shown in Fig 3. Because the capacitance between the wires and the shield is much larger than the 1000 pF capacitor, the voltage reaches over 90 V immediately after first contact, thereby lowering the voltage difference between other connecting pins. For the next seven contact events the voltage difference across the contacts is drastically reduced.

The voltage waveform shown in Fig 3 gradually diminishes due to the 100 MW resistive voltage probe used in the measurement. Without this drain path the voltage on the cable will remain high for a very long time after the connection is made. If the other end of this cable is plugged into an Ethernet device another cable discharge event may occur.

Because the differential pairs of the cable have a welldefined 100 W discharge impedance, after the first wire has made contact and the high voltage capacitor has a low impedance path to ground, such that the second wire also experiences the discharge as it is making contact, resulting in a differential ESD event. This differential ESD current can easily transfer through the magnetics to the isolated PHY circuit, which is hazardous for the PHY chip.


A good Ethernet CDE test setup should be able to control as many of the parameters related to the cable discharge event as possible, and provide a repeatable test. To do this the setup must have these three main components; a Controller, a Charge Module, and a Failure Test Monitor.

The Controller must have the capability to control cable charge voltage and polarity, charge and discharge different types of Ethernet cable arrangements, and separately control the charging, floating, grounding, or discharge of each wire. In addition, the test system should maintain the electrical characteristic of the entire discharge current path as close to real world CDE cases as possible. In particular, it should control common and differential mode impedance of each pair, and the contact sequence delay time between each discharge to the same order of magnitude of a real cable as it is plugged into a device.

The Charge Module represents the Ethernet cable used as the discharge source for the CDE event. This consists of different lengths of various CAT5 cable types. For research purposes, different types of cables and how they are arranged must be studied. For industry testing purposes, a good charge module will provide a worst case, real world CDE source.

ill provide a worst case, real world CDE source. The Failure Test Monitor provides a means for verifying the Ethernet performance. It will check if a failure has occurred, or simply if a degradation in communication speed has occurred. It is important this is automated due to the vast array of tests that can be performed to check all discharge sequences. A general block diagram of the CDE test system is shown in Fig 4.

A. CDE Test Controller

The main CDE test controller consists of high voltage supplies (dual polarity), relays to separately control the connection of each Ethernet cable wire, including whether it is charging, floating, or grounded. The relays are bounce free and provide a clean discharge for each wire. The transmission lines on the board maintain the controlled 100 W differential pair structure of the Ethernet cable, and current probes are embedded into each wire to monitor CDE discharge current. The system also has remote control capability integrated into the upper level system as a part of the automatic test equipment (ATE). A simplified diagram of the main CDE controller is shown in Fig 5.

A common test procedure may consist of the following four steps, as illustrated by the block diagram in Fig 6.

1. Charge cable status control

The controller separately controls the voltage (level and polarity) for each wire in the cable bundle. This includes the status of each wire indicating if it is charged, floating, grounded, or a through path.

2. Pre-discharge preparation

The controller will disconnect the charging path from each wire in the Ethernet cable bundle and disconnect the DUT discharge path between the DUT connector and ground. This will leave all wires floating before the discharge step.

3. Control wire discharge while monitoring ESD Current

The controller will close the relays allowing the wires coming from the charge line to discharge into the DUT or termination load. The sequence of the relay closure and the delay between relay closures can be set by the user.

4. Preparation after a discharge and check DUT status

The controller will open all cable discharge relays such that the cable can be charged again. To charge the wires the high voltage charging relays are closed. In additional all remaining charges on the DUT need to be removed. This is achieved by closing the DUT discharge relays.

The controller will open all cable discharge relays, then close all high voltage charging relays and DUT connector discharge relays to prepare for next CDE test.

B. Charge Module

In real world Ethernet cable installations there are many different possibilities in regard to cable type and arrangements, leading to unlimited test scenarios. Some common real world arrangements are:

A. Cable hanging on the celling (relatively far from ground)

B. Cable on the floor (very close to the ground)

C. A spool of new cable

D. Cable pulled through conduit (very close to the ground)

C. Failure Test Module

Besides the setup for CDE test control, it is also important to test for normal Ethernet performance and functionality. It is important to understand the effects of applied CDE on the DUT, and as in the block diagram of Fig 4, an Ethernet traffic test system should not only monitor the status of DUT during CDE test, but also check the performance of the CDE applied ported after each test level.

D. Calibration of the Ethernet CDE Test System

A CDE Tester (Model ES631-LAN) with two different types of Ethernet Charge Modules (shielded and unshielded) was built. The analysis of real discharge waveforms is difficult. For that reason a proper calibration method with well-defined test loads is important to verify the functionality, to understand the current paths and the output parameters of the CDE test setup. A set of calibration loads including short, open, and 100 W differential load were built using 10 cm CAT5E UTP cables, and are shown in Fig 8.

The EIA 568B cable standard was used for all Ethernet wiring, Fig 9.

In the measurement setup the oscilloscope was set to capture the waveforms: Channel 1-voltage on line 5, Channel 2-current on line 5, Channel 3-voltage on line 4, and Channel 4-current on line 4. The voltage probes were 1010:1 (5 kW/50 W resistor bridge = 101:1, plus 20 dB attenuator). And the current probes were 20:1 (5 V/A plus 40 dB attenuator). The CDE Controller in all tests was set to 500 V, and depending on the test configuration the Charge Module and DUT may have been grounded.

Setup 1 consisted of a short connected to CDE Controller output, one differential pair with one side grounded and preconnected to the load, and a 100 meter Charge Module using S/UTP cable with the chassis not grounded. The setup and measurement waveforms are shown in Fig 10. From the simplified circuit, after the relay is closed in line 5, we expect a large current flowing from line 5 to line 4 over the differential 100 W transmission line structure and the peak current should be 5 A (500 V/100 W). From the waveforms it can be confirmed that the current waveform starts with 5 A peak. Then the waveform shows significant cable loss as the waveforms rapidly decay. After the current reaches the cable ends, reflections occur due to mismatches and several reflections happen until the total signal approaches zero. The voltage is a RC discharge waveform through the voltage measurement path.

Setup 2 is similar to setup 1 except the charge module chassis is connected to ground. The setup and measurement waveforms are shown in Fig 11. As can be seen, the current waveforms are the same as the first setup, but the voltage waveform RC time constant is much larger due to the grounding of the Charge Module chassis.

Setup 3 consisted of an open load connected to the CDE Controller output, one differential pair with one side grounded and pre-connected to the load, and a 100 meter Charge Module using S/UTP cable and chassis grounded. The setup and measurement waveforms are shown in Fig 12. There is little displacement current as the load is an open, and the voltage on line 5 is 494 V peak, which is very close to the charge voltage.

Setup 4 consisted of a 100 W load (with center tap between two 50 W resistors grounded) connected to the CDE Controller output, one differential pair with one side grounded and preconnected to the load, and a 100 meter Charge Module using S/UTP cable and chassis grounded. The setup and measurement waveforms are shown in Fig 13. With the 100 W load in place the current waveform magnitude drops to half of that measured with the short as in setups 1 and 2, and there are no reflections.

Except for the shape and magnitude of the measured calibration waveforms, the time delay of the measurement is also important to understand, in particular, which part of the waveform is due to the 100 W transmission line extension, and which part is due to the DUT. The waveforms shown in Fig 14 are with the CDE Controller connected to a CAT5E UTP cable only. The current waveform shows the 100 W transmission line extension first, then the open end. The real measurement of the DUT starts at the time where the open is shown.

E. Test of the CDE System on Ethernet Systems

Two 10/100Mbps Ethernet DUTs were tested with the CDE test system as shown in Fig 15. The test parameters are: CDE source voltage of 1 kV, a 100 meter Charge Module using S/UTP cable, and oscilloscope channels are scaled to 1 A/div. The first pin discharge waveform is captured and compared between unit A and unit B. Unit B has a much smaller current peak and higher current duration. This is mainly because the common mode impedance of unit B is much smaller than unit A.

Most systems using the Bob Smith Termination are almost fully charged after the initial discharge, so the current magnitude of the 2 nd – 8 th discharges are too small compared to the first one. This is not discussed here.

A Power over Ethernet (POE) system, having more complex termination was also tested. The measurement waveforms are shown in Fig 16. When the first pin contact DUT, first discharge current is generated in common mode through this pin. Then when the other wire in the same twisted pair contacts DUT, another discharge current is generated in differential mode through this pair. Both discharge signals could be transferred from termination to PHY circuit leading to damage in the Ethernet system.


In this article, several important physics for CDEs have been discussed, a general CDE test and measurement solution developed, and some test results with well-defined structures and a few real world Ethernet systems are presented and discussed.

The next steps for CDE related test and measurement would be modeling the overall test system with different terminations, and running more tests with Ethernet systems to understand the design principle for CDE.


We would like to thank the EMC Laboratory, Missouri University of Science and Technology for the partnership of CDE related study and research and Cisco for the partnership in CDE related tests and measurements.

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TN006 Advanced Frequency Compensation Method for VF-TLP Measurement (up to 10 GHz)

TN006_P09 ESDEMC Frequency Compensation of VF-TLP Voltage Measurement Flow Diagram

 TN006 Advanced Frequency Compensation Method for VF-TLP Measurement (PDF)

1. Objective

The objective of this article is to demonstrate a frequency compensation technique for measuring the current and voltage of a device under test in a Very Fast Transmission Line Pulser (VF-TLP) test environment. The current measurement utilizes Non-Overlapping Time Domain Reflectometry, which is useful for On-Wafer testing because the measurement can be made with low profile small pitch probes, such as the Picoprobe Model 10. Further, to increase the bandwidth of the current measurement over common techniques, such as current transformers with 1GHz bandwidth, the method utilizes a resistive Pick-Off. The Pick-Off can be finely tuned to have as little insertion loss as possible, thereby enhancing the bandwidth. Although this method can also yield a DUT voltage measurement, the result suffers from numerical errors for low ohmic devices. A separate, direct measurement is presented that will demonstrate an extremely accurate voltage measurement that also utilizes frequency compensation.


2. Measurement Setup

Very Fast Transmission Line Pulse or VF-TLP testing is a difficult measurement to perform well. This is a high bandwidth measurement and all connections must be completed as well as possible to maintain the characteristic impedance of the system (typically 50 ). This translates into ensuring that any probe connections are well matched, and any connectors/adaptors are of the highest possible quality. Further, due to how Non-Overlapping TDR measurements are implemented, there are great benefits from using low loss cables, which are very expensive.

The overall measurement setup is depicted in Figure 1, where it can be seen to the far right hand of the figure that the system can accommodate a variety of DUT connection methods. In particular, the pulse is applied to the DUT by the Pulse In connection, and a direct voltage measurement is taken at the Vm connection. A true Kelvin measurement can be done using two probes, providing a good On-Wafer measurement solution. Also seen in the figure are an ES 621 Transmission Line Pulser, a Pick-Off tee, a leakage control module (A621-LTKSEM), a Source Meter Unit (SMU), and an Oscilloscope. Encircled numbers denote where frequency domain measurement points are located for the Non-Overlapping TDR current measurement. Under normal pulsing conditions, the leakage control module connections are in the Normally Closed (NC) positions. And during leakage current measurement conditions, the module is in the Normally Open (NO) positions. The NO position connects the DUT to the SMU, and disconnects the voltage measurement resistor Rv. A photograph of the setup is shown in Figure 2.

Figure 1 ESDEMC ES62X Series VF-TLP Measurement Setup
Figure 1 ESDEMC VF-TLP Measurement Setup


Figure 2 ESDEMC ES62X Series VF-TLP Delay Line Cable Arrangement
Figure 2 ESDEMC VF-TLP Delay Line Cable Arrangement

2.1 Current Measurement

A simplified figure highlighting the Non-Overlapping TDR connections of the measurement is shown in Figure 3. From the left, a TLP connects to Port 1 of the cabling layout. The V+ indicates the positive outgoing wave from the TLP. Next in line is the resistive Pick-Off, where the incident or (V+M) measurement is taken as V+ propagates toward the DUT. After reaching the DUT, a reflected wave (V-L) propagates back toward the Pick Off to be measured as V-M. The cable between the Pick-Off and the DUT is labeled the Delay Line. This is because the length of this cable must be long enough to delay the reflected wave from reaching the Pick-Off before the incident wave has fully passed. This can be guaranteed if the Delay Line is at least two times longer than the pulse width. The Delay Line length and the need for low loss cables typically results in pulse widths no longer than 10 ns for this measurement method.

ESDEMC ES62X Series Non-Overlapping TDR connections
Figure 3 ESDEMC VF-TLP Non-Overlapping TDR connections

The encircled numbers (○1, ○2, and ○3) in Figure 3 represent where the frequency compensation measurements must be made. In particular, S21, S31, and S32 must be measured and saved for future use for each measurement setup. If any cables or attenuators, or the Pick-Off are changed, then the S-parameters must be re-measured. The leakage control module must be included in the measurement, and put in the normally closed state. The magnitude of the three S-parameters for a typical setup are shown in Figure 4. It would be desirable for the insertion loss of the cabling and Pick-Off to be 0 dB across all frequencies, allowing the full TLP output pulse to be applied to the DUT. However, real low loss cables can have a few dB of attenuation at 10’s of GHz. For the measured setup the increased loss is most likely from the Pick-Off, and the SMA connectors between the ports for connecting the leakage relay and the DUT. Another item to note is that the S21 measurement is relatively flat.

Magnitude of S-parameter measurements for the Non-Overlapping TDR setup
Figure 4 Magnitude of S-parameter measurements for the Non-Overlapping TDR setup

The other two S-parameter measurements are very similar, and this is to be expected because other than S32 having the longer Delay Line in the path, the connections are identical. The ripple in the magnitude measurements are due to reflections in the connections. The ripple is approximately 1 dB to 1 GHz. How these measured S-parameters are used will be presented in Section 3.

2.2 Voltage Measurement

As stated earlier, the Non-Overlapping TDR measurement does yield a DUT voltage measurement. However, the measurement suffers from numerical errors for low ohmic devices. This is due to the Transmission Line theory math used in the processing of the captured data, and will be explained in greater detail in Section 3. A good measurement of the DUT voltage can be achieved by a separate, direct measurement, and a simplified connection diagram for this is shown in Figure 5.
This measurement is typically very accurate with just using the probe ratio and attenuator value to calculate the DUT voltage. However, with VF-TLP type measurements having higher bandwidth restrictions, a more accurate measurement can be achieved by using frequency compensation. Like Non-Overlapping TDR, the cable loss, attenuator value and connection quality can all be represented and compensated for by capturing the S21 of the measurement system. The magnitude of the S21 measurement taken for the system is shown in Figure 6.
VF-TLP Direct Voltage Measurement Setup

Figure 5. VF-TLP Direct Voltage Measurement Setup


Magnitude of S-parameter measurements for the Voltage Measurement
Figure 6 Magnitude of S-parameter measurements for the Voltage Measurement

For reasons that will be explained in the next section, the probe connection for the measurement in Figure 6 is the PCB, or upper right hand sub-figure, in Figure 1. The measurement is relatively flat to 1 GHz.


3. Frequency Compensation

Processing of the captured data requires loading of the S-parameter data into the TLP measurement control code. This is easily accomplished using the Touchstone file format that all network analyzers support. The core of the processing in this method is done in the frequency domain, which means that the measured time waveforms must be transformed to the frequency domain. Since it is nearly impossible to ensure that the time record length is identical to the measured S-parameters, interpolation must be done to obtain equal length data sets.

A flow diagram for the Non-Overlapping TDR measurement for IDUT is shown in Figure 7. At the upper left hand of the figure is shown a captured Non-Overlapping TDR waveform plot. In the plot, the left hand pulse is the Pick-Off measured incident pulse (V+M), and the right hand pulse is the Pick-Off measured reflected pulse (V-M). The next step in processing gets the data prepared for transforming to the frequency domain. In this step the incident and reflected pulses are separated, Windowed, Filtered, and Interpolated. In particular, the pulses are separated at the Cut Point, which is arbitrary, and merely needs to be in between the two pulses. If the Delay Line is altered or the pulse width changed, the Cut Point should be verified to be in an adequate position. Windowing is required to force to zero the beginning and ending of the time record to ensure that the captured data appear periodic in regard to the FFT. If this is not done, the FFT result will suffer from spectral leakage. Next, if desired, the data can be filtered. In the results presented herein there was no filtering of the data. Finally, the time and frequency domain data are interpolated.

The next step in the flow diagram is to transform the time data by Fast Fourier Transform (FFT). There is other mathematical manipulation not shown herein, but the math is illustrated in the next step of the flow diagram. This manipulation translates the two Pick-Off measurements (V+M and V-M) to the Load/DUT. In particular, the measured incident wave (V+M) must be translated back to the TLP (divide by S31), and then translated to the Load (multiplication by S21), yielding V+L. Since the measured reflected wave (V-M) only traverses between the Load and the measurement port, it only requires translation back to the load by dividing by S32, yielding V-L.

ESDEMC VF-TLP Non-Overlapping TDR Processing Flow Diagram
Figure 7. ESDEMC VF-TLP Non-Overlapping TDR Processing Flow Diagram

Time domain representations of the incident and reflected waves at the Load are then obtained by Inverse-FFT (IFFT). The two waveforms are shown in the plot to the left of the IFFT flow diagram step, and a zoomed in version is shown in Figure 8. Notice that there is a time difference between these two pulses. The S-parameter measurements should have taken care of this time difference, and given the exact same connections they would have. However, since SMA adaptors must be used to connect to the various different ports, all the measurements could not be placed at the calibration plane. Fortunately, the difference is short (typically pico-seconds) which can be accounted for by subtracting the time from the reflected pulse.

V+L and V-L waveforms (Zoom).
Figure 8. V+L and V-L Waveforms (Zoom).

Finally, the Load current or IDUT can then be calculated as shown in the last step of the flow diagram. Notice for low ohmic devices the resulting pulses are comparable in magnitude and in opposite directions. This combination is good for determining the current as the result is the addition of two numbers of comparable size. This is then divided by the characteristic impedance to obtain the current. As stated previously, this is not a good scenario for measuring the DUT voltage. Considering the same pulses, of comparable magnitude and opposite directions, the result for the voltage is the subtraction of two similar numbers, and potential for greater error. This method works great for voltage measurements of high ohmic devices, but for similar reasons the current measurement would suffer.

Processing for the direct voltage measurement is very similar to the current measurement, and the flow diagram is shown in Figure 9. The data is Windowed, Filtered (if desired), and Interpolated before being transformed by FFT. The frequency domain manipulation merely translates the measurement recorded at the oscilloscope back to the Load by dividing by S21 of the measurement path. Shown in the upper left, and bottom left hand of Figure 9 are the raw and resulting voltage at the DUT waveforms, respectively. Notice how the compensation removed the excessive ringing on the voltage measurement introduced by the probe.

ESDEMC VF-TLP Voltage Measurement Flow Diagram
Figure 9. ESDEMC VF-TLP Voltage Measurement Flow Diagram

4. Measurement

The goal of the method described above is to obtain the best possible, high bandwidth measurement possible, and the method utilizes Frequency compensation to try and achieve this goal. To demonstrate the ability of the technique a comparison of two different voltage measurements, recorded simultaneously, was performed. To do this a 1  resistor was mounted onto a PCB along with a measuring resistor (Rv), as demonstrated in the upper right hand of Figure 1. There is one exception to the connections of Figure 1 in that the addition of a Thru port that can be fed directly to the oscilloscope has been added. A schematic and photograph of the PCB are shown in Figure 10. The DUT is connected from Pulse In to ground, making the effective DUT a parallel combination of the 1  resistor with the oscilloscope input impedance (1 Ohm||50 Ohm). The Thru side measurement is directly connected to the oscilloscope channel 3 with a 30 dB / 18 GHz attenuator. The Thru measurement is compensated for by value of the attenuator only.

Photo of VF-TLP DUT test PCB
Figure 10. Photo of VF-TLP DUT test PCB

To truly test and understand the ability of the system, a brief introduction into the pulse shape characteristics that will be used to pulse the DUT are presented. First, the ES 621 TLP can produce a very clean and fast rising pulse, as depicted in Figure 11. The measurement was performed with a Tektronix MSO 72304DX (23 GHz/100 GSa/s) oscilloscope, a short 18 GHz cable and attenuator. As can be seen in the lower left hand of the figure, the average rise time measurement is approximately 60 ps, and the average pulse width measurement is approximately 1.04 ns. Further, the overshoot is small and settles quickly.

ES 621 Vf-TLP output, 60 ps rise time, 1ns pulse, with 23 GHz Oscilloscope
Figure 11. ES 621 Vf-TLP output, 60 ps rise time, 1ns pulse, with 23 GHz Oscilloscope, Measured in ESDEMC Headquarter Rolla, MO, USA 2014/08/28


Shown in Figure 12 are results for a current measurement. The Black trace is the raw result. By raw, it is meant that the final measured current value is determined by aligning the incident and reflected waveforms in time, scaling them by the Pick-Off probe value and attenuator in the measurement path, and then using the equation at the bottom of the flow diagram in Figure 7. The Red trace is the same measurement, but it is the result after the frequency compensation method described above. As can be seen the two measurements are in good agreement in regard to general shape and amplitude. But, the frequency compensated measurement removes artifacts introduced by the measurement probe, such as the high frequency ripple at the beginning of the current pulse.

ESDEMC VF-TLP Raw and Frequency Compensated Current Measurement
Figure 12 ESDEMC VF-TLP Raw and Frequency Compensated Current Measurement

Shown in Figure 13 are results for a voltage measurement. The Black trace is the raw direct voltage measurement, scaled by the probe factor and attenuator value only. The Red trace is the same measurement, but it is the result after the frequency compensation method described above. The Blue trace is VThru and is the result of the direct voltage measurement and a 30 dB / 18 GHz attenuator as the only compensation. As can be seen, the Red and Blue traces match very well, supporting the frequency compensation technique does an extremely good job in obtaining the voltage measurement.

Raw, Frequency Compensated, and Thru Voltage Measurement
Figure 13. Raw, Frequency Compensated, and Thru Voltage Measurement

5. Conclusions

The objective of this article was to demonstrate a frequency compensation technique for measuring the current and voltage of a device under test in a Very Fast Transmission Line Pulser (VF-TLP) test environment. It was shown that by incorporating the S-parameter measurements of the test setup into the processing routine that an extremely good voltage measurement could be obtained. In particular, a high bandwidth direct voltage measurement was used to verify the VF-TLP voltage measurement. Similarly, the compensation method was used to obtain the device current from the Non-Overlapping TDR measurement.

ESDEMC 60ps rise-time 1ns Pulse VF-TLP Measurement
ESDEMC VF-TLP Measurement of 60ps rise-time 1ns VF-TLP Pulse

Appendix: Measurement Equipments

Tektronix MSO 72304DX, 23 GHz/100 GSa/s, Oscilloscope
ESDEMC ES621 Transmission Line Pulser System
ESDEMC A621-LTKSEM Leakage Control Module
Suhner Sucoflex 100 high performance microwave cable
Micro-Coax UTiFlex Ultra low loss microwave cable
Mini-Circuits SMSM Cable
Gore-Tex UltraLow Loss Coax Cable

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PB2013.08 Effect of Cooling on the Probe System Sensitivity for Low Signal Strength RFI Problems

Download PDF – Effect of Cooling on the Probe System Sensitivity for Low Signal Strength RFI Problems

Abstract—Only highly sensitive probe systems can detect the weak field strengths that cause radio-frequency-interference (RFI) problems typically found within cell phones. The sensitivity of the probe systems depends on the probe factor and on the noise floor. The effect of cooling by liquid nitrogen on the received signal strength and the noise floor of three resonant probe systems has been investigated. They operate at the GSM, GPS, and WiFi frequency bands. Cooling increases the Q-factor of these resonant probes, increases the received signal, and lowers the noise floor. The sensitivity of the system, defined as the signal strength at which the Signal-to-Noise Ratio is equal to 0 dB improves by 3-6 dB.
Keywords— Quality factor, radio-frequency interference (RFI), resonant magnetic field probe, signal-to-noise ratio.


High-frequency harmonics generated from the digital ICs and switched power supplies may couple into the antennas which are integrated into mobile systems such as cell phones. The noise of the harmonics is added to the natural noise floor of the receiver and overwhelms weak signals which should be received by the receiver [1], [2]. Near-field probes [3], [4] and scanning technique are effective tools to investigate noise field distribution of circuits at high frequency and to locate the source of the EMI problems at circuit and chip level [5], [6].

Broadband probes are useful tools for initially locating strong noise sources. Magnetic near-field probes for high frequency band up to tens of GHz have been designed by suppressing the inherent resonances of a circular loop [7], and by minimizing the cross-sensitivity of electric near-field [8]. However, when the interfering electromagnetic fields are weak, it is difficult for broadband probes to measure signals of low signal-to-noise ratio (SNR). Probes with larger loop size can improve the SNR but degrade the spatial resolution. Since the noise source of interest is usually in the narrow bands, narrowband resonant probes can detect lower SNR signals than their broadband counterparts because of their higher sensitivity [9], [10]. In the applications of nuclear magnetic resonance (NMR), the SNR is further improved by lowering the coil temperature with liquid helium, since the noise is dominated by the thermal noise of the receiver coil in a welldesigned NMR spectrometer [11], [12].

In the following paper, three resonant magnetic field probes are cooled with liquid nitrogen to investigate the effect of cooling on the probe system sensitivity, where only the probes are cooled. The probes operate at the GSM, GPS, and WiFi frequency bands. The sensitivity is defined as the signal at which the SNR reaches 0 dB within a bandwidth of 1 Hz. The experiment and results are described in detail in the following sections.


The probe for investigating the effect of cooling is based on a differential-loop resonator shown in Fig. 1 and a Marchand balun based impedance transformer shown in Fig. 2. The theory, design and the dimension of the probe have been introduced in detail in [10]. The probe uses a four-layer FR4 printed circuit board. The initial design selected FR4 as substrate due to its low cost. The top and bottom layers in Fig. 1 are signal return planes and shielding planes minimizing unwanted field coupling. The LC resonator consists of a parallel-plate capacitor in parallel with an inductor formed by the probe loops. The resonant frequency of the probe is set by the geometry of the loops and the capacitors. The resonator is terminated with a Marchand balun based impedance transformer. The impedance transformer converts a high impedance Zl of 1800 Ω to a low impedance Z0 of 50 Ω. The high impedance is loading the resonator but allowing for a high Q-factor. The low impedance matches to the input impedance of measurement instruments such as the spectrum analyzer for maximal energy transfer. The transformer also converts differential signals to a single-ended signal, where the differential signals originate from the mirror-symmetrical design of the resonators on the second and third layers. Drawing of the fabricated resonant magnetic field probe at GPS frequency band are shown in Fig. 3. The assembled probe is about 6.5 cm long from the SMA connectors to the probe tip.


Fig. 4 shows the measurement setup for investigating the effect of cooling probes by liquid nitrogen. The tracking generator of the spectrum analyzer outputs a sweeping sinusoidal signal to drive the 50 Ω microstrip trace terminated by a matched load. The probes are placed 2 mm (H = 2 mm, in Fig. 4) above the trace. This height is in the same order of the height commonly used in the near field scanning. The signal is amplified by a three-stage amplifier and then received by the spectrum analyzer. The amplifiers are connected to the probe output port directly.

The first stage amplifier, Amp1, is a narrow band low noise amplifier (LNA). The second and third stage amplifiers, Amp2 and Amp3, are broadband. The noise figures and gains are listed in Table I at the frequency bands of interest. The system noise figure attributed to the noise contribution of each stage amplifier in the cascade follow the Friis equation:

where NF is the system noise figure, NFi (i=1, 2, 3) is the noise figures of three amplifiers, and Gi (i=1, 2, 3) is the gain of three amplifiers. All the probes are matched to 50 Ω at their center frequencies. Therefore, the noise figure of amplifiers measured in a 50 Ω system is a reasonable estimate for calculation in Eqn. 1. All the values in Eqn. 1 are linear scale, not in decibels. The system noise figures are 0.6 dB, 0.9 dB, and 1.1 dB for GSM, GPS, and WiFi frequency bands, respectively. The system noise figure is mainly influenced by the LNA, which has a low noise figure and relatively high gain.


The probe’s Q-factor was measured at room temperature and after cooling the probe in the liquid nitrogen. Although liquid nitrogen is not readily available in a real-word EMC laboratory at present, it is easy to buy a tank of liquid nitrogen. One might pour the liquid nitrogen onto the probe using a pipe during the real-world measurement. In the initial test, however, the probe is immersed in nitrogen. During the cooling, only the PCB of the probe has been placed into the liquid nitrogen for three minutes. The probe can stay cold for approximately two minutes after it is taken out from the liquid nitrogen. Then the probe was placed 2 mm (H = 2 mm) above the trace to measure signals, as shown in Fig. 4.

Cooling the probe increases the resonance frequencies (see Fig. 5). Take the GPS probe as an example. The resonance frequency increases by 46 MHz. The 3 dB bandwidth decreases by 29 MHz. The probe’s Q-factor, Q, is calculated by

where fc is the center frequency of the resonance, BW3dB is the 3 dB bandwidth. The Q-factor when the probe is at room temperature is 11.3. After the cooling, the Q-factor is 14.7. The Q-factor increases by 3.4. Similar results for GSM and WiFi probes are listed in Table II. Both a small increase in the resonance frequency, and lower losses result in an increase of the Q-factor.

From the power point of view, the power received by the spectrum analyzer increases by 1-3 dB at the center frequency. At the same time, the loss in the probe reduces. The thermal noise in the conductors for the signal traces and the ground planes decreases with decreasing temperature. The dissipated power becomes smaller, leading to the higher Q-factor.


The minimal detectable signal can be defined as the signal at which the SNR reaches 0 dB within a bandwidth of 1 Hz, when the noise power is equal to the noise power density. Real bandwidths are much larger. However, it is easy to denormalize to any requested bandwidth from 1 Hz. To calculate the noise equivalent signal, the system probe factor, SPF, and the noise power density, Pn,r, at the output of the probe system is needed. The noise power density is read directly from spectrum analyzer R&S FSV. The system probe factor is obtained from calibration.

During the calibration, the matched microstrip trace is driven by a source with a power level of Pd at the resonance frequency fc . The input impedance looking into the microstrip trace at the driving port is Rin = 50 Ω. The voltage at the driving port is

The microstrip trace generates a magnetic field, which is measured by the probes. The probes output a power, Pr , to the spectrum ananlyzer. Since the input impedance of the spectrum analyzer is RSA = 50 Ω, the receiving voltage measured by the spectrum analzyer is

Therefore, the voltage transfer coefficient TV from the driving voltage Vd to the receiving voltage Vr is

We simulated the same matched microstrip trace driven by one Volt, and the magnetic field above the trace normalized to one Volt is Href in unit of (A/m)/V. In the measurement, the trace is driven by a voltage of Vd. The magnetic field strength, Hm, measured by the probe would be

The system probe factor, SPF, is defined as:

Once the system probe factor SPF is known, the magnetic field strength Hm can be calculated if the receiving voltage Vr is given. When the SNR of the signal probe measures is 0 dB, the probe outputs a noise power of Pn,r within a bandwidth of 1 Hz. The voltage measured by the spectrum analyzer then is

The equivalent magnetic field strength of the noise is

The measured equivalent magnetic field strength is listed in Table III, comparing the cooled and the room temperature cases. The cooling has changed the property of probe materials slightly. This change is reversible.

The driving power Pd is not the same when the probe is cooled and at room temperature. This is caused by a small frequency dependence of the cables losses, as the resonance frequencies shift slightly. It is also caused by a small variation of the tracking generator’s output power at different frequencies. However, the small difference of driving power has no effect on the system probe factor, since the system probe factor is normalized with respect to the driving power, normalizing to 1 volt driving voltage at a 50Ω resistor.

If we take the GPS probe as an example, the received signal increases by 0.8 dB when the probe is cooled. At the same time, the noise power density decreases by 3.89 dB/Hz. The higher sensitivity and the lower noise power density result in an increased sensitivity of 4.69 dB. When this value is converted to the equivalent field strength, the minimal detectable equivalent field strength is 4.8 nA m /)/( Hz lower when the probe is cooled. Similar improvements are seen for the other probes when cooled.


The change of the system sensitivity by cooling near field probes for the GSM, GPS and WiFi bands using liquid nitrogen has been investigated. We observed increasing Qfactor, higher sensitivity, larger output power, and lower noise power density of the probe system at lowered temperature. The sensitivity of the system, defined as the signal strength at which the SNR is equal to 0 dB improved by 3-6 dB. The cooled probe system is helpful for detecting low electromagnetic fields coupled to RF antennas.


This material is based upon work supported by the National Science Foundation under Grant No. 0855878.

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PB2012.09 An application of utilizing the system-efficient-ESD-design (SEED) concept to analyze an LED protection circuit of a cell phone

Download PDF – An application of utilizing the system-efficient-ESD-design (SEED) concept to analyze an LED protection circuit of a cell phone

An application of utilizing the system-efficient-ESD-design (SEED) concept to analyze an LED protection circuit of a cell phone
Tianqi Li #1, Junji Maeshima *2, Hideki Shumiya*3, David J. Pommerenke#4, Takashi Yamada*5, Kenji Araki*6

# EMC laboratory, Missouri University of Science and Technology, 4000 Enterprise Dr., Rolla, MO, 65401, USA, tlx6f; 4
* Sony Corporation, Sony City, 1-7-1 Kounan Minato-ku, Tokyo, 108-0075, Japan
2 Junji.Maeshima; 3 Hideki.Shumiya; 5 TakashiB.Yamada;


Abstract—An LED circuit of a cell phone is analyzed using the System-Efficient-ESD-Design (SEED) methodology [1]. The method allows simulation of the ESD current path, and the interaction mechanisms between the clamp and the on-chip ESD protection circuit. The I-V curve and the non-linear behavior under high current pulses of every component including R, L, C, and ferrite beads are measured and modeled. By combining all of the component models, a complete circuit model is built for predicting the circuit behavior and damaging threshold at a given setting-voltage of a Transmission Line Pulser (TLP).


To build lower cost systems with better ESDresistant design at the system level it is important to understand the ESD current path, and how an IC’s on-chip protection circuit interacts with outside clamp circuits [2]. For example, if the on-chip ESD circuit of an IO pin could provide enough protection, then any external protection components could be omitted to reduce cost. A more complex case would be if the on-chip ESD circuit could not meet the protection requirements and the off-chip protection circuit has a relatively large resistance, more ESD current would still flow through the IO pin’s internal ESD circuit and finally damage the IO circuit itself. In this case, the external protection circuit should be replaced with a different clamp with smaller resistance in order to protect the IO pin.

For this reason, the interaction between components, especially between different protection circuits inside a system needs to be thoroughly analyzed, to achieve a more efficient protection scheme at the system level [1]. This is the purpose of the SEED approach. Circuit modelling and simulation is a convenient approach for such SEED analysis. However, typical SPICE models of components cannot be used in these simulations because they usually only contain information for normal operating conditions, without responses to several kV pulses such as those seen in ESD strikes. In this project a TLP is used to measure transient IV characteristics of each component, and highvoltage-SPICE models are built based on the tested data [3].

In this paper, an LED circuit in a cell phone is chosen to demonstrate the SEED analysis approach. The schematic of the LED circuit is shown in Fig.1. Under typical working conditions the VCC pin outputs DC current that flows through the LED and is sunk by the IO pin. The driver IC controls LED turn-on and turn-off by changing the status of the output MOSFET. All other components such as capacitors and Zener diodes are used for ESD protection and other filtering purposes. A potential discharge point is at the LED, which is located near the cell phone’s keyboard.

A. Modeling the LED

The I-V curve of the LED has been measured using a TLP resulting in the SPICE model shown in Fig. 2. The model includes two parts: the normalcondition SPICE model which is provided by the device manufacturer, as well as switches for matching the transient I-V curve. The factory model is OK for emulating the device I-V curve in the positive voltage region, but does not conform to the I-V curve in the negative-voltage region. For this reason, two switches are used to correct the simulated I-V curve.

During the measurements, it was also found that the LED will be damaged if the current reaches +15A or -10A.

B. Modeling the Zener Diode

The Zener diode was modeled in a similar way. In the model which is shown in Fig. 4, diode 11 defines the I-V characteristics of the Zener under a negative pulse. Diode 10 and the switch determine the positive I-V characteristics. Diode 9 is used as a unidirectional switch.

A linear capacitance of 25 pF is also included. Its value is taken from the datasheet and verified through measurements.

The simulation results of this model (Fig. 5) show good agreement to measurements as well.

C. Modeling the IO Pin of the LED Driver IC

A reflection-based TLP system is used for insystem measurement of the transient I-V curve of the IO pin, which is modeled without knowledge of its internal circuit. Similarly, the model is a combination of linear and non-linear components. The non-linear behavior was measured by the reflection-based TLP system, and its linear part can be obtained by tuning the model parameters to conform to the measured S11. In this way, a complete model of the IO pin could be developed, as shown in the Fig. 6. R20 and C2 are these linear components which were obtained from the Sparameter measurement.

Similar to the Zener diode model, diode 7 defines the non-linear behavior of the device when a negative pulse is applied at the IO pin. Diodes 6 and 8 define the non-linear behavior when a positive pulse is applied to the IO pin.

A damage threshold of 22A was determined using a 13.5 ns pulse from the TLP to the IO pin. The transient I-V curve of the model is shown in Fig. 7.

D. Modeling the Ferrite Beads

Because ferrites are non-linear components, their equivalent inductances drop as through currents increasing, due to saturation effect. A non-linear model of the ferrite bead, as shown in Fig. 8, was obtained by defining its equivalent inductance as a function of current.

In this model, the linear parts include R1, C2 and R9, which are extracted from the impedance plot provided by the datasheet. The non-linear part of the ferrite model, the inductance as a function of current, was measured by a TLP, and modeled with following equation:

Where I stands for the current through the nonlinear inductor, L0 is the inductance value for I=0. Thus, for FB1 L0 equals to 60nH. Lsat stands for the saturated inductance which, for FB1, equals 20nH. The plot of the equation is shown in Fig. 9.

The model is validated by comparing simulation and measurement results, as shown in Fig. 10.

E. Modeling the Inductors

The inductors used in the circuit are assumed to be linear components, and the transient simulation result, as shown in Fig. 11, validates this assumption.

F. Modeling the Capacitors

The capacitors used in this circuit have anNP0 type dielectric, therefore it was expected that the capacitance would not change as a function of the voltage across the capacitor. Such expectation was validated by measuring capacitance variation with respect to voltage by using a TLP. These TLP measurements confirm that the NP0-dielectric capacitor can be modeled as a simple linear capacitor.


A. The System Model

A system model was built by combining each of the experimentally obtained component models, as well as a TLP model as the source. The system model is validated through S-parameter measurements, as well as transient pulse measurements. The simulation result is compared to the measurement in Fig. 12. This comparison clearly shows that the injected 500 V TLP pulse is clamped to 9V by the protection circuit.

B. SEED Analysis

From Fig. 12, although it is known that the injected pulse is clamped to a low voltage, it is not known which one of the clamp circuit components is the primary clamping element. Additionally, it is not easy to predict what level of the injection pulse will damage the circuit, due to the fact that only a limited number of DUTs were available for real testing.

With the SEED method, the previous questions can easily be answered because it is possible to observe currents as they flow through various components in a simulation environment. In Fig. 13, it is clearly shown that more pulse current flows though the Zener diode during the first 10ns of an applied pulse before the protection diode inside the IO pin starts to conduct.

If the Zener diode is a more effective form of ESD protection we can ask if it is possible to remove FB1 before the IO pin to reduce cost. The simulation result in Fig. 14 shows that without the ferrite bead more current would flow through the IO pin, but not the Zener diode. Therefore, the ferrite bead has significant effect on the current that flows through the IO pin, and thus should not be removed.

SEED analysis may also tell us what the vulnerable parts in this circuit are, and how much margin left till the circuit would fail under a given injecting level, if the damage threshold of each component is known. For example, the simulation result in Fig. 15, shows that the current which flows though the LED is much larger than the current that flows through the IO pin. Therefore, for this circuit, the LED is more prone to damage than the driver IC, especially considering that LED device is usually placed at a location that has a greater chance to experience air discharge. It can be predicted that the LED will be damaged under 2000V TLP pulse because under this condition the LED’s through current reaches to 15A, which is its damaging threshold measured with 13.5ns TLP pulses.


In this study, the SEED strategy is applied to analyze the ESD performance of a cell phone’s LED circuit. High current SPICE behavioral models of each component in the circuit were developed and validated against measurements. By combining these models with a TLP source model, major pulse-current paths, protection mechanisms, system transient response, and weak points of the protection circuit are revealed. These parameters can then easily be analyzed through simulation, instead of performing a large number of destructive measurements.

For next step, the TLP model can be replaced with an ESD gun SPICE model, so that we can predict the circuit’s response under real ESD gun contact discharge measurements. This may help circuit designers predict the ESD performance of a circuit before it is put in to production. This SEED strategy also facilities PCB level ESD protection design during initial product development, rather than traditional trial-and-error process.


This material is based upon work supported by the National Science Foundation under Grant No. 0855878, and supported by Sony Corporation of Japan.

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TN005 TEM Cell Measurement of 2.4GHz Device Radiation

Overlaid spectra in GHz TEM Cell Measurment

Download TN005 TEM Cell Measurement of 2.4GHz Device Radiation (PDF)


1. Objective

The objective of this article is to demonstrate how the EM601 TEM Cell can be used for measuring the spectrum of 2.4 GHz devices such as Bluetooth and WiFi.

EM601-5.5 DC-5.5 GHz IC Stripline TEM Cell
EM601-5.5 DC-5.5 GHz IC Stripline TEM Cell

2. Measurement Setup

With the large field injection area of 50 x 50 mm, the EM601 series of TEM Cells is readily suitable for measuring the spectrum USB Bluetooth and WiFi devices such as those shown in Figure 1. The only additional equipment required is a computer, for powering and activating the device, and a spectrum analyzer. For the measurements presented herein, an Agilent E4448A spectrum analyzer was used.

USB Bluetooth and WiFi devices
Figure 1. USB Bluetooth and WiFi devices

In order to fit the Bluetooth device into the cell, it was removed from its plastic enclosure and a cable soldered to its connector terminals. The modified device is shown in Figure 2. A copper clad PCB was used as the TEM cell cover, and an aperture the size of a USB connector was milled for mounting USB devices, or exiting a cable. Figure 3 depicts the Bluetooth device inside the cell, and its’ USB cable exiting.

Modified Bluetooth device TEM Cell Measurement
Figure 2. Modified Bluetooth device for TEM Cell Measurement
Bluetooth device mounted inside TEM cell
Figure 3. Bluetooth device mounted inside TEM cell

Measuring the WiFi device was simpler in that it readily fit into the cell, and only required a USB cable to be connected externally as shown in Figure 4.


WiFi Device mounted inside TEM cell
Figure 4. WiFi Device mounted inside TEM cell


3. Measurements

The measurements were taken with an Agilent E4448A 3 Hz – 50 GHz spectrum analyzer with the settings: 3 MHz RBW, 50 MHz VBW, 10.375 ms sweep time, 10 dB attenuation, 3 Hz start frequency, and 6 GHz stop frequency. Port 1 of the TEM cell was connected to the spectrum analyzer, and Port 2 was terminated in 50 . The first measurement taken was of the TEM cell fully covered and no device inside. The empty cell spectrum measurement is shown in Figure 5.

Empty TEM Cell measurement (Dynamic Range Check)
Figure 5. Empty TEM Cell measurement (Dynamic Range Check)


The measured spectra of the Bluetooth, and WiFi devices are shown in Figure 6 and Figure 7. For each device measurement they were connected to a computer and fully functional. The Bluetooth device was put into search for a new device mode.

Spectra of Bluetooth device
Figure 6. Spectra of Bluetooth device


Spectra of Wifi device
Figure 7. Spectra of Wifi device

A graph with all plots overlaid is shown in Figure 8. As can be seen, the devices both operate in the 2.4 GHz band, and there is potential for interference when both devices are present and operating.

Overlaid spectra in GHz TEM Cell Measurment
Figure 7. Overlaid spectra in GHz TEM Cell Measurement

4. Conclusions:

The EM601-5.5 TEM Cell is well suited for measuring GHz device spectra. Further, the TEM cell cover can be customized to suit any device that can fit into the large 50 x 50 mm cell of the EM601.

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PB2012.06 Nonlinear Capacitors for ESD Protection

Download PDF – Nonlinear Capacitors for ESD Protection

Hongyu Li, Victor Khilkevich, Tianqi Li, David Pommerenke, Missouri University of Science and Technology, USA;
Seongtae Kwon, Wesley Hackenberger, TRS Technologies, Inc., USA

Abstract – In order to protect electronic products from Electrostatic Discharge (ESD) damage, multi-layer ceramic capacitors (MLCC) are often used to bypass the transient ESD energy. Most
dielectric materials used in MLCC are nonlinear, since the dielectric constant decreases with increasing voltage, reducing the capacitance value, thus degrading the ESD protection effect. Using a large initial capacitance value will ensure sufficient ESD protection; however, the shunt capacitors also limit the signal bandwidth of the ESD-protected data channel, thus setting a maximal capacitance value at data voltage levels. This paper investigates the nonlinearity of capacitors and suggests improved tradeoff between ESD protection and data bandwidth by using the Antiferroelectric (AFE) capacitors as ESD protection. The dielectric constant of AFE material increases with increasing voltage. The voltage dependence of X7R and AFE capacitors are measured
using static and nanosecond transient measurements. The ESD protection effectiveness with different material capacitors are compared by simulation. Due to very limited availability of suitable
AFE material samples only hand-made capacitors have tested without investigating the long term stability of the material.

Index Terms— ESD protection, AFE material, nonlinear capacitor

I. Introduction

ESD is one of the most important reliability problems in an electronic product. In order to provide ESD protection to electronic products, decoupling capacitors and series resistors can be used as shown in Fig. 1. The capacitors absorb the injected charge, and limit the maxi

I. Introduction

ESD is one of the most important reliability problems in an electronic product. In order to provide ESD protection to electronic products, decoupling capacitors and series resistors can be used as shown in Fig. 1. The capacitors absorb the injected charge, and limit the maximal

showed no noticeable voltage dependence. The measurement fixture is shown in Fig. 4. The two cylindrical devices are the PIO capacitors.

B. Static Measurement Results for X7R Capacitors

Static measurement results for X7R capacitors are shown in Fig. 5. All four capacitors (4.7nF, 50V) showed similar behaviour. The capacitance decreases from 4.7nF to about 1nF at 400V DC bias. We observed no damage to the capacitors at 400V.

C. Static Measurement Results for AFE Capacitor

The measurement result for an AFE capacitor is shown in Fig. 6. The capacitance is about 3nF without any DC bias, and increases with increasing DC bias voltage before the transformation from the AFE phase to the FE phase. For this AFE sample, the transformation occurs at about 325V, causing a peak in its capacitance value of about 8.5nF at 325V. In the FE phase the capacitor acts as normal capacitor, and the capacitance decreases with increasing DC bias voltage. The capacitance drops back to 3.5nF at 500V.

IV. Transient Measurement

The nonlinearity of the capacitors can be seen clearly from the static measurement results. However, ESD is a transient process of nanosecond time scale. ESD currents typically have rise time of less than 1ns. However, the voltage and current rise times at the capacitor is limited by the capacitance value and the source impedance (about 300 Ohm for an IEC 61000-4-2 ESD generator at lower frequencies and around 100 Ohm at higher frequencies). The voltage and current rise time at a capacitor with hundreds pF or a few nF is generally between a few and tens of nanoseconds. Transient measurements investigate if the capacitance can react with sufficient speed to provide ESD protection.

A. Transient Measurement Method

In the measurement setup illustrated in Fig. 7, C represents the capacitor under test. A pulse with duration of 70ns and a rise time of 150ps generated by the Transmission Line Pulser (TLP) is injected into the capacitor under test through a microstrip transmission line. A loop formed by a trace and vias is embedded underneath the transmission line. The mutual inductance between the transmission line and loop is used to measure the derivative of the current flowing on the transmission line. The current is obtained by integrating the measured derivative of the current. The voltage across the capacitor is measured with an oscilloscope.

The measurements capture the current derivative and the voltage across the capacitor. The post processing obtains the current and the voltage derivative. Low pass filtering is used for noise suppression and de-trending is used to remove the effect of scope’s imperfect DC-offset on the integration of the current derivative.

B. Transient Measurement Results for X7R Capacitors

If the TLP is set to 1200V charge voltage it takes about 60ns to charge the capacitor to 450V, as shown in Fig. 8. The stress was repeated many times to assure the phenomena are stable. Results from three repeats are plotted in Fig. 8. The change of the capacitance versus time for X7R capacitors is shown in Fig. 9. The results show that the X7R capacitors react fast enough to the transient signal

Fig. 10 compares transient and static measurement results for X7R capacitors and the trend of the nonlinearity matches well.

C. Transient Measurement Results for AFE Capacitor

If the TLP is charged to 2500V, it takes about 60ns to charge the AFE capacitor to 400V, as shown in Fig. 11. Results from three pulses are plotted in Fig. 11. Those indicate good repeatability. The peak and the dip at the beginning and the end of the pulse are due the parasitic inductance in the measurement setup and the large rate of current change at the beginning and end of the TLP pulse. The measurements indicate an inductance of about 5.5nH for the AFE capacitor test setup. Only 1.3nH had been measured for the X7R capacitor (fig. 8). Its 0603 package allowed a lower inductance placement within the test setup. The change of the capacitance versus time for AFE capacitor is shown in Fig. 12. The result shows that the AFE capacitor reacts fast enough to the transient signal, allowing this beneficial property being used for ESD protection. Fig. 13compares the transient and static measurement results for the AFE capacitor and the trend of the nonlinearity matches well. The deviation above 300V may be caused by the limitation of the transient measurement method. Due to its large capacitance it was barely possible to reach 400V at the highest TLP charge line setting of 2500V as shown in Fig. 11, causing uncertainties in the capacitance estimation as the capacitance values are derived just at the beginning of the falling voltage edge.

V. Comparision of the Capacitors for ESD Protection

The effectiveness of the capacitors for ESD protection can be compared by simulation. The nonlinear capacitor models are based on the static and transient measurements.

A. SPICE Model for Nonlinear Capacitor

The Analog Behavioral Model is used to model the nonlinear capacitor, as shown in Fig. 14. The capacitor is modeled by a controlled current source, GVALUE in PSpice, whose current is defined by equation (2). The time derivative of the voltage is modeled by using the discrete derivative of time (DDT) function in PSpice. A voltage dependent capacitance is specified by using a look-up table based on the measurement. This table contains voltage-capacitance pairs picked from points on the measured curve. The voltage input is nonlinearly mapped from the voltage values in the table to the capacitance values. Linear interpolation is used between table values [9].

B. ESD Current Source Model

ESD generator is modeled using the equivalent circuit as shown in Fig. 15. This circuit models the current and the impedance of the ESD generator. Initially, the capacitors are charged until the switch initiates the breakdown. C4, L2, R4 and R5 set the initial rise time, R1 and C2 represent the interaction between the body of the ESD generator and ground. The main discharge constant (330 Ohm, 150pF) is formed by R3+R4+R5 and by C1+C2+C4. R6 represents the ESD target and the current flowing through it is shown in Fig. 16. In this example, the ESD generator is charged to 2000V initially.

C. Capacitors to Compare

Sample1 from the X7R capacitors is selected to compare to the AFE capacitor. Fig. 17 shows the capacitance normalized to their value at 0V. In the simulation both X7R and AFE capacitors are de-normalized to 1nF at 0V; therefore, both protection circuits have the same frequency response, but different protection behavior.

D. ESD Protection Effectiveness Comparison

The simulation circuit is explained in Fig. 18. The device under protection is assumed as an IC. Diode ESD protection is commonly used in IC design. Here only these diodes are modeled and the IC’s internal structure is omitted. The destruction threshold of the commonly used human body model (HBM) test level is 2000V. The IC level HBM test and the IEC 61000-4-2 testing are both based on discharges from a human body, thus their total charge and pulse length are similar. The source impedance for the HBM testing is 1500Ω. Passing the HBM test ensures a robustness of the IC input for currents up to about 1.3A which we assume as the failure threshold of the simulation. Another consideration leads to the usage of a series resistor. Without such a resistor the internal ESD protection of the IC would compete with the PCB based protection, possibly leading to the IC protecting an external ESD protection. A series resistor allows for a sufficient voltage drop separating both protection methods electrically. A resistance of 200Ω is selected in this simulation. ESR and ESL represent the effective series resistance and inductance of the capacitor respectively, whose values are set to 100mΩ and 1nH. The circuit is excited by the ESD generator shown in Fig. 15. The ESD generator is charged to 2000V initially.

The critical current flowing into the IC is shown in Fig. 19. Using the X7R capacitor, it reaches 1.6A which is above the destruction threshold ensured by 2000V HBM testing of 1.3A. In contrast the increasing capacitance of the AFE capacitor limits the peak current below 0.9A.

In designing a protection circuit, the 0V capacitance is determined by the required signal bandwidth. The protection effect is determined by the capacitance ratio between the capacitance at the highest voltage reached during ESD and its 0V capacitance. The larger the ratio is, the better the ESD protection will be. For the X7R capacitor this ratio is usually about 0.3, while it reaches about 3 for the AFE capacitor investigated in this research. This larger ratio allows an improved trade-off between ESD protection and bandwidth.

VI. Conclusion

X7R capacitors are often used as ESD protection. In this application the voltage across the capacitor will surpass the rated voltage, often reaching 400V on a 50V capacitor. The voltage dependence of capacitors with two different dielectric materials, X7R and AFE, are measured using both static and transient measurement methods. Similar capacitance changes have been observed for static voltages and transient voltage changes. The X7R capacitors lose most of their capacitance while the AFE capacitors increase their capacitance values as the voltage increases up to a certain point as shown in Fig. 13, for example. This increasing nonlinearity of AFE capacitor improves ESD protection at a given signal bandwidth. The improvement of the ESD protection has been quantified with simulation. The temperature dependence of the AFE’s capacitance and the long term reliability of AFE capacitors have not been investigated.


This material is based upon work supported by the National Science Foundation under Grant No. 0855878. EMC

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TN003 ESD Simulator Calibration Method for IEC61000-4-2 & ISO10605

TN003_P01 ESD Simulator Calibration setup

Download ESDEMC_TN003 ESD Simulator Calibration Method for IEC61000-4-2 & ISO10605 (PDF)

1. Calibration Objective

The objective of this report is to present calibration parameters required for ESD simulators, verify their performance, and compare the results to the requirements of the IEC 61000-4-2 or ISO10605 standard.

2. Requirements and Equipment

2.1 Tip voltage Verification

Both IEC61000-4-2:2008 and ISO10605:2008 specify that the tip voltage or the HV source of an ESD simulator must be verified with a high voltage meter or electrostatic voltmeter.

  IEC61000-4-2:2008 ISO10605:2008
Voltage calibration Up to ± 15 kV Up to ± 25 kV
Tolerance < ± 5% < ± 5%

Table 1 Simulator tip/HV source voltage tolerance.
When using a contact high voltage meter (>100 G Ohm input impedance) for calibration, the HV source will need to continuously charge the tip to maintain the voltage level, otherwise the meter will discharge the tip and the voltage reading will decrease gradually. ES105-100 High-Impedance High-voltage Meter from ESDEMC satisfies the requirements for HV calibration (>100 G Ohm input impedance and measures up to 100 kV with less than 2% tolerance).

Because the ESD simulator tip is sharp and small, the capacitive coupling between the tip and a non-contact electrostatic meter is weak, and therefore <± 5% accuracy may not be achievable. Further, most precision non-contact electrometers do not measure to ±25 kV. This would require a coupling factor for calibration between the discharge tip and the sensor of the non-contact electrometer. ES102 Vibrating Capacitance Electrometer from ESDEMC satisfies the requirements for the HV calibration (non-contact measurement with self-calibration up to 1 kV). With the coupling factor integrated with the externally calibrated HV source a measurement range of 200 V to 200 kV with less than 2% tolerance is obtained.

2.2 Contact discharge mode current verification

Both IEC61000-4-2:2008 and ISO10605:2008 standards specify that the ESD contact mode discharge current waveform meet the requirements listed in Table 2.


Standards IEC61000-4-2:2008 ISO10605:2008


RC Network 150 pF  330 Ohm


150 pF  330 Ohm

330 pF  2000 Ohm

150 pF  330 Ohm

330 pF  2000 Ohm


Voltage Range CD 2 kV – 8 kV

AD 2 kV – 15 kV


CD 2kV – 15 kV

AD 2kV – 25 kV

First peak



0.6  – 1.0 ns 0.7  – 1.0 ns
First Peak



3.75 A/kV

< ± 15 %

3.75 A/kV

< ± 10 % for 330 Ohm Res

0 ~+ 30 % for 2000 Ohm Res


Current at 40% RC


2 A/kV

< ± 30 %

2 A/kV, < ± 30 %

for 330 Ohm Res


0.275 A/kV, < ± 30 %

for 2000 Ohm Res


Current at 20% RC


1 A/kV

< ± 30 %

1 A/kV , < ± 30 %

for 330 Ohm Res


0.15 A/kV , < ± 50 %

for 2000 Ohm Res


Equipment 4 GHz Wideband ESD Current Target – Attenuator – Cable Chain

< ± 0.5 dB   DC – 1 GHz

< ± 1.2 dB   DC – 4 GHz


> 1.2 x 1.2  meter reference plane


Oscilloscope > 2 GHz analog Band


1 GHz Wideband ESD Current Target – Attenuator – Cable Chain

< ± 0.5 dB   DC – 1 GHz



> 1.2 x 1.2  meter reference plane


Oscilloscope > 1 GHz analog Band


Tolerance Require ESD waveforms to be tested 5 times at each level and all waveforms should be within the standard specification Require ESD waveforms to be tested 10 times at each level and calculated the average Tr, Ip, I1, I2, then the average parameters should be within the standard specification

Table 2 Contact mode discharge current waveform parameters.
ES613 ESD Simulator from ESDEMC satisfies the requirements for both IEC61000-4-2:2008 and ISO10605:2008 (ES613-20 up to ±20 or ES613-30 up ±30 kV).

A4001 ESD Current Target from ESDEMC satisfies the requirements for both IEC61000-4-2:2008 and ISO10605:2008 (up to ± 30 kV).

A4002 ESD Current Target Adapter Line from ESDEMC satisfies the requirements for both IEC61000-4-2:2008 and ISO10605:2008 to calibrate the frequency response of both ESD target and adapter line.

3. Test Setup:

The ESD current target should be mounted in the center of a 60” x 60” (1.2 m x 1.2 m) or larger vertical calibration plane. The plane can be one wall of a Faraday cage. The target is mounted to a 40 mm diameter hole centered in the plane and fastened by 8 screws and lock-washers. An oscilloscope, attenuators, and cabling are located inside the enclosure, or on the other side of the plane from the ESD simulator. Figure 1 illustrates a possible setup.

TN003_P01 ESD Simulator Calibration setup
TN003_P01 Figure 1.ESD Simulator Calibration setup

Connect the attenuator directly to the ESD target output. If it is expected that the output voltage will exceed the oscilloscope input voltage rating additional attenuation may be used. Please refer to the Attenuation Calculation section below for details on selecting proper attenuation. Connect the ESD ground return cable to the target plane according to the standard. A simplified block diagram is shown in Figure

Typical setup of ESD simulator measurement
Figure 2. Typical setup of ESD simulator measurement

Attenuation Calculation

ESD Target with 20 dB attenuator configuration
Figure 3. ESD Target with 20 dB attenuator configuration

In the diagram above, a 20 dB attenuator is used in the measurement of an ESD discharge event, and an oscilloscope is represented as a 50 Ohm load. Because of the 20 dB attenuator the voltage seen at the input of the oscilloscope is 1/10 of the voltage incident at the target, or
V2= V1/10.
Because the attenuator is terminated in 50 Ohm, the input impedance seen at port 1 is 2.08//50 Ohm = 2.00 Ohm, meaning
V1 = Iesd ×2.00 Ohm
Where, IESD is the current into port 1 during a discharge event. The 2.08 Ohm resistor is the specification for an ESDEMC factory calibrated A4001 Target. This may be different for other manufacture’s targets. The ratio between ESD current and voltage present at the oscilloscope is then
Iesd / V2 = 5:1
This ratio is useful for determining how much attenuation is required for oscilloscope safe measurements because the currents for different high voltage set points are known. For example, during an 8 kV ESD test a discharge current, IESD, is expected to have a 30 A peak, corresponding to a peak voltage at the oscilloscope of 6 V. Additional attenuation should be added at the beginning of any new measurement setup to ensure safety of equipment until confidence in the setup is established.
An ESD Source Voltage versus Recommended Target Attenuator Size table is calculated below for reference. It is based on a 50 Ohm 5 Vrms real time oscilloscope measurement (a measurement range of 8 V with 1 V/div). The green zone is a safe operating area, and the numbers therein are the peak voltages seen at the oscilloscope. The yellow zone is a boarder-line area and should probably be avoided because when considering the ±15% peak current tolerance margin from standard, it might not be enough. A GHz high speed Oscilloscope has max voltage reading of 8V or 10 V at maximum scale:

ESD Source
Peak I
First Peak Voltage in Oscilloscope
Attenuation after ESD Target
20 dB 26 dB 30 dB 40 dB
4 15 3.0 V 1.5 V
8 30 6.0 V 3.0 V
15 56.25 11.25 V 5.62 V 3.56 V 1.13 V
25 93.75 18.75 V 9.38 V 5.93 V 1.88 V
30 112.50 22.5 V 11.25 V 7.12 V 2.25 V

Table 3 ESD Source voltage and Recommended Target Attenuation Setups.
Expected Waveform (for IEC standard)

The expected 4kV IEC 61000-4-2 standard waveform is shown in Figure 4.

Figure 4: Ideal IEC 61000-4-2 ESD Simulator Waveform
Figure 4: Ideal IEC 61000-4-2 ESD Simulator Waveform

Measurement 8kV IEC Result

Figure 5 Measured IEC 61000-4-2 ESD Simulator Waveform
Figure 5 Measured IEC 61000-4-2 ESD Simulator Waveform


Test Levels Indicated Voltage First Peak (±15%)

Trise = 0.8 ± 0.2 ns

Current @ 30 ns


Current @ 60 ns


Level 1 ±2kV 7.5 A 4 A 2 A
Level 2 ±4kV 15 A 8 A 4 A
Level 3 ±6kV 22.5A 12 A 6 A
Level 4 ±8kV 30 A 16 A 8 A


Voltage Rise time (ns) Peak Current  [A] Current  at 30 ns [A] Current  at 60 ns [A] Result
IEC (±20%) Cal Result IEC (±15%) Cal Result IEC (±30%) Cal Result IEC (±30%) Cal Result  
2 kV  




0.905 7.5 (6.375~8.625) 7.6 4 (2.8~5.2) 3.45 2 (1.4~2.6) 1.75 PASS
4 kV 0.909 15 (12.75~17.25) 15.15 8 (5.6~10.4) 7.6 4 (2.8~5.2) 3.3 PASS
6 kV 0.914 22.5 (19.125~25.875) 22.3 12 (8.4~15.6) 11.3 6 (4.2~7.8) 5 PASS
8 kV 0.925 30 (25.5~34.5) 30.6 16 (11.8~20.8) 15.5 8 (5.6~10.4) 6.5 PASS

Table 4 IEC 61000-4-2 contact discharge current waveform parameters.


4. FAQ Section

4.1 How do oscilloscope bandwidth / sampling rate affect calibration?

Some ESD events have been measured with a rise time <100 ps and the actual ESD waveform may be even faster. The bandwidth needed to resolve such a fast rise time is approximately 0.35/rt, or 3.5 GHz for a 100 ps rise time. Without enough bandwidth or sampling rate, the rise time will be down sampled and not adequately captured. A simplified comparison of the same rise time with not enough and enough sampling rate, respectively, is shown below,

Figure 6 Rise-time comparison with and without enough sampling rate
Figure 6 Rise-time comparison with and without enough sampling rate

In addition, the oscilloscope bandwidth / sampling rate could affect the measured first peak value as the first peak contains high frequency components. Even a waveform measured with the same oscilloscope with different sampling rates will show different results. This could lead to an ESD simulator appearing to have passed the standard with a slower sampling rate, but actually failing with a higher sampling rate. An example of this is shown below,

Figure 7 Effect of using different sampling rates with the same oscilloscope
Figure 7 Effect of using different sampling rates with the same oscilloscope


4.2 When buying an ESD Target, can I buy only the ESD target and use the cable and attenuators already in house for the calibration?

The standards require the ESD Target-Attenuator-Cable Chain (up to the connection to the oscilloscope) and the oscilloscope to be calibrated before the ESD simulator calibration test. If the ESD target is calibrated without the attenuator and cable, the ESD Target will have to be recalibrated with the new cable and attenuator. Or one should characterize the effects of their own cables and attenuators to compensate for them mathematically.
For cable selection, the standard requires the test cable to be well shielded and low loss. A RG400 cable no more than 1 meter long is preferred by the standard. RG 214 is 1/2 the loss and is commonly available, but may not be available with SMA connectors. Most high speed oscilloscopes use SMA or improved BNC connectors.
For attenuator selection, the frequency response needs to be flat up to 4 GHz to make the overall transfer impedance of Target-Attenuator-Cable Chain flat according to test standard. Also the attenuator needs to be able to handle a relatively large peak power rating.

4.3 How do the other setup parameters affect the waveform?

Parameters Influence
Shielding A 1.2 m x 1.2 m reference plane is required for the shielding against the direct coupling between oscilloscope and the ESD simulator. It is required by the standard.  And the measurements observed by different oscilloscopes can be very different.  Some oscilloscopes will show significant noise coupling (without the ESD target connection), and some will show very little.
Position of ground cable


The length and shape of the grounding wire, and thereby the effective inductance of the loop, will affect the secondary RC peak.  This should be positioned correctly, but the effects on waveform are normally small.
Orientation of simulator


This typically has some effect on the test waveform but normally small.
Air Discharge


The approach speed and environmental factors greatly affect results making repeatability difficult.

Table 5 Parameters and their influence


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TN002 ESD Target Calibration Method

Download ESDEMC_TN002 ESD Target Calibration Method (PDF )

1. Calibration Objective

The objective of this report is to calibrate the ESD target and check its performance and compare the results to the requirements of the IEC 61000-4-2 standard.
Requirements from IEC 61000-4-2 standard:

1. Input Impedance of ESD target

The Front Side of ESDEMC A4001 ESD Current Target
Figure 1 The Front Side of ESDEMC A4001 ESD Current Target

The ESD current target used to measure the discharge current from ESD generators should have input impedance between the inner electrode and ground ≤ 2.1 Ohm @ DC.

2. Insertion Loss of the Target-Attenuator-Cable Chain

ESDEMC A4001 ESD Current Target-Attenuator-Cable Chain
Figure 2 ESDEMC A4001 ESD Current Target-Attenuator-Cable Chain


Instead of specifying the insertion loss of the ESD current target, the insertion loss of the measurement chain consisting of the target, attenuator and cable is specified. The variation of the insertion loss may not exceed:
+/- 0.5 dB up to 1 GHz
+/- 1.2 dB 1 to 4 GHz.
The nominal value S21 of the insertion loss:
S21 = 20*log [2*Zsys/(Rin + 50 Ω) ] dB
Where Rin is the DC input impedance of the chain when loaded with 50 Ω.

2. Measurement Setup and Results:

Device Manufacture Model Serial Number Calibration Due
Network Analyzer Agilent E8357A US42070561 08/13/2016
VNA Calibration Kit Agilent 85092C MY46180831 08/14/2016
Digital Multi-meter Keithley 2110 1374108 07/15/2016
Digital Power Supply Agilent E3648A MY40004580 07/20/2016
ESD Target Adapter Line ESDEMC A4002 A4002-001 09/02/2016

Table 1. Measurement Equipment used in this report
1. For the DC input impedance
An LCR meter or a 4 wire source-measurement-meter (SMU) should be used to measure the DC input impedance. The electrodes should be connected in parallel to the input of the target. In this calibration report, the target was connected with a 20 dB attenuator plus the RG400 cable and a 50-Ohm termination. A value of around 2.00 Ohm should be measured.
2. For the frequency response
The ESD current target, attenuator and coax cable are attached to the target adapter for determination of the frequency response. The typical setup is shown in figure 3:

Mount ESD Target on to Target Adapter Line and connect to VNA
Figure 3 Mount ESD Target on to Target Adapter Line and connect to VNA


The Insertion Loss - S21 of ESDEMC A4001 ESD Target Chain (SN A4001-195)
Figure 4 The Insertion Loss – S21 of ESDEMC A4001 ESD Target Chain (SN A4001-195)


 Transfer Impedance of the ESDEMC A4001 ESD Target Chain (SN A4001-195)
Figure 5 Transfer Impedance of the ESDEMC A4001 ESD Target Chain (SN A4001-195)

For measuring insertion loss of the target-attenuator-cable chain, a network analyzer was used to measure the S21. The S21 result of the setup is shown on figure 4. The red dash lines are the limits from the ICE 61000-4-2 standard. So this ESD Target is within the spec per ICE 61000-4-2 standard.

3. Maintaining the Current Target Performance

The performance of the current target shall be verified at least every two years. It is sufficient to verify the DC-characteristics of the target. The rational is that changes in the overall mechanical geometry are very unlikely, as they require a lot of force. The only place damage can occur is at the connector (inspect visually) and at the resistors due to excessive force on the center conductor of the target. If resistors break or get otherwise damage these change will be seen at DC and at high frequencies.
The test can be done by injecting a current of about 1 A into the target while terminating the target with 50-Ohm. The DC transfer impedance, defined as the voltage measured across the 50 Ohm termination divided by the input DC current of about 1A. It shall not deviate from the expected by more than 2%. Care must be taken to inject the current at two points that are different from the points at which the voltage is measured. This is typical for 4-wire resistance measurements. It is suggested to inject the current at the front side of the target and to measure the voltage on the back side of the target. A T-junction connector can be used to attach a DC voltage meter and a 50-Ohm termination at the same time. Often it is advisable to perform the test with two opposing polarities of the DC current and to take the average of the two resistance readings. This cancels effects of thermal voltages that might occur across contacts of different material. A direct use of a 4-wire, 4-contact impedance meter might lead to instable results as long as the target is mounted in a large ground plane, due to noise coupled into the 4-wire, 4- contact connection setup. It is suggested to test the measurement setup on a known, low impedance (e.g., 1 Ohm) resistor at first.

Reference: IEC 61000-4-2 standard ed2.0 – 2008

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TN001 ESD Target Adapter Line Calibration Method

Face-to-face adapter line calibration test setup

Download ESDEMC_TN001 ESD Target Adapter Line Calibration Method (PDF )


Model A4002-N ESD Target Adapter Line
Figure 1. Model A4002-N ESD Target Adapter Line

1. Calibration Objective

The objective of this report is to calibrate the ESD target adapter line and check its performance and compare the results to the requirements of the IEC 61000-4-2 standard.
Requirements from IEC 61000-4-2 standard:
The 50 ohm conical adapter line connects the 50 ohm cable to the input of the ESD target. Geometrically, it smoothly expands from the diameter of the 50 ohm coaxial cable to the diameter of ESD target. If the target is made such that the impedance calculated from the diameter ratio d/D not being equal to 50, the target adapter line shall be made such that the outer diameter of its inner conductor equals the diameter of the inner electrode of the current target. The impedance is calculated considering the dielectric constant of the material that fills the conical adapter line (typically air).

The target adapter line shall show an impedance of 50 ohm +/-2% from DC to 4 GHz. The reflection coefficient of two target adapter lines face-to-face mounted shall be better than 30 dB up to 1 GHz and better than 20 dB up to 4 GHz while the insertion loss shall be less than 0.3 dB in the same configuration.

2. Measurement Setup and Results:

In the test, two identical ESD target adapter lines are mounted face to face and connected to a calibrated network analyzer.

Face-to-face adapter line calibration test setup
Figure 2. Face-to-face adapter line calibration test setup

The measure results, S11 and S22 values, show the reflection coefficient of the ESD Target adapter line, which according to the standard the value should be better than 30 dB up to 1 GHz and better than 20 dB up to 4 GHz, the S21 or S12 values show the insertion loss of the shall be less than 0.3 dB. The results below are the examples passed the Requirements from IEC 61000-4-2 standard:


Insertion Loss and Reflection Coefficient of 2 Face to Face Mounted ESDEMC A4002 ESD Target Adapter Lines
Figure 3. Insertion Loss and Reflection Coefficient of 2 Face to Face Mounted ESDEMC A4002 ESD Target Adapter Lines



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PB2009.08 A Measurement Technique for ESD Current Spreading on A PCB Using Near Field Scanning

Download PDF – A Measurement Technique for ESD Current Spreading on A PCB using Near Field Scanning

Abstract — Electrostatic discharge (ESD) can cause interference or damage in circuits in many ways e.g., by E- or Hfield coupling or via conduction paths. Although we can roughly estimate the voltage and current at the injection point during an ESD event, the real offending parameter is mostly the ESD current spreading throughout the system. Those currents can be simulated if great simplifications of the system are accepted.
However, even in moderately complex systems the ability to simulate is limited by lack of models and computational resources. Independent of the complexity, but obviously not free of its own limitations is a measurement technique that captures the current as a function of time and location through the system.
This article describes the proof on concept of ESD such a measurement technique that allows reconstructing the spreading current as a movie from magnetic field measurements. It details the technique, question of probe selection and how to process the data to present the current spread as a movie.


ESD can damage or disrupt a system. Understanding of system level ESD has been approached from different directions, such as ESD generator modelling [1], in circuit measurements [2], air discharge analysis [3], numerical simulation of currents and fields, protection circuit analysis, etc.

One of the effective methods for analysing ESD robustness is using a three dimensional scanning system to localize ESD sensitive areas or traces [4, 5, 6]. In conjunction with the circuit information the root cause of a system level problem often can be fully understood.

However, as in near field scanning, it is not obvious to connect local results (e.g., sensitive area, or strong fields in near field EMI scanning) to system level performance. For ESD one needs to understand which current densities, field strengths and derivatives are to be expected at one location if an ESD is injected into a test point.

The sensitive areas found by near field susceptibility scanning might not be those, which will receive a lot of current or field strength during an ESD. Thus, the current spreading during an ESD needs to be known to connect local sensitivity data with system level responses.

This article reports on our proof of concept for a current spreading measurement method. The main objective of the research is to develop a method to measure and reconstruct current spreading and field coupling in or close to circuits by scanning; to correlate system level ESD with scanning level ESD in time and spatial domain; and at the end to analyze and extract circuit and layout design strategies for ESD current protection.

This paper is mainly describing the methods of ESD current reconstruction on PCB. Research beyond this simple PCB will be continued in the future.


For a proof of concept the structure of the device under test (DUT) and the experiments based on it have to be simple but meaningful. Fig. 1 shows the PCB structure we used:

It is a simple two layer PCB with 3 traces on the top layer and a solid ground plane on the bottom layer. Signal probing (for traces) is performed via SMA male to male connectors at the back side of the PCB. Their ground connects to a large ground plane. Injection is performed via a coax connection on the edge of ground layer. This allows easy numerical modelling. Fig. 2 is the setup picture:

For the test setup above, the injected current from the cable centre conductor will spread on the top PCB ground layer (both sides of the copper) and return via the 6 SMA connectors outer conductors to the large aluminium ground, then return to the injection cable through the injection structure. This current spreading and return is shown in fig.3 (top view) and fig.4 (side view).


To capture the current, the magnetic field is measured by placing a probe close to the surface of the PCB. An ESD pulse is injected into the PCB and the magnetic field is captured. Due to the close proximity of the probe to the PCB one can approximately equate the magnetic field to the surface current density. Then the probe is moved to the next location and another pulse is injected. This is repeated until a sufficient number of locations have been measured. There are a couple of choices for setting up the measurements:

a) Probe Selection.

Before choosing current probes, we need to understand the E and H field coupling of the ESD scenario [7, 8, 9]. Fig. 5 shows the 3 field coupling paths we are concerned about:

We want to suppress the E-field. There are two relevant currents: The current density on the PCB and the currents on the traces. We are interested in both. The magnetic fields of the trace currents are often much weaker than the magnetic field of the surface current density.

Therefore it is difficult to measure trace currents by the same H-field probe that is used for the ground layer current. However, the field components are different. The trace current has an Hz field component. It is possible to separate the trace current by measuring the Hz component over the PCB. Probe selection requirements are:

1) The probe needs to suppress the E-Field, otherwise the E-field coupling will easily override the H-field coupling from the current.

2) The probe for measuring the ground layer current can be a shielded vertical loop probe measuring Hx or Hy. The trace current that is induced into the traces generates much weaker Hx Hy components, they are mostly overwhelmed by the Hx and Hy components from the ground layer current. In the test we used a 6 by 8 mm coaxial shielded vertical loop probe to capture Hx and Hy from the PCB ground layer current.

3) A good probe of measuring trace current in this scenario needs to well reject ground layer current coupling. For this application, a 3 by 3 mm patent pending trace current probe was designed to capture the trace current. It measures the trace currents Hz components since Hz is dominated by trace current locally and incorporate other features.

b) Time or Frequency Domain.

The first set of data presented here has been captured using a transmission line pulser (TLP) as source (about 300 ps rise time) and a real time oscilloscope to capture the signal. The use of a Network analyser (NWA) is also discussed further down this article.

A. TLP and Oscilloscope Scanning Method Setup

Fig.6 shows the test setup for current reconstruction scanning using a TLP and an oscilloscope.

The current is injected from the right middle edge (x =300mm, y = 150mm) of the PCB into the ground layer. From the injection point current spreads over the ground layer as fig. 3 showed before, and couples to the 3 traces. All traces are terminated by matched loads. A shielded vertical loop will measure the current spread on the surface of the PCB with 2 orthogonal directions (measuring Hx and then Hy components separately). In this way, two sets of data will be created for data processing.

The oscilloscope records data after receiving a trigger from the TLP. Providing the TLP repeats well all measurements are “synchronized” and show the current spread when plotted as a function of time. The probe couples to the time derivative of the current density via a probe factor. Thus multiplication by the factor (yet unknown, but a pure function of geometry) and integration would allow determining the current in absolute values.

B. Network Analyzer Scanning Method Setup

Our test setup is linear with respect to current. Thus, one is not forced to use a high voltage generator as injection. A network analyzer with time domain transformation can be used instead as setup in fig. 7 shows. The setup of the network analyzer is very similar to the TLP and oscilloscope method, the only difference is that the injection part is connected to network analyzer port 1; the probe is connected to the network analyzer port 2. S21 is measured and transformed to the time domain. To improve the signal to noise ratio, a 20 dB amplifier is added at the receiving port.

Its excitation equals the excitation of a step function (or the user could select an impulse transformation instead) [10]. For a linear system a network analyzer has many advantages over a direct time domain measurement:

It has better repeatability as it is frequency domain measurement, unlike TLP which uses a High Voltage relay to produce pulses.

Network analyzers have much better dynamic range than oscilloscopes

The time domain image of the signal injected by the Network analyzer is clean, e.g., there is no ringing, or overshoot. Fig. 8 shows the voltage waveform comparison.


A. Reconstructed Movie using the TLP and Oscilloscope Scanning Method on PCB Ground Layer

Fig. 9-12 show 4 fames of the reconstructed current spreading on the PCB surface when the shielded vertical loop probe is oriented at x-axis direction.

The first frame shows a very large current density at the injection moment. The current spreads in a circular fashion on both sides of the board as shown in frame 2 and 3. All frames here illustrate only the Hx component on the top side of the board. The board is connected to a large ground plane via SMA male to male connectors on PCB bottom side so most of the current will return through them. After the waveform reaches the left side of the board, reflections are visible in the last frame.

B. Reconstructed Movie for the Network Analyzer Scanning Method on PCB Ground Layer

Below are 2 current reconstruction frames obtained using the network analyzer scanning method:

The data shown in Fig.13 indicate that the wavefronts are better visible using the network analyser method. The large dynamic range of the NWA allows us to follow the current wave front over a larger distance.

However, it is necessary to use a network analyser that can cover the frequency range from 100 KHz – 3GHz; otherwise the missing frequency component will distort the time domain signal, especially the tails.

C. Data Process in MATLAB

The total field is reconstructed using MATLAB from two orthogonal scans (Hx and Hy). The scanning resolution was set to 1 by 1 cm. This leads to 30 by 30 scanning points for each scan. Fig. 14 shows 3 plots resulting from the recovering process.

The first plot is using the raw data taken from the Hy scanning. When the vertical loop probe is oriented such that the loop is normal to Y-axis, it measures the Hy component which is mainly generated by the current flowing in the direction of the X-axis.

The second plot shows the result of the Hx scanning. When the vertical loop probe is oriented such that the loop is normal to the X-axis, it measures the Hx component which is mainly generated by current flowing in Y direction. The first and second frames are snapshots at the same moment for better understanding and comparison.

The third plot in fig. 15 plots the root square sum of the raw data from the two orthogonal scanning results:

 This is the magnitude of the total horizontal H-field strength close to the plane which equals the current density on the PCB ground layer.

D. Trace Current Reconstruction

If the vertical loop is used, we can hardly see the H-field of the trace current (the trace current caused by the current injected into the PCB). It is overwhelmed by the magnetic field of the ground plane current.

Different probes have been designed a special probe just for the trace current. These probes detect the magnetic field from the trace while suppressing other field components. Fig.15 shows the comparison of the probe response when moving it across a trace during ground layer injection:

The vertical loop can hardly detect the trace current (blue trace). The horizontal loop detects the Hz component; it can detect the magnetic field of the trace current (green trace). The response of the trace current probe (red) detects only the trace current as one peak, which is located above the center of the trace.

Fig. 16 shows one frame of the current reconstruction using the trace current probe and a frame from the CST simulation movie. In both the trace current is visible.

One final remark on the trace current probe: It recovers the trace current well, but it is only sensitive to the Ix or Iy current, thus two scans need to be conducted for full reconstruction.


The paper presents a prove of concept for a measurement method that reconstructs currents spread as a function of time for ESD or other pulses injected into a system. A special probe is able to suppress the ground plane current to extract trace currents; its principle function has been shown.

The next steps are a comparison to simulated data and a comparison of local current density and field strength, as seen during a system level ESD tests compared to local current density and field strength as they are caused by local injection during ESD scanning. This will further help to connect local to system level results.

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PB2003.11 Problems with the electrostatic discharge (ESD) immunity test in electromagnetic compatibility (EMC)

Download PDF – Problems with the electrostatic discharge (ESD) immunity test in electromagnetic compatibility (EMC)

Asia-Pacific Conference on Environmental Electromagnetics, CEEM’ 2003 Nov. 47,2003 Hanzhou .China

Jiusheng Huang*, David Pommerenke**, Wei Huang**
*)Beijing Institute of Electromechanical Technology, Beijing, China, jshuang@ESD-China.Com
* *) Electromagnetic Compatibility Laboratory, University of Missouri-Rolla, USA
***) Beijing University of Post and Telecommunication, Beijing, China

Abstract- Electrostatic discharge (ESD) immunity test is one of the important electromagnetic compatibility (EMC) tests. The IEC standard IECdlOOO-4-2 is the widely used standard to test the ESD immunity for electronic equipment. Many amendments such as amendment 1 (1998), amendment 2 (2000) have been published since 1995, but there is still problems with the ESD immunity test even with the 200x version. More than six ESD generators of different bands are tested for different equipment. The results show that the failure voltages of different ESD generators are vary much from different bands for the same test equipment. This may lead to the results incomparable when test the ESD immunity test in the EMC. Further studies show that there is a good correlation between the failure voltage and the induced voltage.

1. Introduction The electrostatic discharge (ESD) current waveform of the IEC61000-4-2 s&ndard[ 11 is shown in figure 1. It says the rise time of the first peak is 0.7-1 ns and the current is in the range of 3.375-4.125 A/kv. The current at 30 ns is in the range of 1.4-2.6 A/kv and the current at 60 ns is in the range of 0.7-1.3~kv. Many works were made on the research of the ESD current, electromagnetic and magnetic field radiated from the ESD[2-51. Any ESD generator is standard if its ESD current is per IEC61000-4-2 standard. The failure ESD voltage for the same equipment should be the same in certain tolerances. But the failure voltages for the same equipment are very large for more than six bands of ESD generators. This paper is to investigate the main reasons and the factors which influence the compatibility of the results.

2. Test 2.1 Test setups More than six bands of ESD simulators from different factors were used as the test equipment of the experiment. A high speed oscilloscope (TekTonix TDS7404 Phosphor oscilloscope 4GHz, 20GS/s) and ESD current targets and field sensors were used as the main equipment in our experiment.

2.2. Test Results

All the ESD generators are calibrated as the IEC6 1000-4-2 standard requirements. They have the same ESD current as the standard. The ESD failure voltages of the same electronic equipment for different bands of ESD generators were tested. The failure voltage may be very much from 1kV to even 6kV for the same equipment even if all the ESD current are accordant with the same standard. This may lead to the results incomparable when test the ESD immunity test in the EMC.

2.2.1 The influence of the ground strip to the ESD current waveform Many factors such as the parasitic capacitors and inductors will influence the waveform of the ESD current and the failure voltage in our experiments. The rise time, the first peak of the ESD current and the shape of waveforms of the ESD current are easily influenced by those factors. But those parasitic capacitors and inductors are constant in a given ESD generator when it is made in the factor. Other factors such as the length and shape of the ground strip are vary in the practice experiment. The waveform of the second segment is influenced by the RC network and the shape and position of the ground strip. Several tests are made to demonstrate the effects. A ESD generator is used to test the waveform. The results are shown in figure 3 and figure 4. Figure 4 has some offset in order to observe easily (Total Y offset 70%, Total X offset 20%)

It can be seen from figure 3 and figure 4 that when the ground strip is in winding, that is the inductance is very large, the waveform (Black) vibrating during the decay period. When the ground strip is in straight line, the waveform (Blue) is very similar to the waveform proposed by IEC standard. When tlhe ground strip is in other shape and position, the waveform is also influenced by the inductance.

2.2.2 ESD induced voltage Voltage induced by both the electric field and magnetic field radiated from ESD at a given distance can be easily measured than that of the electric field and magnetic field. It is mainly the induced voltage which makes the electronic equipment failure. So, more attention will be paid to the induced voltage. There &e two typical induced voltages which represent the real effects of ESD. One is the monopole induced voltage. It is mainly induced by electric field. Another is the loop induced voltage which may be induced by both magnetic field and electric field if the sensor is not electric shielded. In order to test the ESD current, monopole induced voltage and loop induced voltage. Three channels of the digital oscilloscope is connected to ESD current target, monopole with 10″ length and the half circular loop with diameter of 13 mm respectively. It will be unstable due to the lower sampling rate when three or more channels are used simultaneously. But the concurrent phenomena can be easily observed.

2.3 ESD current and ESD induced voltage In order to test the ESD current and ESD induced voltage in the sensor. Two channels of the oscilloscope are connected the ESD current target and the loop sensor. The ESD current is much varies with the ESD induced voltage in shape and duration. The induced voltage is very short in duration than that of the ESD current shown in Fig.6. The induced voltage may be small just like noise after several ns even if the ESD current is increase.

Figure 6 shows that the ESD current will increase after 10 nanoseconds due to the discharge of the capacitor in the ESD. But the induced voltage doesn’t increase any more. This further demonstrates that the induced voltage doesn’t correlate with the ESD current.

For the same equipment the failure level of discharge may be from 1kV to 6kV. But there is good correlation between the ESD susceptibility and induced voltage from different simulators. The correlation coefficient R= -0.88567, standard deviation SD= 0.86476[2].

3. Conclusions and Future Works ESD current for different ESD simulators are tested. The ESD susceptibility of computer with different CPU and auto switch are experimentally investigaied. ESD induced voltage are tested for different ESD simulators. Some conclusions are summarized [ 51. 1. The parasitic inductor and capacitor of the ESD simulator are critical factors which will influenced the both the waveform of the ESD current and the ESD model of discharge, Different ESD simulators have different parasitic parameters that lead to the different ESD susceptibility. 2. The shape and position of the ground strip of the ESD simulator will influence the inductor of the LCR and lead to the generation of different waveform of the ESD current. These two factors are mainly source lead to the variation of the ESD susceptibility of the electronic equipment. 3. ESD induced voltage doesn’t correlate with the ESD current but it is correlated with the induced voltage. It is generated by the process of contact of the relay in the ESD. The duration of the ESD voltage is about 5 nanoseconds and the typical duration of ESD current is more than 100 nanoseconds. The ESD susceptibility is very complicated. It may be influenced by both the ESD current and Electromagnetic, and magnetic field radiated from the ESD. If the ESD current and the induced voltage can be defined more exactly, the ESD susceptibility test results may be more repeatable.


Thanks go out to Dr. Thomas Van Doren of EMC laboratory, University of Missouri-Rolla for his warmly supports to the ESD work, Kai Wang and all students in UMR for their supports and helps during my stay in UMR from 2002-2003.