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PB2010.11 Full-Wave Simulation of an Electrostatic Discharge Generator Discharging in Air-Discharge Mode Into a Product

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Abstract—This paper introduces a methodology to simulate the currents and fields during an air discharge electrostatic discharge (ESD) into a product by combining a linear description of the behavior of the DUT with a nonlinear arc resistance equation. The most commonly used test standard IEC 61000–4-2 requires using contact-mode discharges to metallic surfaces and air-discharge mode to nonconducting surfaces. In the contact mode, an ESD generator is a linear system. In the air-discharge mode, a highly nonlinear arc is a part of the current loop. This paper proposes a method that combines the linear ESD generator full-wave model and the nonlinear arc model to simulate currents and fields in air-discharge mode. Measurements are presented comparing discharge currents and fields for two cases: ESD generator discharges into a ground plane, and ESD generator discharges into a small product.

Index Terms—Air-discharge mode, cosimulation, electrostatic discharge (ESD) generator, full-wave modeling.

I. INTRODUCTION

Simulating electrostatic discharge (ESD) allows predicting the currents and fields seen within a device under test (DUT) during an ESD, thus it helps to predict failure levels [1], [2]. The most commonly used test standard IEC 61000–4-2 [3] requires using contact-mode discharges to metallic surfaces and air-discharge mode to nonconducting surfaces. If an air discharge is attempted to a nonconducting surface, a discharge to a conducting part can occur.

In contact mode, the output waveform is proportional to the charge voltage, thus, the ESD generator can be analyzed as a linear system in both time domain (TD) and frequency domain (FD) [4]. Those models [5]–[8] for contact mode differ in the software used, the upper frequency limits, and if a specific commercial model of an ESD generator is simulated. However, the numerical modeling of an air discharge is more complex due to the highly nonlinear behavior of the arc [9]–[14]. The generator needs to be separated into the linear sections comprising the metallic elements, resistors, capacitors, and the nonlinear arc. It has been shown that the arc can be modeled as a time-varying resistor valid for the first tens of nanoseconds [13]. This model needs to be integrated into the numerical model.

Air-discharge currents badly repeat. Even if the voltage and speed of approach are kept the same, ESD currents will vary strongly from discharge to discharge. The variations are due to different arc lengths and not a direct result of corona or speed of approach [13]. In [12], a method to combine the arc model from Rompe and Weizel with an equivalent circuit of the discharging object is shown. This methodology is expanded in this paper to combine a linear full-wave model of the ESD generator and the DUT with a nonlinear arc model. Currents and fields are obtained.

Section II introduces the methodology. Sections III and IV verify the methodology by comparison to measured data. Section V discusses the application and the limitations of this method.

II. METHODOLOGY

In general, different processes are possible for coupling SPICE to a full-wave solver: Simultaneous solution exchanges voltage and current information with a SPICE-like solver after every time step of the full-wave solution [15], [16]. Sequential solutions first calculate the S-parameters of the linear section of the circuit and then combine them with the nonlinear part of the circuit in SPICE. We use the second method. It allows reusing the S-parameters to save calculation time, if only the arc parameters are changed.

More in detail, a four-step process is used, which simulates linear parts in full wave and nonlinear in SPICE. The arc attaches at two points: at the ESD generator tip and at the DUT. These two points are used to define a port. In the first step, the impedance at this port is calculated. This is the impedance looking into the DUT and a Noiseken ESD generator (ESS2000). The simulation is performed using computer simulation technology (CST) [17]. Both the TD and FD solver can be used. Although the impedance Z11 is calculated in the full-wave model for a given distance (0.7 mm) between the ESD generator and the DUT, different distances will influence the result little as long as the distance is in the arc length range (0.3–3.0 mm). The tip to ground capacitance is small relative to the distributed capacitance of the rod. This impedance is transformed into a form suitable for TD simulation. Here, the commercial software Broadband SPICE [21] was used. An order of 28 was selected to generate the circuit. SPICE then combines the impedance description from step 1 with an arc model based on the law of Rompe and Weizel. This law describes the arc during the first tens of nanoseconds as a resistance and has been validated for ESD applications [18], [19]. The resulting current is reimported into CST as the excitation waveform of the current port, which is placed between the two points that had been previously selected to define the impedance port to calculate Z11 to obtain fields and currents within the ESD generator and the DUT. The process is summarized in Table I.

The detailed combination in SPICE is now shown (see Fig. 2). The Z11 describes the linear part of the system. Once the Z11 has been obtained, it needs to be transformed into a form suitable for TD simulation. Software tools like IDEM [20] or Broadband SPICE [21] have been used successfully in this research. The subcircuit created from Z11 is not unique. Its complexity can be user defined, which depends on the transformation algorithm, the error, and the order of interest.

The arc of an ESD can be modeled by breaking it down into different phases. The first phase is the resistive phase. The arc is best modeled by a time varying resistance. In the second phase, which is usually reached after a few tens of nanoseconds, the impedance of the external circuit is larger than the impedance of the arc. In this case, the arc often acts more as a constant voltage drop of about 25–40 V. The rising edge of the ESD is the main contributor to the radiated and inductive coupling into DUTs. For this reason, we concentrate on the resistive phase and do not model other aspects (e.g., how the arc extinguishes). Multiple models describe the resistive phase or arcs [18], [19], [22]. In [13], it has been shown that the model of Rompe and Weizel is the most suitable for ESD simulation, as it can correctly describe the effect of the arc length on the rise time and peak current. The arc resistance can be calculated as follows [13]:

The structure of the SPICE model is shown in Fig. 2. A step function having a rise time of approximately 30 ps was used as the source. The rise time is selected by two criteria. If it is too long, then it will influence the current rise time. The current rise time should be determined only by the arc resistance law and the linear equivalent circuit. Further, the rise time cannot be too small, if the pulse contains strong frequency components beyond the range, in which the impedance is calculated, it can lead to instabilities in the SPICE simulation. The fast voltage rise starts the arc resistance model. The current rise time is not determined by the rise time of the step function, but by the arc resistance model. The subcircuit represents Z11 . The user provides the voltage and the arc length to calculate the discharge currents. The longest possible arc length in a homogeneous field is given by the Paschen law [13]. Such arc lengths would occur in air discharge for low approach speeds or in humid air conditions. The long arc length leads to slow rise times and lower peak values. Longer arc lengths than the length given by Paschen’s equation are possible in strongly nonhomogeneous fields, e.g., if the discharge is between an ESD generator and a sharp edged metal part, or if the discharge is gliding on a nonconducting surface. Very short arc lengths occur at high approach speeds and in dry air [9], [13], [23], leading to fast rise times and very high peak current values.

In the following, we will first apply this methodology to a discharge to a ground plane, mainly for verification purposes, and then to a discharge to a small MP3 player.

III. CASE 1: ESD GENERATOR DISCHARGE TO A GROUND PLANE

A. Z11 Between the Tip of the ESD Generator and the Ground Plane

The structural and discrete elements of the ESD generator are linear with respect to voltage. We further assume that the DUT acts linearly. For obtaining the current injected by the arc, this does not require that no nonlinear effects take place inside the DUT; it only requires that the current injected into the DUT is proportional to the charge voltage. For example, if an internal ESD protection device would clamp a trace voltage while the ESD current is injected into the ground system of the DUT, then, this clamping would have hardly any effect on the current, thus, the DUT would act as a linear device, as seen by the ESD generator. However, if secondary breakdown occurs, e.g., a spark within an attached two-wire power supply, then this could strongly affect the ESD current, thus, the modeling approach might lead to wrong results.

Both TD and FD solvers can be used to obtain Z11 . We observed the FD simulation giving a more reasonable Z11 result and using less simulation time. The simulated Z11 for the structure of the ESD generator above a ground plane is shown in Fig. 3 as the dotted line. This result is verified by comparison with measurement and an approximate SPICE model of this ESD generator [4]. The model contains sufficient detail for achieving a good match to measured impedance data, and correctly represents the 110-pF capacitor and 330-Ω resistor structure inside the ESD generator at lower frequencies. The calculation takes about 15 h on a PC (CPU 3.20 GHz, 16G RAM).

ESD generators have long ground straps. It increases the simulation time if the full length is included into the simulation domain. As most disturbances are caused by the fast changing parts of the currents and fields, one may not need to include the full ground strap into the model. The ground strap mainly influences the falling part of the waveform. The SPICE model shown in Fig. 4 includes a 3500-nH inductor to model the ground strap. A shorter ground strap will reduce the time between the first and the second peak of the discharge waveform.

The first step obtained the impedance representing an ESD generator discharges to a large ground plane. In the next step, the impedance is transformed into the TD suitable form and combined with a nonlinear arc equation in SPICE.

B. SPICE Simulation for the Discharge Current

Fig. 6 illustrates the effect of the arc length on the current waveform. It shows SPICE-simulated discharge currents for a 5-kV charge voltage. An arc length of 1.1-mm equals the Paschen length, such a discharge current would be expected at high humidity and slow approach speeds. A more typical value at moderate approach speeds is 0.7 mm. At this value, the rise time will be somewhat similar to the rise time of an ESD, as given in the IEC 61000–4-2 standard (about 850 ps). A more extreme case is given by the 0.3-mm arc length simulation. Very dry air and high approach speeds might lead to such a discharge. The simulated current peak value is 26 A and the rise time is 150 ps.

C. Reimport of Currents Into CST

For obtaining the fields, one needs to reimport the discharge current into the full-wave model as the excitation waveform. This is discussed and validated in the second case example.

D. Validation by Measurement Results

The current into the large ground plane was measured using an ESD current sensor, as described in [3]. In Fig. 7, the SPICEsimulated discharge currents are compared to the measured data for different approach speeds. Even if the exact approach speed or arc lengths are not known, it shows that the ranges of arc lengths used in the simulation are representative for discharge currents obtained in the experiment. A more in-depth comparison based on measured arc length values can be found in [13].

IV. CASE 2: ESD GENERATOR DISCHARGE INTO A SMALL PRODUCT

A. Z11 Between the Tip of the ESD Generator and the DUT Surface

This case simulates a discharge into an MP3 player, a small, nongrounded DUT. The whole geometry is shown in Fig. 8. The MP3 player model includes the main blocks of the DUT similar to [24]. In brief, the major blocks of the player (metal frame, battery, display, PCBs) are modeled as metal blocks connected at the locations of connectors and frame connection points.

The DUT is placed on a dielectric sheet above a larger ground plane. This forms a capacitor having a capacitance of about 25 pF, leading to a higher value of Z11 at lower frequencies. The value for Z11 was obtained, as shown in Fig. 9. The comparison between Z11 of the ESD generator and the large ground plane and Z11 of the ESD generator with the MP3 player is shown in Fig. 10. It mainly shows the smaller capacitance at lower frequencies; at higher frequencies the impedance of the 25-pF capacitor formed by the player against the ground plane is lower than the source impedance of the ESD generator, thus, the impedance in case 2 is similar to the impedance seen in case 1, the discharge to a large ground plane.

B. SPICE Simulation for the Discharge Current

The Z11 defined between the discharge tip and the MP3 player was transformed into a subcircuit using Broadband SPICE. The subcircuit combined with the arc model gave the simulated discharge current for different user-defined charging voltage and arc length. The simulated discharge current at the 5-kV charge voltage with different arc lengths is shown in Fig. 11.

The obtained peak values and rise times are tabulated in Table II. The arc length has a very strong effect on the parameters shown, especially, the current derivative.

C. Reimport of Currents Into CST

To obtain transient fields, the current waveform obtained from the SPICE simulation is reimported into CST as the excitation waveform. The current source port is placed between the two points that had been previously selected to define the impedance port to calculate Z11 . One check is worthwhile: If the Z11 representation used in SPICE would perfectly match the Z11 from the FD full-wave simulation, then the port voltage obtained during the full-wave simulation using the reimported current would match the port voltage (= voltage across the arc) in the SPICE simulation.

For case 2, the SPICE-simulated current was imported back to the CST model as the current source. The comparison of the port voltage in the SPICE model and the port voltage in the CST model in Fig. 12 shows a good match.

The simulation using the reimported current allows simulating the fields within and around the MP3 player by placing appropriate monitor probes. If these probes are placed close to the metallic surfaces of the MP3 player, then they represent the surface current densities and the displacement current densities, which can be used to estimate the coupling into bond wires of an IC, traces, and flex cables for predicting ESD upset threshold levels. Before current and field results are shown, the measurement methods are introduced.

D. Validation by Measurement Results

The current was injected into the small product, and the magnetic field was measured. To capture the current injected into the MP3 player, an F-65 (1 MHz–1 GHz) current probe was used, as shown in Fig. 13. The magnetic field was measured using a small shielded loop and a Tektronix 7404 (4 GHz BW, 20 GS/s) oscilloscope.

At 5-kV charge voltage, a NoiseKen ESD generator was discharged into the player. The player was placed above a large GND plane with a dielectric sheet between them. Figs. 13 and 14 illustrate the setup.

The relationship between approach speed, humidity, and arc length is not of deterministic nature, but given by the influence of the humidity on the statistical time lag [13]. Thus, on an average, one will observe shorter arc lengths with increasing approach speeds for a given charge voltage. For achieving short arc length discharges without reducing the humidity, the surface had been cleaned using alcohol and fast approach speeds have been used, longer arc lengths are achieved by slow approach speeds. Shown are examples of the captured waveforms for different approach speeds.

1) Measured Discharge Current: The current clamp’s frequency response falls off above 1-GHz bandwidth, thus, the fastest rise time of a step response signal would be approximately 300 ps. Fig. 15 shows the measured discharge currents for different approach speeds.

The simulation results are compared to the measured results for verification. The fast rise time result is shown in Fig. 16. The simulated discharge current for a 0.3-mm arc length and 5-kV charging voltage gives a discharge current with a rise time of about 200 ps and a peak value of 21 A. The measured discharge current has a rise time of about 300 ps and a peak magnitude of about 22 A. The difference can be explained by the limited bandwidth of the F-65 clamp. Due to the difficulty in measuring arc length, we can only approximately compare measured and simulated results. Nevertheless, the comparison shows that the simulated and measured data are within the same ranges.

In Figs. 17 and 18, the comparison of simulation discharge current for 0.7-mm and 1.1-mm arc lengths is shown. They match well with the measured results.

2) Measured Magnetic Field: This is to confirm the last step of the process: Injecting the SPICE simulated current back into the full-wave simulation for obtaining fields. A shielded loop was placed 5 cm away from the product (see Fig. 14). A deconvolution was performed to obtain the field strength from the captured voltage at the probe output. The deconvolution is mainly an integration process, having two deviations from the ideal integration. At lower frequencies, high-pass filtering is performed to avoid the accumulation of the oscilloscope’s small but relevant dc offset during the integration. Second, at higher frequencies, the self-inductance of the probe in conjunction with the 50-Ω load, leads to a self-integration, thus, no external integration is needed above 3 GHz. The resulting magnetic fields are shown in Fig. 19. The data match well. The measured rise time is about 250 ps. By using the SPICE model, one can estimate the arc length from the rise time. Repeated simulations indicate an arc length of about 0.4 mm. The Paschen length for 5 kV is about 1.1 mm at sea-level air pressure. Thus, the combination of the speed of approach and the statistical time lag reduced the arc length in this measurement to 35% of the Paschen value, leading to a very fast rising ESD current.

Several field probes were placed in the full-wave model to monitor the magnetic field. A probe that is 5 cm away from the discharge point gives the H-field data shown in Fig. 19. The result matches well with the measured data.

V. DISCUSSION

The methodology allows predicting the currents and fields in and around a product. There are three types of limitations in the methodology.

The most obvious one results from the limited ability of simulating details in the product and within the ESD generator. As with every simulation, the number of unknowns and the ratio of the smallest to the largest detail will limit the size of the model. The methodology allows circumventing this at least partially, especially for small products. If the product is small, then the fields inside the product will be dominated by the fields caused from the injected current and not by fields directly coupling from the body of the ESD generator. Those fields would especially be significant in the contact mode, in which the field components that are greater than 1 GHz are often caused by the rapid voltage breakdown in the gas-filled relay that initiates the discharge. As this analysis is for an air discharge, one will find the strongest high-frequency components directly at the arc, as with further distance from the arc high-frequency components will be attenuated by both frequency-dependent loss and radiation. If the fields are dominated by the injected current, then one can use a relatively simple model of the product just to determine the current, but in the last step, in which the current is reinjected into the product, a more complex model of the product can be used, but a very simple model of the ESD generator (and a forced current).

The second limitation results from the need for providing the arc length for the arc resistance calculation. Although possible, arc length measurements are difficult to implement. In a simulation, we suggest the following approach. At first, an arc length should be selected that leads to an air-discharge current that is similar to the contact-mode discharge current, as specified in the IEC 61000–4-2 standard. For 5 kV, this is about 0.8-mm arc length. Values for other voltages can be found in [13]. As a very slow rising current, the Paschen value can be selected, leading to discharges of lower severity and as extremely fast rising current; a value of about 30% of the Paschen length is suggested. This value is based on experimental evidence. In measurements that captured the arc length [13], we found it possible even under very dry air and clean surface conditions to obtain arc lengths of less than 30% of the Paschen value.

The third limitation is related to the stability of the TD SPICE simulation. In this simulation, a very rapid change of resistance is combined with a SPICE impedance model created from fullwave simulation. If instabilities occur, one should inspect the SPICE model for passivity and causality, in addition, one can simulate the discharge using longer arc lengths first, as these show a slower change of the arc resistance.

The main application of this model lies in the simulation of ESD to products. For example, it is known that the arc length tends to be small for fast approach speeds in dry air. The short arc length leads to fast rise times and high peak values. Using this model, one can quantify the fields inside a product for different arc lengths. Further applications are the simulation of grounding conditions of products on the arc, and thus, the current. Further, the model can be extended to the case of secondary breakdown, e.g., an ESD occurs to an ungrounded metal part leading to a second discharge from this ungrounded part to the main part of the DUT.

VI. CONCLUSION

This paper proposes a method for simulating an ESD generator discharging in air-discharge mode into a product. The linear and the nonlinear part of the problem are separated to simulate the linear part in a full-wave solution and the nonlinear arc in SPICE. The SPICE results are reimported into the full-wave problem as the excitation. This allows the fields inside a product during an air discharge to be obtained. The method has been verified by the comparison of simulated current and transient field results with measurements.

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PB2010.11 Effects of TVS Integration on System Level ESD Robustness

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50 Words Abstract – Higher integration of Transient Voltage Suppression (TVS) functionality into ASIC I/O cells implies lower system costs. But as the ESD pulse is directed deeper into the system, migrating the TVS clamping function from the periphery of the system to a central ASIC may actually reduce the system’s ESD robustness. ESD current reconstruction scanning can be used to trace the current path on a PCB, and possibly within an IC. The article compares the current spreading during and ESD for different ESD protection methods.

I. Introduction

The inevitable trend in system design for ESD robustness has tended toward higher integration of Transient Voltage Suppression (TVS) functionality into ASIC I/O cells. In low cost systems where the entire device has been distilled into a single “System on a Chip” (SOC) and perhaps an additional DDR memory device and a power supply and clock generator, the addition of discrete TVS devices near I/O connector ports can add appreciable costs to the parts count and in the case of a system with just a few USB or Ethernet ports, can double the assembly/placement costs for the entire PCB.

By shifting the ESD clamping into the highly integrated SOC these costs can be eliminated, however, this requires that the aggressor ESD pulse must be allowed to travel deep into the system where new susceptibilities to system upset may be triggered. While the cost is reduced, and the system ESD level survivability (resistance to permanent damage and hard failures) may be retained, the relocation of TVS clamping from the periphery of the system PCB to a central ASIC may actually reduce the system’s ESD robustness and resistance to upset and soft errors.

This paper demonstrates an improved methodology for quantitatively analyzing and potentially predicting robustness of different system level ESD protection circuits, topologies and layout permutations on a given product. The methodology uses current reconstruction scanning, a methodology to observe the ESD current spreading in a time resolved fashion [2, 5, 6].

II. Measurement Techniques

The objective of this analysis is to characterize what happens throughout the PCB, at various “nearby” nodes when an ESD pulse enters the system through an I/O port, or other means.

Two different analysis techniques are used:

Susceptibility scanning: This determines the local susceptibility of circuits to field injected noise, e.g. ESD like pulses

Current reconstruction scanning: This determines in a time resolved fashion the spread of current after an ESD strike on the system

What is needed is an analysis technique to quantitatively identify all areas of susceptibility on a board, and then relate that to potential I/O entry vectors. This makes it possible for the designer to correlate and potentially predict how a system level IEC61000-4-2 ESD strike may cause a system upset, and provides a method for objectively comparing improvements to the system design.

For example, a designer with a prototype failing minimum system level ESD testing may need to compare different types of discrete TVS clamp solutions near the I/O connector, versus a costreduced alternative I/O cell integrated into an interior system ASIC.

It is a common practice to place ESD protection as close to the perimeter of the system as possible in order to shunt the energy back to the chassis and out of the system as soon as possible.

However, even in the case of a well protected system, upset in an apparently unrelated subsystem may still occur (i.e. an ESD strike to a USB port upsets a PC’s video memory) making blind debug of the system upset extremely problematic.

By combining ESD susceptibility scanning [5] with a new reciprocal technique for “current spread” scanning [1,3,6], a matrix of potentially related aggressor and victim nodes can be identified and provide a comparative focal point for iterative improvement in design robustness.

A. Susceptibility Scanning Testing

1. Equipment

The scanning setup comprises a robotic 3D scanner with test control computer, Transmission Line Pulser (TLP), and DSO for data capture (See Figure 1).

We used the SmartScan system from Amber Precision Instruments [2]. For this test a 10mm horizontal loop probe was used for field injection (Figure 2). The maximum TLP charge level is set be a non-destructive 1kV, with a modified network to minimize the falling edge rate applied (Figure 2).

The scanning resolution is 5 by 5 mm and can traverse the entire system PCB area. When desirable, the system PCB can be mounted in as much of the system level enclosure as desired for closer relation to system level tests. The primary objective here is to probe the extent of the PCB design, routing and components, given a fixed case and mounting enclosure for the product. Certain systems, especially small handheld devices may dramatically hinder access to stacked PCBs or grounding brackets and consideration should be given to the extents of the scans.

2. Procedure

The iterative scanning process traverses a predetermined area of interest on the PCB, alternately injecting a pulse, and then checking the system under test for continued operation. The initial pulse is 4kV until a system upset is detected and the stepped failure level is then tested at the failure location and recorded. In this particular example, when the router operation was upset (reset) due to pulse injection, the router would stop replying to HTTP requests for the configuration setup page (a typical “recoverable loss of function” criterion as might be used in standard system level ESD testing).

Failure criteria are determined on a system-by-system basis, as they would be with a manual system level ESD testing. In this particular example, the test system repeatedly sends Ethernet requests to the Device Under Test’s (DUT’s) configuration stack. When the upset occurred in this case, the DUT would hang and stop responding to requests. At this point, the DUT would be reset by the system test controller and move on to the next test point on the grid.

B. “Current Reconstruction” Testing

In a corollary to the Susceptibility Scanning, the same TLP waveform is injected into a particular I/O port of interest, and the scanning probe is used to “listen” to the PCB.

At each point on the defined grid, the sensed H-field is recorded and processed at a low, non-destructive level creating a new surface plot of energy flow due to the injected pulse. The sensing methodology must take care to sufficiently shield the probe from E-field pickup, and/or remove this component from the measurement capture. [1,7] This does not actually require the system to be functioning, and it may be performed with and without power depending on the failure mechanism to be analyzed. However, the pulse needs to be large enough to trigger the non-linear ESD protection devices, but not so energetic that it causes permanent damage, or a “hard failure” of the system. This creates a great deal of data which can be postprocessed for myriad perspectives on the design.

By trapping the entire pulse at each position, a time variant surface plot can be reconstructed by windowing an interval of interest at various times during the TLP (or IEC or HMM) pulse applied. By post-processing multiple frames with incremental windowing of the pulse, an animated “movie” of the ESD current spreading can be assembled.

In Figure 6, the obvious entry vector of the residual current from the USB port to the SOC ASIC is seen in the upper left corner at the connector where a TVS clamp shunts much of the pulse.

Additional analysis can contrast the current reconstruction path with and without a discrete TVS clamp installed. Without the clamp installed (Figure7a), the current flowing in the signal traces is much higher than with the clamp (Figure 7b), and can be seen coupling into other unrelated, nearby nodes (blue circles.) This may indicate a link into other subsystems if these coupled nodes are related to other susceptible areas identified in the susceptibility scanning.

This potential problem can then be evaluated or eliminated from consideration by overlaying these plots, and comparing the resulting plots of different selections of TVS devices, layouts or ASIC revisions to determine the ESD robustness of each solution.

For example, the original Susceptibility Scan from Figure 5 is shown here expanded in Figure 8.

This plot is then overlaid with the Current Reconstruction Scanning plot of a particular USB port (Figure 9).

This results in a graphical representation of ESD susceptible areas which can be “reached” externally from that particular USB port (Figure 10).

Repeating this procedure for each I/O port (or other potential system level ESD injection point) yields a new plot (and associated peak susceptibility values and positions on the PCB) for each port or injection point of the system. This does not replace IEC61000- 4-2 testing, for example, but rather aides in the debugging of the design when an unexpected susceptibility is discovered.

In Figure 10, the method correctly identifies that the USB pins of the ASIC are of course susceptible to strikes on the USB port. Here, traditional TVS clamping methods can be expected to improve overall system robustness. However, if the scan overlay indicated that a sensitive DRAM or CLOCK pin was within the area of current spreading from the USB injection port, then the robustness improvement solution might simply require a reoriented layout of the USB and CLOCK/DRAM traces.

Such areas can also unexpectedly be aggravated by migrating the system level ESD protection into the ASIC by driving a larger residual ESD pulse current deeper into the system. The overlaid susceptibility plots for the integrated and external TVS solutions in Figure 7a and 7b can be compared to ensure that the integrated clamping solution does not create other robustness issues elsewhere in the system.

This analysis methodology can be used to help identify, compare and grade the relative improvement of each protection solution to problems at the system level.

Acknowledgements

The authors would like to thank Michael Hopkins of Amber Precision Instruments for his assistance.